Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. This action is in response to application amendments filed on 9-16-2025.
2. Claims 1 - 16 are pending. Claims 1, 9 have been amended. Claims 1, 9 are independent. This application was filed on 9-27-2023.
Response to Arguments
3. Applicant’s arguments, see Arguments/Remarks Made in an Amendment, filed 9-16-2025 with respect to the rejection(s) under Haukness in view of JI and further in view of Weinert have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Haukness in view of JI and further in view of Weinert and JP3639786.
A. Applicant argues on page 6 of Remarks: ... "encrypting and mapping the first channel row address through a key-based mapping method to obtain a second channel row address that corresponds to the first channel row address within a predetermined address range, wherein a channel corresponding to the second channel row address is different from a channel corresponding to the first channel row address.".
The Examiner respectfully disagrees. JI discloses encrypting and mapping a first channel row address to obtain a second row address. The first row address has a correlation to the second address. (see JI paragraph [0048]: The first logic processing and the second logic processing may be mutual reverse processing. The first logic processing and the second logic processing may be the same or different encryption processing, and configured to encrypt the corresponding memory array, or portion thereof, so that the each storage unit of the semiconductor memory, such as a memory array, a bank, portion of the memory array having particular row addresses or column addresses can be independently encrypted using the mapping factor MF0, or portion thereof.)
And, JP3639786 prior art discloses separate and unique channels (first channel, second channels; 2 separate and distinct communication paths) enabling access to row addresses. (see JP3639786 paragraph [0027]: This unidirectional behavior allows the memory decoder to establish a unique circuit path to each memory cell, individually (for reading and writing) regardless of the state of all other cells.; (first channel: first unique path; second channel: second unique path); paragraphs [0131]-[0134]: there are two paths to each bit line, one from the word line in the conductor layer immediately below and one from the word line in the conductor layer immediately above. In order to avoid ambiguity, it must be ensured that only one of the two possible paths is enabled. This is easily accomplished by dividing the word line into a “first set” (first channel) and a “second set” (second channel); (two distinct channels).; two sets of word lines (FIG. 10 (b)), all bit lines (first channel, second channel) will have a memory cell with the row leading to it selected.)
B. Applicant argues on page 7 of Remarks: ... Haukness does not teach or suggest obtaining a second channel row address where "a channel corresponding to the second channel row address is different from a channel corresponding to the first channel row address.".
The Examiner respectfully disagrees. JI discloses encrypting and mapping a first channel row address to obtain a second row address. The first row address has a correlation to the second address. (see JI paragraph [0048]: The first logic processing and the second logic processing may be mutual reverse processing. The first logic processing and the second logic processing may be the same or different encryption processing, and configured to encrypt the corresponding memory array, or portion thereof, so that the each storage unit of the semiconductor memory, such as a memory array, a bank, portion of the memory array having particular row addresses or column addresses can be independently encrypted using the mapping factor MF0, or portion thereof.)
And, JP3639786 prior art discloses separate and unique channels (first channel, second channels; 2 separate and distinct communication paths) enabling access to row addresses. (see JP3639786 paragraph [0027]: This unidirectional behavior allows the memory decoder to establish a unique circuit path to each memory cell, individually (for reading and writing) regardless of the state of all other cells.; (first channel: first unique path; second channel: second unique path); paragraphs [0131]-[0134]: there are two paths to each bit line, one from the word line in the conductor layer immediately below and one from the word line in the conductor layer immediately above. In order to avoid ambiguity, it must be ensured that only one of the two possible paths is enabled. This is easily accomplished by dividing the word line into a “first set” (first channel) and a “second set” (second channel); (two distinct channels).; two sets of word lines (FIG. 10 (b)), all bit lines (first channel, second channel) will have a memory cell with the row leading to it selected.)
C. Applicant argues on page 7 of Remarks: ... Haukness provides no mechanism by which a channel corresponding to a second channel row address would be different from a channel corresponding to a first channel row address.
The Examiner respectfully disagrees. JI discloses encrypting and mapping a first channel row address to obtain a second row address. The first row address has a correlation to the second address. (see JI paragraph [0048]: The first logic processing and the second logic processing may be mutual reverse processing. The first logic processing and the second logic processing may be the same or different encryption processing, and configured to encrypt the corresponding memory array, or portion thereof, so that the each storage unit of the semiconductor memory, such as a memory array, a bank, portion of the memory array having particular row addresses or column addresses can be independently encrypted using the mapping factor MF0, or portion thereof.)
And, JP3639786 prior art discloses separate and unique channels (first channel, second channels; 2 separate and distinct communication paths) enabling access to row addresses. (see JP3639786 paragraph [0027]: This unidirectional behavior allows the memory decoder to establish a unique circuit path to each memory cell, individually (for reading and writing) regardless of the state of all other cells.; (first channel: first unique path; second channel: second unique path); paragraphs [0131]-[0134]: there are two paths to each bit line, one from the word line in the conductor layer immediately below and one from the word line in the conductor layer immediately above. In order to avoid ambiguity, it must be ensured that only one of the two possible paths is enabled. This is easily accomplished by dividing the word line into a “first set” (first channel) and a “second set” (second channel); (two distinct channels).; two sets of word lines (FIG. 10 (b)), all bit lines (first channel, second channel) will have a memory cell with the row leading to it selected.)
D. Applicant argues on page 8 of Remarks: ... does not teach remapping addresses across different channels.
The Examiner respectfully disagrees. JI discloses encrypting and mapping a first channel row address to obtain a second row address. The first row address has a correlation to the second address. (see JI paragraph [0048]: The first logic processing and the second logic processing may be mutual reverse processing. The first logic processing and the second logic processing may be the same or different encryption processing, and configured to encrypt the corresponding memory array, or portion thereof, so that the each storage unit of the semiconductor memory, such as a memory array, a bank, portion of the memory array having particular row addresses or column addresses can be independently encrypted using the mapping factor MF0, or portion thereof.)
And, JP3639786 prior art discloses separate and unique channels (first channel, second channels; 2 separate and distinct communication paths) enabling access to row addresses. (see JP3639786 paragraph [0027]: This unidirectional behavior allows the memory decoder to establish a unique circuit path to each memory cell, individually (for reading and writing) regardless of the state of all other cells.; (first channel: first unique path; second channel: second unique path); paragraphs [0131]-[0134]: there are two paths to each bit line, one from the word line in the conductor layer immediately below and one from the word line in the conductor layer immediately above. In order to avoid ambiguity, it must be ensured that only one of the two possible paths is enabled. This is easily accomplished by dividing the word line into a “first set” (first channel) and a “second set” (second channel); (two distinct channels).; two sets of word lines (FIG. 10 (b)), all bit lines (first channel, second channel) will have a memory cell with the row leading to it selected.)
E. Applicant argues on page 8 of Remarks: ... Ji provides no mechanism or suggestion that its mapping would cause an address originally corresponding to one channel to be redirected to a different channel and instead the encryption processing maintains the address within the same memory structure.
The Examiner respectfully disagrees. JI discloses encrypting and mapping a first channel row address to obtain a second row address. The first row address has a correlation to the second address. (see JI paragraph [0048]: The first logic processing and the second logic processing may be mutual reverse processing. The first logic processing and the second logic processing may be the same or different encryption processing, and configured to encrypt the corresponding memory array, or portion thereof, so that the each storage unit of the semiconductor memory, such as a memory array, a bank, portion of the memory array having particular row addresses or column addresses can be independently encrypted using the mapping factor MF0, or portion thereof.)
And, JP3639786 prior art discloses separate and unique channels (first channel, second channels; 2 separate and distinct communication paths) enabling access to row addresses. (see JP3639786 paragraph [0027]: This unidirectional behavior allows the memory decoder to establish a unique circuit path to each memory cell, individually (for reading and writing) regardless of the state of all other cells.; (first channel: first unique path; second channel: second unique path); paragraphs [0131]-[0134]: there are two paths to each bit line, one from the word line in the conductor layer immediately below and one from the word line in the conductor layer immediately above. In order to avoid ambiguity, it must be ensured that only one of the two possible paths is enabled. This is easily accomplished by dividing the word line into a “first set” (first channel) and a “second set” (second channel); (two distinct channels).; two sets of word lines (FIG. 10 (b)), all bit lines (first channel, second channel) will have a memory cell with the row leading to it selected.)
F. Applicant argues on page 9 of Remarks: ... Weinert fails to cure the above-discussed deficiencies of Haukness and Ji.
The Examiner respectfully disagrees. Weinert is not used to disclose the indicated claim limitation(s). The Office Action indicates the claim limitation(s) Weinert is used to reject.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1 - 4, 9 - 12 are rejected under 35 U.S.C. 103 as being unpatentable over Haukness et al. (Patent No. WO 2023/018653 A1) in view of JI et al. (US PGPUB No. 20210182205) in view of JP3639786 et al. (Patent No. JP 3639786 B2) and in view of Weinert et al. (Patent No. EP 3021516 A1).
Regarding Claims 1, 9, Haukness discloses a method for remapping a row address on a multichannel DIMM, applied to a memory controller and a system for remapping a row address on a multichannel DIMM, the system comprises a multichannel DIMM and a memory controller, the memory controller comprises: a channel row address generator, config, comprising:
a) receiving a first read/write access address and extracting a first channel row address from the first read/write access address by the memory controller; (see Haukness paragraph [0013]: memory controller 102 includes a memory interface 113 with data interface circuitry 114 and command/address (C/A) interface circuitry 116. One embodiment of the memory controller 102 includes dedicated write data transmit circuits for coupling to dedicated write data paths of the signaling media 106, and dedicated read data receivers for coupling to dedicated read data paths of the signaling media 106.; paragraph [0023]: A row address decoder 250 is also provided by the CA path circuitry 213 to extract the row address information for the given memory access operation, where it is fed to memory core row decoder circuits 214; (first read/write access address; extract row); paragraph [0013]: One embodiment of the memory controller 102 includes dedicated write data transmit circuits for coupling to dedicated write data paths of the signaling media 106, and dedicated read data receivers for coupling to dedicated read data paths of the signaling media 106. Additional interfaces may also be included to support additional memory channels, each with similar data and C/A interface circuits. (analogous to DIMM memory interface with multiple channels))
c) forming a second read/write access address based on the second channel row address and unextracted address information in the first read/write access address, and performing read/write access to the DIMM based on the second read/write access address. (see Haukness paragraph [0013]: memory controller 102 includes a memory interface 113 with data interface circuitry 114 and command/address (C/A) interface circuitry 116. One embodiment of the memory controller 102 includes dedicated write data transmit circuits for coupling to dedicated write data paths of the signaling media 106, and dedicated read data receivers for coupling to dedicated read data paths of the signaling media 106.; paragraph [0023]: A row address decoder 250 is also provided by the CA path circuitry 213 to extract the row address information for the given memory access operation, where it is fed to memory core row decoder circuits 214; (second read/write access address; extract row)
Haukness does not specifically disclose for b) encrypting and mapping the first channel row address to obtain a second channel row address.
However, JI discloses:
b) encrypting and mapping the first channel row address through a method to obtain a second channel row address that corresponds to the first channel row address within a predetermined address range. (see JI paragraph [0048]: The first logic processing and the second logic processing may be mutual reverse processing. The first logic processing and the second logic processing may be the same or different encryption processing, and configured to encrypt the corresponding memory array, or portion thereof, so that the each storage unit of the semiconductor memory, such as a memory array, a bank, portion of the memory array having particular row addresses or column addresses can be independently encrypted using the mapping factor MF0, or portion thereof.)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Haukness for b) encrypting and mapping the first channel row address to obtain a second channel row address as taught by JI. One of ordinary skill in the art would have been motivated to employ the teachings of JI for the enhanced security of a system that enables encryption of data processing parameters. (see JI paragraph [0048])
Haukness in view of JI does not specifically disclose for b) wherein a channel corresponding to the second channel row address is different from a channel corresponding to the first channel row address.
However, JP3639786 discloses for b) wherein a channel corresponding to the second channel row address is different from a channel corresponding to the first channel row address. (see JP3639786 paragraph [0027]: This unidirectional behavior allows the memory decoder to establish a unique circuit path to each memory cell, individually (for reading and writing) regardless of the state of all other cells.; (first channel: first unique path; second channel: second unique path); paragraphs [0131]-[0134]: there are two paths to each bit line, one from the word line in the conductor layer immediately below and one from the word line in the conductor layer immediately above. In order to avoid ambiguity, it must be ensured that only one of the two possible paths is enabled. This is easily accomplished by dividing the word line into a “first set” (first channel) and a “second set” (second channel); two distinct channels).; two sets of word lines (FIG. 10 (b)), all bit lines (first channel, second channel) will have a memory cell with the row leading to it selected.)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Haukness in view of JI for b) wherein a channel corresponding to the second channel row address is different from a channel corresponding to the first channel row address as taught by JP3639786. One of ordinary skill in the art would have been motivated to employ the teachings of JP3639786 for the enhanced security of providing unique paths for accessing row address information within a data structure. (see JP3639786 paragraph [0027])
Haukness in view of JI in view of JP3639786 does not specifically disclose encryption through key-based mapping.
However, Weinert discloses wherein encryption through a key-based mapping method. (see Weinert paragraph [0028]: the key derivation a one-way function, like a hash function, is applied to the transaction identifier. The one-way function to be used may be configured based on a function parameter. Multiple different one-way functions may be selected in the server. Furthermore, in sub step 12, the result of the applied one-way function is combined, via XOR, DES or 3DES, with the master key CMK, thereby deriving a modified master key CMK' for the second key derivation sub step 14.; (key derivation one-way function, key based mapping))
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Haukness in view of JI in view of JP3639786 for encryption through key-based mapping as taught by Weinert. One of ordinary skill in the art would have been motivated to employ the teachings of Weinert for the flexibility of a system that enables multiple functional techniques such as key-based one-way derivation function to be utilized in data processing in a network environment. (see Weinert paragraph [0028])
Regarding Claims 2, 10, Haukness-JI-Weinert-JP3639786 discloses the method for remapping the row address on the multichannel DIMM of claim 1 and the system for remapping the row address of claim 9, wherein the first channel row address and the second channel row address include a channel selection signal and a row address. (see Haukness paragraph [0029]: selector circuitry 212 of FIG. 2 was disposed in the internal signaling interface circuitry 211 (FIG. 2) to select between activating read and write signaling paths at the bank group level, the architecture of FIG. 4 incorporates per-bank selection circuitry 402 that is distributed within enhanced memory core circuitry 404 in a manner that allows for selectively activating read and write signaling paths on a per-bank basis to achieve concurrent memory accesses to different banks within a same or different bank group within the memory core circuitry 404)
JI discloses mapping addresses as stated in Claim 1 above.
Regarding Claims 3, 11, Haukness-JI-Weinert-JP3639786 discloses the method for remapping the row address on the multichannel DIMM of claim 1 and the system for remapping the row address of claim 9, wherein the unextracted address information includes one or more of the following: a column address, a chip selection signal for memory rank, a chip selection signal for 3D stacked chip, a memory bank address, and a rank where the memory bank is located. (see Haukness paragraph [0029]: selector circuitry 212 of FIG. 2 was disposed in the internal signaling interface circuitry 211 (FIG. 2) to select between activating read and write signaling paths at the bank group level, the architecture of FIG. 4 incorporates per-bank selection circuitry 402 that is distributed within enhanced memory core circuitry 404 in a manner that allows for selectively activating read and write signaling paths on a per-bank basis to achieve concurrent memory accesses to different banks within a same or different bank group within the memory core circuitry 404; (bank address); paragraph [0023]: received CA signals are fed to a column address decoder 242 which extracts column address information for a given memory access operation. The column address information is then fed to an input of a column multiplexer 244 which includes multiple outputs for read column information routed along the dedicated read column path RCOL PERI and write column information along the dedicated write column path WCOL PERI; (selected: memory bank address, column address))
Regarding Claims 4, 12, Haukness-JI-Weinert-JP3639786 discloses the method for remapping the row address on the multichannel DIMM of claim 1 and the system for remapping the row address of claim 9.
Haukness does not specifically disclose a key-based one-way derivation function.
However, Weinert discloses wherein the key-based mapping method includes a key-based one-way derivation function. (see Weinert paragraph [0028]: the key derivation a one-way function, like a hash function, is applied to the transaction identifier. The one-way function to be used may be configured based on a function parameter. Multiple different one-way functions may be selected in the server. Furthermore, in sub step 12, the result of the applied one-way function is combined, via XOR, DES or 3DES, with the master key CMK, thereby deriving a modified master key CMK' for the second key derivation sub step 14.)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Haukness for a key-based one-way derivation function as taught by Weinert. One of ordinary skill in the art would have been motivated to employ the teachings of Weinert for the flexibility of a system that enables multiple functional techniques such as key-based one-way derivation function to be utilized in data processing in a network environment. (see Weinert paragraph [0028])
6. Claims 5, 6, 13, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Haukness in view of JI et al. and further in view of Weinert and JP3639786 and Woo et al. (Patent No. WO 2023/027984 A2) and Zheng et al. (Patent No. CN 115497534 A).
Regarding Claims 5, 13, Haukness-JI-Weinert-JP3639786 discloses the method for remapping the row address on the multichannel DIMM of claim 4 and the system for remapping the row address of claim 12, wherein the encrypting and mapping the first channel row address through a key-based mapping method to obtain a second channel row address that corresponds to the first channel row address within a predetermined address range.
Haukness does not specifically disclose for a) reversing first channel row address and performing XOR process on reversed first channel row address, and for c) performing XOR process on shifted value with a second key to obtain second channel row address.
However, Zheng discloses:
a) reversing the first channel row address and performing XOR process on the reversed first channel row address with a first key to obtain a process result; c) performing XOR process on the shifted value with a second key to obtain the second channel row address. (see Zheng page 9: Inverter (246-a to 246-m) can output (or configured as output) target row address REF_ADDR or reverse target row address as refresh row address (RRAa to RRAm) according to (or based on) intermediate signal (Sa to Sm). For example, the inverters (246-a to 246-m) may perform (or are configured to perform) XOR operations on the intermediate signals (Sa to Sm) and the target row address REF_ADDR.)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Haukness for a) reversing first channel row address and performing XOR process on reversed first channel row address, and for c) performing XOR process on shifted value with a second key to obtain second channel row address as taught by Zheng. One of ordinary skill in the art would have been motivated to employ the teachings of Zheng for the flexibility of a system that enables the manipulation of multiple data processing parameters such as memory row addressing and memory column addressing in the processing of memory type objects within a network environment. (see Zheng page 9)
Haukness does not specifically discloses for b) shifting the process result to obtain a shifted value.
However, Woo discloses:
b) shifting the process result to obtain a shifted value. (see Woo paragraph [0121]: the mapping, by the first DRAM device, of the first row address to the first internal row address uses a first linear feedback shift register (LFSR) function, and the mapping, by the second DRAM device, of the second row address to the second internal row address uses a second LFSR function, where the first LFSR function and the second LFSR function are configured to)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Haukness for b) shifting the process result to obtain a shifted value as taught by Woo. One of ordinary skill in the art would have been motivated to employ the teachings of Woo for the flexibility of a system that enables multiple data manipulation techniques such as a linear feedback register to be utilized in data processing within a network environment. (see Woo paragraph [0121])
Regarding Claims 6, 14, Haukness-JI-Weinert-JP3639786-Woo-Zheng discloses the method for remapping the row address on the multichannel DIMM of claim 5 and the system for remapping the row address of claim 13.
Haukness does not specifically disclose shifting process result through a linear feedback shift register.
However, Woo discloses wherein shifting the process result includes shifting the process result through a linear feedback shift register. (see Woo paragraph [0121]: the mapping, by the first DRAM device, of the first row address to the first internal row address uses a first linear feedback shift register (LFSR) function, and the mapping, by the second DRAM device, of the second row address to the second internal row address uses a second LFSR function, where the first LFSR function and the second LFSR function are configured to)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Haukness for shifting process result through a linear feedback shift register as taught by Woo. One of ordinary skill in the art would have been motivated to employ the teachings of Woo for the flexibility of a system that enables multiple techniques such as a linear feedback shift register to be utilized in data processing within a network environment. (see Woo paragraph [0121])
7. Claims 7, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Haukness in view of JI et al. and further in view of Weinert and JP3639786 and Woo and Zheng and Wei et al. (US PGPUB No. 20140079215).
Regarding Claims 7, 15, Haukness-JI-Weinert-JP3639786-Woo-Zheng discloses the method for remapping the row address on the multichannel DIMM of claim 5 and the system for remapping the row address of claim 14.
Haukness does not specifically disclose selecting a random number as initial value of the linear feedback shift register to generate a random number with predetermined bits as the first key.
However, Wei discloses wherein further comprising when the memory controller is powered on, selecting a random number as initial value of the linear feedback shift register to generate a random number with predetermined bits as the first key, and selecting another random number with predetermined bits as the second key. (see Wei paragraph [0010]: means for obtaining a predetermined number of input bits and means for generating at least one multi-byte pseudo-random number based in part on the input bits, wherein each byte of the at least one multi-byte pseudo-random number provides an index to a different one of a plurality of optimized substitution boxes, ... means for obtaining a value from each of the plurality of optimized substitution boxes using a corresponding byte of the at least one multi-byte pseudo-random number, and means for generating at least one key value based on the values obtained from the optimized substitution boxes, wherein the key value is used in connection with the means for applying the ZUC cryptographic algorithm to the data stream.; (generate first key, generate second key))
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Haukness for selecting a random number as initial value of the linear feedback shift register to generate a random number with predetermined bits as the first key as taught by Wei. One of ordinary skill in the art would have been motivated to employ the teachings of Wei for the flexibility of a system that enables multiple techniques to be utilized such as random numbers and feedback registers to generate keys. (see Wei paragraph [0010])
Haukness does not specifically disclose a linear feedback shift register.
However, Woo discloses wherein a linear feedback shift register. (see Woo paragraph [0121]: the mapping, by the first DRAM device, of the first row address to the first internal row address uses a first linear feedback shift register (LFSR) function, and the mapping, by the second DRAM device, of the second row address to the second internal row address uses a second LFSR function, where the first LFSR function and the second LFSR function are configured to)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Haukness for a linear feedback shift register as taught by Woo. One of ordinary skill in the art would have been motivated to employ the teachings of Woo for the flexibility of a system that enables multiple techniques such as a linear feedback shift register to be utilized in data processing within a network environment. (see Woo paragraph [0121])
8. Claims 8, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Haukness in view of JI et al. and further in view of Weinert and JP3639786 and Yap et al. (US PGPUB No. 20150169472) and Koo et al. (US PGPUB No. 20220385332).
Regarding Claims 8, 16, Haukness-JI-Weinert-JP3639786 discloses the method for remapping the row address on the multichannel DIMM of claim 1 and the system for remapping the row address of claim 9, wherein the encrypting and mapping the first channel row address through a key-based mapping method to obtain a second channel row address that corresponds to the first channel row address within a predetermined address range.
Haukness does not specifically disclose for a) concatenating first channel row address with preset characters to obtain input data that meets data length required for AES encryption operation, and for b) performing AES encryption operation on input data using a key.
However, Yap discloses:
a) concatenating the first channel row address with preset characters to obtain input data that meets data length required for AES encryption operation; b) performing AES encryption operation on the input data using a key. (see Woo paragraph [0017]: generates a value based on a channel address concatenated with the logical or physical address for the data and padded with zeros to form a fixed bit length base tweak for encryption, such as 128 bits. Other techniques may be used to generate the base tweak from the address. The tweak encryption engine 312 then generates an encrypted base tweak having a bit length, e.g., 128 bits, using a tweak key 314 and an algorithm such as Advanced Encryption Standard (AES) 256 or other suitable encryption algorithms known in the art.)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Haukness for a) concatenating first channel row address with preset characters to obtain input data that meets data length required for AES encryption operation, and for b) performing AES encryption operation on input data using a key as taught by Yap. One of ordinary skill in the art would have been motivated to employ the teachings of Yap for the enhanced security of a system that enables multiple processing steps including manipulation of encryption results such as concatenation of addresses in address generation techniques. (see Yap paragraph [0017])
Haukness does not specifically disclose for c) truncating low address portion of output of AES encryption operation.
However, Koo discloses:
c) truncating low address portion of output of the AES encryption operation as the second channel row address. (see Koo paragraph [0202]: The UWB device may obtain an output having a length corresponding to the length (e.g., 2 bytes) of a short MAC address from the Hash result (by truncation) in step 1040. For example, the UWB device may truncate the lower 2 bytes or upper 2 bytes of the Hash result.; paragraph [0192]: UWB device may obtain an output having a length corresponding to the length (e.g., 2 bytes) of the short MAC address from the AES encryption result (by truncation) in step 9050. For example, the UWB device may truncate the lower 2 bytes or upper 2 bytes of the AES encryption result.; (reduce output by truncation))
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Haukness for c) truncating low address portion of output of AES encryption operation as taught by Koo. One of ordinary skill in the art would have been motivated to employ the teachings of Koo for the enhanced security of a system that enables multiple processing steps such as manipulation of encryption results such as truncation in address generation techniques. (see Koo paragraph [0202]; paragraph [0192])
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/CJ/
December 15, 2025
/SHEWAYE GELAGAY/Supervisory Patent Examiner, Art Unit 2436