Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to remarks filed on 1/16/2026.
Claims 1 & 4 are pending and presented for examination.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 10-2021-0046757, filed on 4/9/2021.
Response to Amendment
Claims 2, 3 & 5-7 have been cancelled.
Claims 1 & 4 have been amended.
Rejections to claims 1 & 4 under 35 USC 103 based on Wood et al. (US 7978012)(herein after “Wood”) in view of Hormis et al. (US 2023/0413309)(herein after “Hormis”) have been withdrawn based on amendments to these claims. However, after further consideration, new grounds of rejections to these claims under 35 USC 103 based on Wood in view of Hormis and further in view of Li et al. (CN 103580686)(herein after “Li”) have been introduced based on amendments to these claims.
Response to Arguments
Applicant’s arguments, see “Remarks”, filed 1/16/2026, with respect to the objection to drawings have been fully considered and are persuasive. A replacement sheet for Fig 2 showing the control unit 140 has been submitted. The objection to drawings has been withdrawn.
Applicant’s arguments, see “Remarks”, filed 1/16/2026, with respect to the rejection of claim 2 under 35 USC 112(b) have been fully considered and are persuasive. The amended claim language of claim 2, that has been incorporated into claim 1, provides clarification that the condition for detection is when the difference between the initial carrier frequency and a target carrier frequency is less than a predetermined value. The rejection of the claim language for claim 2, now incorporated into claim1, under 35 USC 112(b) has been withdrawn.
Applicant's arguments filed 1/16/2026 regarding 112(b) rejections of claims 1 & 4 have been fully considered but they are not persuasive.
Regarding claims 1 & 4, applicant submits that the structure of the first PLL unit and the second PLL unit is disclosed in the current application specification through Fig 2. Examiner respectfully disagrees noting that a claimed invention may be rejected under 35 USC 112(b) when the claims fail to (A) set forth the subject matter that the inventor or a joint inventor regards as the invention; and (B) particularly point out and distinctly define the metes and bounds of the subject matter to be protected by the patent grant. See MPEP §2171. Further, a claim limitation expressed in means- (or step-) plus-function language "shall be construed to cover the corresponding structure…described in the specification and equivalents thereof." "If one employs means plus function language in a claim, one must set forth in the specification an adequate disclosure showing what is meant by that language. If an applicant fails to set forth an adequate disclosure, the applicant has in effect failed to particularly point out and distinctly claim the invention as required by the 35 U.S.C. 112(b) [or the second paragraph of pre-AIA section 112 ]." In re Donaldson Co., 16 F.3d 1189, 1195, 29 USPQ2d 1845, 1850 (Fed. Cir. 1994) (en banc) (see MPEP §2181, Section II).
Applicant argues that fig 2 of the current application specification illustrates that the first PLL unit includes hardware components of an oscillator 111, frequency dividers (Div2, DivN), a phase frequency detector (PFD), and a center of gravity digital loop filter (CG DLF), and the second PLL unit 110 includes hardware components of a baseband phase detector (BBPD), and a clock and data recovery digital loop filter (CDR DLF). The current application specification fails to include any mention of, or description of the structure of, frequency dividers (Div2, DivN), a phase frequency detector (PFD), a center of gravity digital loop filter (CG DLF), a baseband phase detector (BBPD), and a clock and data recovery digital loop filter (CDR DLF). The current application specification fails to disclose that these elements are hardware components. While the current application specification mentions an oscillator 111, it fails to describe structure for the oscillator (i.e. no discussion that this is a hardware component) but only provides the function of the oscillator 111 (i.e. generates a clock).
Based on the above discussion, examiner maintains rejection of claims 1 & 4 under 35 USC 112(b).
Applicant’s arguments, see “Remarks”, filed 1/16/2026, with respect to the rejection of claim 7 under 35 USC 102 have been fully considered and are persuasive. Applicant submits that claim 7 has been cancelled and thus rejection of claim 7 under 35 USC 102 is moot. Examiner agrees.
Applicant's arguments filed 1/16/2026 with respect rejections of claims 1 & 4, and limitations of claims 3, 4 & 6 that have been incorporated into claims 1 & 4, under 35 USC 103 have been fully considered but they are not persuasive.
Regarding claim 1, applicant submits that this claim is patentable because Wood, Hormis and Li individually or in combination fail to disclose or teach all the limitations of amended claim 1. Examiner respectfully disagrees noting that, per 35 U.S.C. 103, a patent for a claimed invention may not be obtained if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains (see §MPEP 2141).
Applicant argues that Wood fails to teach of suggest "a second PLL unit configured to generate a second clock based on the first clock generated by the first PLL unit and a baseband signal generated by demodulating a reception signal, wherein the second clock is provided to the first PLL unit as the reference clock," as recited in amended independent claim 1. Applicant argues that the output of secondary PLL 14 is not a reference clock provided to first PLL 12. Examiner respectfully disagrees noting that second frequency VCO2 fVCO2 is provided to first PLL 12 to adjust the frequency of first frequency of VCO1 fVCO1. Thus, fVCO2 can be interpreted as comprising a reference clock for adjusting the frequency of fVCO1.
Applicant argues that Wood fails to teach or suggest “wherein, when the first PLL unit is in an initial state, the first clock that determines an initial carrier frequency is generated as an arbitrary initial clock is provided to the first PLL unit as the reference clock, and when a frequency locking in which a difference between the initial carrier frequency and a target carrier frequency is less than a predetermined value is detected, a phase of the first clock generated by the first PLL unit and a phase of the second clock generated by the second PLL unit are synchronized with each other as the second clock is provided to the first PLL unit as the reference clock," as recited in amended independent claim 1. Applicant argues that claim 1 recites a sequence where a first PLL unit is in an initial state and a first clock determines an initial carrier frequency generated by providing an arbitrary clock to the first PLL as a reference clock, then detecting frequency locking in which a difference between the initial carrier frequency and a target carrier frequency is less than a predetermined value, and in response to such detection, the second clock generated by the second PLL is switched to be the reference clock of the first PLL, thereby synchronizing the phases of the first clock and the second clock. Applicant argues that claim 1: i) includes a technical feature in which the source of the reference clock input to the PFD of the first PLL is replaced before and after satisfaction of the frequency-locking condition, ii) recites switching-upon detection of frequency locking-the reference clock provided to the PFD of the first PLL to the second clock generated by the second PLL and iii) claims an event-based reference-replacement operational sequence in which, upon detection of frequency locking, the second clock generated by the second PLL is switched to be the reference clock provided to the first PLL so as to achieve phase synchronization. Examiner respectfully disagrees noting that the claim language of amended claim 1 only requires that “when a frequency locking in which a difference between the initial carrier frequency and a target carrier frequency is less than a predetermined value is detected, a phase of the first clock generated by the first PLL unit and a phase of the second clock generated by the second PLL unit are synchronized with each other as the second clock is provided to the first PLL unit as the reference clock”. The claim language of amended claim 1 does not require a sequence where a first PLL unit is in an initial state and a first clock determines an initial carrier frequency generated by providing an arbitrary clock to the first PLL as a reference clock, then detecting frequency locking in which a difference between the initial carrier frequency and a target carrier frequency is less than a predetermined value, and in response to such detection, the second clock generated by the second PLL is switched to be the reference clock of the first PLL, thereby synchronizing the phases of the first clock and the second clock. The highlighted terms are nowhere to be found in the claim language of amended claim 1. Thus, claim 1 as currently amended does not include a technical feature in which the source of the reference clock input to the PFD of the first PLL is replaced before and after satisfaction of the frequency-locking condition, nor does claim 1 require switching-upon detection of frequency locking-the reference clock provided to the PFD of the first PLL to the second clock generated by the second PLL or an event-based reference-replacement operational sequence. Wood teaches of first PLL 12 being in an initial state where first frequency of VCO1 fVCO1 determines an initial carrier frequency of fXTAL when an arbitrary initial fOFFSET=0 is provided to first PLL 12 as a reference frequency. Wood further teaches that when there is a difference between the initial carrier frequency (e.g. fVCO1 = fXTAL when fOFFSET=0), then first PLL 12 and second PLL 14 will synchronize and frequency lock so that fOUT=fVCO1=fIN.
Applicant argues that Li fails to teach “when a frequency locking in which the initial carrier frequency approaches a target carrier frequency by a predetermined level or more is detected” because Li differs in what is being switched and the resulting effect. Examiner respectfully disagrees noting that Li is only used to teach of frequency locking by detecting an initial carrier frequency approaching a target frequency by a predetermined level. Li in [0084] teaches of locking an oscillator when the oscillator is tuned (i.e. an initial carrier frequency approaches) to within a predetermined range a target frequency. Thus, it is moot that Li differs in what is being switched, and examiner argues Li does teach of the main resulting effect of detecting frequency locking when an initial carrier frequency is withing a target frequency by a predetermine level.
Applicant argues that Wood in view of Hormis does not teach a second PLL unit configured to generate a second clock based on the first clock generated by the first PLL unit and a baseband signal generated by demodulating a reception signal, ... wherein a phase synchronization is implemented as a phase of the first clock and a phase of the baseband signal are synchronized with each other," as recited in amended independent claim 1. Examiner respectfully disagrees. Applicant argues that Wood does not consider a baseband signal of any configuration for synchronizing a phase of an RF carrier to a baseband phase. Examiner notes that Hormis is used to teach of synchronizing a phase of an RF carrier to a baseband signal (see Fig 8 & [0175]-[0179] of Hormis that discloses phase synchronization through a PLL 876-a that synchronizes a phase of a first VCO 875a with a phase of baseband signal that is output from Digital Processing and Control circuitry 830).
Applicant argues that Hormis fails to teach of a second clock generated by a second PLL based on a baseband signal and provided to a first PLL as its reference clock because Hormis describes a VCO 875 generating a LO frequency and that carrier-tracking PLL 876 tunes VCO 875 based on a secondary link providing a clock reference for the carrier-tracking PLL. Examiner respectfully disagrees noting that Wood teaches of a second PLL providing a first PLL a reference clock (i.e. a second clock), and thus Hormis is only used to teach of a PLL providing a reference clock based on a baseband signal and wherein a carrier frequency used for demodulating the reception signal is determined by a first clock. Fig 8 & [0175]-[0179] of Hormis discloses a PLL 876-a providing a reference VCO 875-a based on a digital signal (i.e. baseband signal) generated by A/D converter 825 and control circuitry 830 that performs demodulation of beamformed signals received through antennas 805-a through 805-n and that VCO 875a (i.e. a first clock) determines a carrier frequency used for demodulating the signals received by antennas 805-a through 805-n.
Applicant argues that Hormis fails to teach or suggest a configuration in which a generated clock is provided to a reference input of a first PLL so that the reference clock is switched. Examiner notes that the claim language of amended claim 1 does not recite “switching” of a reference clock, and thus argument is moot.
Based on the above discussion, and the incorporation of limitations from claims 2, 3, 5 & 6 into claim 1, examiner withdraws rejection of claim 1 under 35 USC 103 based on Wood in view of Hormis, but introduces new grounds of rejection of claim 1 under 35 USC 103 based on Wood in view of Hormis and further in view of Li.
Regarding claim 4, applicant submits that this claim is patentable based on similar amendments and arguments made for claim 1. Examiner respectfully disagrees and for the same reasons as discussed above withdraws rejection of claim 4 under 35 USC 103 based on Wood in view of Hormis, but introduces new grounds of rejection of claim 4 under 35 USC 103 based on Wood in view of Hormis and further in view of Li.
Regarding claims 2, 3, 5 & 6, applicant submits that rejections to these claims are moot as these claims have been cancelled. Examiner agrees.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitations use a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are:
In claims 1 & 4, “a first PLL unit configured to generate a first clock based on a reference clock” has been interpreted under 112(f) as a means plus function because of the combination of non-structural element “first PLL unit” and functionality “configured to generate a first clock based on a reference clock” without reciting sufficient structure to achieve the function. The specification also fails to disclose the structure for implementing the function of the “first PLL unit”. Note that claim 4 also recites “a step” which clearly invokes 112(f).
“A second PLL unit configured to generate a second clock based on the first clock generated by the first PLL unit” has been interpreted under 112(f) as a means plus function because of the combination of non-structural element “second PLL unit” and functionality “configured to generate a second clock based on the first clock generated by the first PLL unit” without reciting sufficient structure to achieve the function. The specification also fails to disclose the structure for implementing the function of the “second PLL unit”.
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitations to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim limitations “first PLL unit” and “second PLL unit” in claims 1 & 4 invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed functions and to clearly link the structure, material, or acts to the functions. The specification fails to disclose the structures for implementing the functions of the “first PLL unit” or the “second PLL unit” stated in these claims. Therefore, these claims are indefinite and are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 & 4 are rejected under 35 U.S.C. 103 as being unpatentable over Wood et al. (US 7978012)(herein after “Wood”) in view of Hormis et al. (US 2023/0413309)(herein after “Hormis”), and further in view of Li et al. (CN 103580686)(herein after “Li”).
Regarding claim 1, Wood discloses a system, the system comprising:
a first phase locked loop (PLL) unit configured to generate a first clock based on a reference clock (Fig 1A, col 3, lines 60-67 & col 4, lines 1-11 disclose a first PLL 12 configured to generate a first frequency of VCO1 fVCO1 (i.e. a first clock) based on a frequency of VCO2 fVCO2 (i.e. a reference clock).); and
a second PLL unit configured to generate a second clock based on the first clock generated by the first PLL unit (Fig 1A, col 3, lines 60-67 & col 4, lines 1-11 disclose a second PLL 14 configured to generate a second frequency of VCO2 fVCO2 (i.e. a second clock) based on the first frequency of VCO1 fVCO1.),
wherein the second clock is provided to the first PLL unit as the reference clock (Fig 1A, col 3, lines 60-67 & col 4, lines 1-11 disclose second frequency of VCO2 fVCO2 is provided to first PLL 12 as the reference clock), and
(Fig 1A, col 3, lines 60-67 and col 4, lines 1-11 & lines 26-28 disclose first frequency (i.e. a carrier frequency) VCO1 fVCO1 is used in PFD2 to compare the frequency of VCO1 to fIN (i.e. demodulate reception signal fIN).),
wherein, when the first PLL unit is in an initial state, the first clock that determines an initial carrier frequency is generated as an arbitrary initial clock is provided to the first PLL unit as the reference clock (Fig 1A & col 4, lines 12-35 disclose an initial state for first PLL 12 where a first frequency of VCO1 fVCO1 determines an initial carrier frequency fXTAL is generated as an arbitrary initial clock of FOFFSET=0 is provided to first PLL 12 as the reference clock.), and
a phase of the first clock generated by the first PLL unit and a phase of the second clock generated by the second PLL unit are synchronized with each other as the second clock is provided to the first PLL unit as the reference clock (Fig 1A & col 4, lines 12-35 discloses comparing first frequency of VCO1 fVCO1 to the reception signal frequency fIN and if there is any difference in the phase, the difference is output at PFD2. The phase difference output from PFD2 adjusts second frequency of VCO2 fVCO2 that is provided to first PLL 12 to feed TF22 that adjusts the first frequency of VCO1 fVCO1 such that fOUT tracks changes in fIN and changes in fXTAL. Thus, first frequency of VCO1 fVCO1 and second frequency of VCO2 fVCO2 are synchronized to track changes in fIN and changes in fXTAL.), and
Wood fails to disclose wherein the system is for implementing a broadband radio frequency (RF) communication, and wherein the second PLL unit is configured based on a baseband signal generated by demodulating a reception signal, wherein a carrier frequency used for demodulating the reception signal is determined by the first clock, and wherein a phase synchronization is implemented as a phase of the first clock and a phase of the baseband signal are synchronized with each other.
However, Hormis teaches wherein the system is for implementing a broadband radio frequency (RF) communication (Fig 1 & [0060]-[0061] discloses a wireless communication system supporting broadband communications.), and
wherein the second PLL unit is configured based on a baseband signal generated by demodulating a reception signal, and (Fig 8 & [0175]-[0179] discloses a second PLL 876-a configured to provide a reference VCO 875-a signal based on a digital signal (i.e. baseband signal) generated by A/D converter 825 and control circuitry 830 that performs demodulation of beamformed signals received through antennas 805-a through 805-n.), and
wherein a carrier frequency used for demodulating the reception signal is determined by the first clock (Fig 8 & [0175]-[0179] disclose that VCO 875a (i.e. a first clock) determines a carrier frequency used for demodulating the signals received by antennas 805-a through 805-n.), and
wherein a phase synchronization is implemented as a phase of the first clock and a phase of the baseband signal are synchronized with each other (Fig 8 & [0175]-[0179] discloses phase synchronization through a PLL 876-a that synchronizes a phase of a first VCO 875a with a phase of baseband signal that is output from Digital Processing and Control circuitry 830.).
Therefore, it would have been obvious to someone having ordinary skill in the art prior to the effective filing date of the claimed invention to have a system with a first phase locked loop (PLL) unit configured to generate a first clock based on a reference clock; and a second PLL unit configured to generate a second clock based on the first clock generated by the first PLL unit, wherein the second clock is provided to the first PLL unit as the reference clock, as disclosed by Wood, wherein the system is for implementing a broadband radio frequency (RF) communication, and wherein the second PLL unit is configured based on a baseband signal generated by demodulating a reception signal, wherein a carrier frequency used for demodulating the reception signal is determined by the first clock, and wherein a phase synchronization is implemented as a phase of the first clock and a phase of the baseband signal are synchronized with each other as taught by Hormis. The motivation to do so would be to have a system where a first PLL generates a first RF frequency carrier, based on a reference frequency signal from a second PLL that is based on the first RF frequency carrier generated by the first PLL and a baseband signal generated by demodulating a reception signal, that is used for demodulating the reception signal, to provide a baseband signal that is phase synchronized to the first RF frequency carrier and can be used for use for adjusting the second PLL reference frequency signal in order to frequency lock both phase lock loops for tracking of the reception signal.
Wood fails to disclose determining when a frequency locking in which the initial carrier frequency approaches a target carrier frequency by a predetermined level or more is detected.
However, Li further teaches determining when a frequency locking in which the initial carrier frequency approaches a target carrier frequency by a predetermined level or more is detected (Fig 3 & [0083]-[0084] discloses a switch 904 that determines when an initial carrier frequency based on a reference frequency Freq-ref is within a predetermined range of a target frequency.).
Therefore, it would have been obvious to someone having ordinary skill in the art prior to the effective filing date of the claimed invention to have a system for implementing a broadband radio frequency (RF) communication, wherein when a first PLL unit is in an initial state, a first clock that determines an initial carrier frequency is generated as an arbitrary initial clock is provided to the first PLL unit as the reference clock, and a phase of the first clock generated by the first PLL unit and a phase of the second clock generated by the second PLL unit are synchronized with each other as the second clock is provided to the first PLL unit as the reference clock, as disclosed by Wood in view of Hormis, and determining when a frequency locking in which the initial carrier frequency approaches a target carrier frequency by a predetermined level or more is detected, as further taught by Li. The motivation to do so would be to have a system for implementing a broadband radio frequency (RF) communication where a switch can determine when an initial carrier frequency output from a first PLL of a coupled pair of PLLs, based on an arbitrary reference carrier frequency, is tuned to within a predetermined range of a target carrier frequency, so that the switch can change from using the arbitrary reference carrier frequency to drive the first PLL to using a carrier frequency output from a second PLL of the couple PLLs to drive the first PLL, to avoid a situation where the initial carrier frequency output from the second PLL is outside the capture range of the first PLL.
Regarding claim 4, Wood discloses a method comprising:
a step in which a first phase locked loop (PLL) unit generates a first clock based on a reference clock (Fig 1A, col 3, lines 60-67 & col 4, lines 1-11 disclose a first PLL 12 configured to generate a first frequency VCO fVCO1 (i.e. a first clock) based on a frequency of VCO2 fVCO2 (i.e. a reference clock).); and
a step in which a second PLL unit generates a second clock based on the first clock generated by the first PLL unit (Fig 1A, col 3, lines 60-67 & col 4, lines 1-11 disclose a second PLL 14 configured to generate a second frequency of VCO2 fVCO2 (i.e. a second clock) based on the first frequency of VCO1 fVCO1.),
wherein the second clock is provided to the first PLL unit as the reference clock (Fig 1A, col 3, lines 60-67 & col 4, lines 1-11 disclose second frequency of VCO2 fVCO2 is provided to first PLL 12 as the reference clock), and
wherein, when the first PLL unit is in an initial state, the first clock that determines an initial carrier frequency is generated as an arbitrary initial clock is provided to the first PLL unit as the reference clock (Fig 1A & col 4, lines 12-35 disclose an initial state for first PLL 12 where a first frequency of VCO1 fVCO1 determines an initial carrier frequency fXTAL is generated as an arbitrary initial clock of FOFFSET=0 is provided to first PLL 12 as the reference clock.), and
a phase of the first clock generated by the first PLL unit and a phase of the second clock generated by the second PLL unit are synchronized with each other as the second clock is provided to the first PLL unit as the reference clock (Fig 1A & col 4, lines 12-35 discloses comparing first frequency of VCO1 fVCO1 to the reception signal frequency fIN and if there is any difference in the phase, the difference is output at PFD2. The phase difference output from PFD2 adjusts second frequency of VCO2 fVCO2 that is provided to first PLL 12 to feed TF22 that adjusts the first frequency of VCO1 fVCO1 such that fOUT tracks changes in fIN and changes in fXTAL. Thus, first frequency of VCO1 fVCO1 and second frequency of VCO2 fVCO2 are synchronized to track changes in fIN and changes in fXTAL.), and
Wood fails to disclose wherein the system is for implementing a broadband radio frequency (RF) communication, and wherein the second PLL unit is configured based on a baseband signal generated by demodulating a reception signal, wherein a carrier frequency used for demodulating the reception signal is determined by the first clock, and wherein a phase synchronization is implemented as a phase of the first clock and a phase of the baseband signal are synchronized with each other.
However, Hormis teaches wherein the system is for implementing a broadband radio frequency (RF) communication (Fig 1 & [0060]-[0061] discloses a wireless communication system supporting broadband communications.), and
wherein the second PLL unit is configured based on a baseband signal generated by demodulating a reception signal, and (Fig 8 & [0175]-[0179] discloses a second PLL 876-a configured to provide a reference VCO 875-a signal based on a digital signal (i.e. baseband signal) generated by A/D converter 825 and control circuitry 830 that performs demodulation of beamformed signals received through antennas 805-a through 805-n.), and
wherein a carrier frequency used for demodulating the reception signal is determined by the a clock (Fig 8 & [0175]-[0179] disclose that VCO 875a (i.e. a first clock) determines a carrier frequency used for demodulating the signals received by antennas 805-a through 805-n.), and
wherein a phase synchronization is implemented as a phase of the first clock and a phase of the baseband signal are synchronized with each other (Fig 8 & [0175]-[0179] discloses phase synchronization through a PLL 876-a that synchronizes a phase of a first VCO 875a with a phase of baseband signal that is output from Digital Processing and Control circuitry 830.).
Therefore, it would have been obvious to someone having ordinary skill in the art prior to the effective filing date of the claimed invention to have a method with a step in which a first phase locked loop (PLL) unit generates a first clock based on a reference clock; and a step in which a second PLL unit generates a second clock based on the first clock generated by the first PLL unit, wherein the second clock is provided to the first PLL unit as the reference clock, as disclosed by Wood, wherein the system is for implementing a broadband radio frequency (RF) communication, and wherein the second PLL unit is configured based on a baseband signal generated by demodulating a reception signal, wherein a carrier frequency used for demodulating the reception signal is determined by the first clock, and wherein a phase synchronization is implemented as a phase of the first clock and a phase of the baseband signal are synchronized with each other as taught by Hormis. The motivation to do so would be to have a method where a first PLL generates a first RF frequency carrier, based on a reference frequency signal from a second PLL that is based on the first RF frequency carrier generated by the first PLL and a baseband signal generated by demodulating a reception signal, that is used for demodulating the reception signal, to provide a baseband signal that is phase synchronized to the first RF frequency carrier and can be used for use for adjusting the second PLL reference frequency signal in order to frequency lock both phase lock loops for tracking of the reception signal.
Wood fails to disclose determining when a frequency locking in which the initial carrier frequency approaches a target carrier frequency by a predetermined level or more is detected.
However, Li further teaches determining when a frequency locking in which the initial carrier frequency approaches a target carrier frequency by a predetermined level or more is detected (Fig 3 & [0083]-[0084] discloses a switch 904 that determines when an initial carrier frequency based on a reference frequency Freq-ref is within a predetermined range of a target frequency.).
Therefore, it would have been obvious to someone having ordinary skill in the art prior to the effective filing date of the claimed invention to have a method for implementing a broadband radio frequency (RF) communication, wherein when a first PLL unit is in an initial state, a first clock that determines an initial carrier frequency is generated as an arbitrary initial clock is provided to the first PLL unit as the reference clock, and a phase of the first clock generated by the first PLL unit and a phase of the second clock generated by the second PLL unit are synchronized with each other as the second clock is provided to the first PLL unit as the reference clock, as disclosed by Wood in view of Hormis, and determining when a frequency locking in which the initial carrier frequency approaches a target carrier frequency by a predetermined level or more is detected, as further taught by Li. The motivation to do so would be to have a method for implementing a broadband radio frequency (RF) communication where a switch can determine when an initial carrier frequency output from a first PLL of a coupled pair of PLLs, based on an arbitrary reference carrier frequency, is tuned to within a predetermined range of a target carrier frequency, so that the switch can change from using the arbitrary reference carrier frequency to drive the first PLL to using a carrier frequency output from a second PLL of the couple PLLs to drive the first PLL, to avoid a situation where the initial carrier frequency output from the second PLL is outside the capture range of the first PLL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JAMES P SEYMOUR/Examiner, Art Unit 2419
/Nishant Divecha/Supervisory Patent Examiner, Art Unit 2419