Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/17/2026 has been entered.
Claims 1 & 4 are pending and presented for examination.
Response to Amendment
Claims 1 & 4 have been amended.
Rejection to claims 1 & 4 under 35 USC 112(b) have been withdrawn based on amendments to these claims.
Rejections to claims 1 & 4 under 35 USC 103 made in the Final rejection dated 3/19/2026 have been withdrawn based on amendments to these claims, but new grounds of rejections to these claims under 35 USC 103 have been made in view of new references Drexler et al. (US 2007/0103214)(herein after “Drexler”) and McCollum et al. (US 6028460)(herein after “McCollum”).
Response to Arguments
Applicant’s arguments, see “Remarks”, filed 6/17/2026, with respect to rejections of claims 1 & 4 under 35 USC 112(b) have been fully considered and are persuasive. Elimination of the term “unit” in these claims eliminates the invoking of 35 USC 112(f) in these claims, and clarifies that phase locked loops are being claimed, which have structure known to someone having ordinary skill in the art. The rejections of claims 1 & 4 under 35 USC 112(b) have been withdrawn.
Applicant’s arguments, see “Remarks”, filed 6/17/2026, with respect to the rejections of claims 1 & 4 under 35 USC 103 have been fully considered and are persuasive. Therefore, these rejections have been withdrawn. However, upon further consideration, new grounds of rejections to these claims are made in view of new references Drexler et al. (US 2007/0103214)(herein after “Drexler”) and McCollum et al. (US 6028460)(herein after “McCollum”).
Regarding claim 1, applicant submits that amendments to this claim traverse the rejection of this claim under 35 USC 103 made in the Final Rejection dated 3/19/2026. Examiner agrees and withdraws rejection of claim 1 under 35 USC 103 made in the Final Rejection dated 3/19/2026. However, after further consideration, examiner introduces a new ground of rejection of claim 1 under 35 USC 103 based on new references Drexler and McCollum. Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding claim 4, applicant submits that this claim traverses the rejection of this claim under 35 USC 103 made in the Final Rejection dated 3/19/2026 due to similar amendments and arguments as made for claim 1. Examiner agrees and withdraws rejection of claim 4 under 35 USC 103 made in the Final Rejection dated 3/19/2026. However, for the same reasons as discussed above, examiner introduces a new ground of rejection of claim 4 under 35 USC 103 based on new references Drexler and McCollum.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 & 4 are rejected under 35 U.S.C. 103 as being unpatentable over Wood et al. (US 7978012)(herein after “Wood”) in view of Hormis et al. (US 2023/0413309)(herein after “Hormis”), and further in view of Drexler et al. (US 2007/0103214)(herein after “Drexler”) and McCollum et al. (US 6028460)(herein after “McCollum”).
Regarding claim 1, Wood discloses a system, the system comprising:
a first phase locked loop (PLL) configured to generate a first clock based on a reference clock (Fig 1A, col 3, lines 60-67 & col 4, lines 1-11 disclose a first PLL 12 configured to generate a first frequency of VCO1 fVCO1 (i.e. a first clock) based on a frequency of VCO2 fVCO2 (i.e. a reference clock).); and
a second PLL configured to generate a second clock based on the first clock generated by the first PLL (Fig 1A, col 3, lines 60-67 & col 4, lines 1-11 disclose a second PLL 14 configured to generate a second frequency of VCO2 fVCO2 (i.e. a second clock) based on the first frequency of VCO1 fVCO1.),
wherein a carrier frequency used for demodulating the reception signal is determined by the first clock (Fig 1A, col 3, lines 60-67 and col 4, lines 1-11 & lines 26-28 disclose first frequency (i.e. a carrier frequency) VCO1 fVCO1 is used in PFD2 to compare the frequency of VCO1 to fIN (i.e. demodulate reception signal fIN).),
Wood fails to disclose but Hormis teaches wherein the system is for implementing a broadband radio frequency (RF) communication (Fig 1 & [0060]-[0061] discloses a wireless communication system supporting broadband communications.), and
wherein the second PLL unit is configured based on a baseband signal generated by demodulating a reception signal (Fig 8 & [0175]-[0179] discloses a second PLL 876-a configured to provide a reference VCO 875-a signal based on a digital signal (i.e. baseband signal) generated by A/D converter 825 and control circuitry 830 that performs demodulation of beamformed signals received through antennas 805-a through 805-n.),
wherein phase synchronization is implemented by synchronization of a phase of the first clock with a phase of the baseband signal (Fig 8 & [0175]-[0179] discloses phase synchronization through a PLL 876-a that synchronizes a phase of a first VCO 875a with a phase of baseband signal that is output from Digital Processing and Control circuitry 830.).
Therefore, it would have been obvious to someone having ordinary skill in the art prior to the effective filing date of the claimed invention to have a system with a first phase locked loop (PLL) configured to generate a first clock based on a reference clock; and a second PLL configured to generate a second clock based on the first clock generated by the first PLL, wherein a carrier frequency used for demodulating the reception signal is determined by the first clock, as disclosed by Wood, wherein the system is for implementing a broadband radio frequency (RF) communication, and wherein the second PLL is configured based on a baseband signal generated by demodulating a reception signal, and wherein phase synchronization is implemented by synchronization of a phase of the first clock with a phase of the baseband signal, as taught by Hormis. The motivation to do so would be to have a system where a first PLL generates a first RF frequency carrier, based on a reference frequency signal from a second PLL that is based on the first RF frequency carrier generated by the first PLL and a baseband signal generated by demodulating a reception signal, that is used for demodulating the reception signal, to provide a baseband signal that is phase synchronized to the first RF frequency carrier and can be used for use for adjusting the second PLL reference frequency signal in order to frequency lock both phase lock loops for tracking of the reception signal.
Wood fails to disclose but Drexler further teaches wherein, when the first PLL is in an initial state, the first clock that determines an initial carrier frequency is generated, in response to an arbitrary initial clock being provided to a reference clock input path of the first PLL as the reference clock (Fig 2 & [0014] disclose a PLL2 (i.e. a first PLL) in a first operating mode (i.e. an initial state) generating VCO2 (i.e. a first clock that determines an initial carrier frequency) in response to an input signal IN (i.e. an arbitrary initial clock) being provided to the input of PLL2 through switch S2 (i.e. a reference clock input path of the first PLL).), and
when a frequency locking is detected, the reference clock input path of the first PLL is switched so that the second clock is provided to the reference clock input path of the first PLL as the reference clock (Fig 3 & [0014]-[0015] discloses that when a locking detector (LD) detects that a PLL1 (i.e. a second PLL) is locked, the input of PLL2 is switched through switch S2 so that the VCO1 (i.e. a second clock) is provided to the input of PLL2 (i.e. as a reference clock).).
Therefore, it would have been obvious to someone having ordinary skill in the art prior to the effective filing date of the claimed invention to have a system with a first phase locked loop (PLL) configured to generate a first clock based on a reference clock; and a second PLL configured to generate a second clock based on the first clock generated by the first PLL, wherein a carrier frequency used for demodulating the reception signal is determined by the first clock, wherein the system is for implementing a broadband radio frequency (RF) communication, and wherein the second PLL is configured based on a baseband signal generated by demodulating a reception signal, and wherein phase synchronization is implemented by synchronization of a phase of the first clock with a phase of the baseband signal, as disclosed by Wood in view of Hormis, wherein, when the first PLL is in an initial state, the first clock that determines an initial carrier frequency is generated, in response to an arbitrary initial clock being provided to a reference clock input path of the first PLL as the reference clock, and when a frequency locking is detected, the reference clock input path of the first PLL is switched so that the second clock is provided to the reference clock input path of the first PLL as the reference clock, as further taught by Drexler. The motivation to do so would be to have a system where a first PLL generates an initial RF frequency carrier, based on an arbitrary reference frequency signal being input to the first PLL, that feeds a second PLL that generates a second RF frequency carrier based on the initial frequency carrier and a baseband signal generated by demodulating a reception signal using the initial frequency carrier, and when locking of the second PLL is detected, switch the input to the first PLL to an RF frequency carrier generated by the second PLL, in order to stabilize and reduce jitter in the initial frequency carrier output from the first PLL.
Wood fails to disclose but McCollum further teaches wherein frequency locking is in which a difference between the initial carrier frequency and a target carrier frequency is less than a predetermined value (Figs 3-5 & col 5, lines 20-65 disclose switching the input to an analog PLL when VCO 240 (i.e. an initial carrier frequency) is locked to a reference signal oscillator 100 (i.e. a target carrier frequency), wherein locking is determined by a mismatch (i.e. a difference) between VCO 240 and reference signal oscillator 100 is within a predefined tolerance +/- Df1.).
Therefore, it would have been obvious to someone having ordinary skill in the art prior to the effective filing date of the claimed invention to have a system with a first phase locked loop (PLL) configured to generate a first clock based on a reference clock; and a second PLL configured to generate a second clock based on the first clock generated by the first PLL, wherein a carrier frequency used for demodulating the reception signal is determined by the first clock, wherein the system is for implementing a broadband radio frequency (RF) communication, and wherein the second PLL is configured based on a baseband signal generated by demodulating a reception signal, and wherein phase synchronization is implemented by synchronization of a phase of the first clock with a phase of the baseband signal, wherein, when the first PLL is in an initial state, the first clock that determines an initial carrier frequency is generated, in response to an arbitrary initial clock being provided to a reference clock input path of the first PLL as the reference clock, and when a frequency locking is detected, the reference clock input path of the first PLL is switched so that the second clock is provided to the reference clock input path of the first PLL as the reference clock, as disclosed by Wood in view of Hormis and Drexler, wherein frequency locking is in which a difference between the initial carrier frequency and a target carrier frequency is less than a predetermined value, as further taught by McCollum. The motivation to do so would be to have a system where a first PLL generates an initial RF frequency carrier, based on an arbitrary reference frequency signal being input to the first PLL, that feeds a second PLL that generates a second RF frequency carrier based on the initial frequency carrier and a baseband signal generated by demodulating a reception signal using the initial frequency carrier, and when locking of the first PLL is detected based on the initial frequency carrier mismatch with a target carrier frequency being within a predefined tolerance, switch the input to the first PLL to an RF frequency carrier generated by the second PLL, in order to stabilize reduce jitter in the initial frequency carrier output from the first PLL when it is detected that the initial frequency carrier is close enough to the target carrier frequency to benefit from serially cascading the first PLL and second PLL.
Regarding claim 4, Wood discloses a method comprising:
a step in which a first phase locked loop (PLL) generates a first clock based on a reference clock (Fig 1A, col 3, lines 60-67 & col 4, lines 1-11 disclose a first PLL 12 configured to generate a first frequency VCO fVCO1 (i.e. a first clock) based on a frequency of VCO2 fVCO2 (i.e. a reference clock).); and
a step in which a second PLL generates a second clock based on the first clock generated by the first PLL (Fig 1A, col 3, lines 60-67 & col 4, lines 1-11 disclose a second PLL 14 configured to generate a second frequency of VCO2 fVCO2 (i.e. a second clock) based on the first frequency of VCO1 fVCO1.),
wherein a carrier frequency used for demodulating the reception signal is determined by the first clock (Fig 1A, col 3, lines 60-67 and col 4, lines 1-11 & lines 26-28 disclose first frequency (i.e. a carrier frequency) VCO1 fVCO1 is used in PFD2 to compare the frequency of VCO1 to fIN (i.e. demodulate reception signal fIN).),
Wood fails to disclose but Hormis teaches wherein the second PLL unit is configured based on a baseband signal generated by demodulating a reception signal (Fig 8 & [0175]-[0179] discloses a second PLL 876-a configured to provide a reference VCO 875-a signal based on a digital signal (i.e. baseband signal) generated by A/D converter 825 and control circuitry 830 that performs demodulation of beamformed signals received through antennas 805-a through 805-n.),
wherein phase synchronization is implemented by synchronization of a phase of the first clock with a phase of the baseband signal (Fig 8 & [0175]-[0179] discloses phase synchronization through a PLL 876-a that synchronizes a phase of a first VCO 875a with a phase of baseband signal that is output from Digital Processing and Control circuitry 830.).
Therefore, it would have been obvious to someone having ordinary skill in the art prior to the effective filing date of the claimed invention to have a method comprising a step in which a first phase locked loop (PLL) generates a first clock based on a reference clock; and step in which a second PLL generates a second clock based on the first clock generated by the first PLL, wherein a carrier frequency used for demodulating the reception signal is determined by the first clock, as disclosed by Wood, wherein the second PLL is configured based on a baseband signal generated by demodulating a reception signal, and wherein phase synchronization is implemented by synchronization of a phase of the first clock with a phase of the baseband signal, as taught by Hormis. The motivation to do so would be to have a method where a first PLL generates a first RF frequency carrier, based on a reference frequency signal from a second PLL that is based on the first RF frequency carrier generated by the first PLL and a baseband signal generated by demodulating a reception signal, that is used for demodulating the reception signal, to provide a baseband signal that is phase synchronized to the first RF frequency carrier and can be used for use for adjusting the second PLL reference frequency signal in order to frequency lock both phase lock loops for tracking of the reception signal.
Wood fails to disclose but Drexler further teaches wherein, when the first PLL is in an initial state, the first clock that determines an initial carrier frequency is generated, in response to an arbitrary initial clock being provided to a reference clock input path of the first PLL as the reference clock (Fig 2 & [0014] disclose a PLL2 (i.e. a first PLL) in a first operating mode (i.e. an initial state) generating VCO2 (i.e. a first clock that determines an initial carrier frequency) in response to an input signal IN (i.e. an arbitrary initial clock) being provided to the input of PLL2 through switch S2 (i.e. a reference clock input path of the first PLL).), and
when a frequency locking is detected, the reference clock input path of the first PLL is switched so that the second clock is provided to the reference clock input path of the first PLL as the reference clock (Fig 3 & [0014]-[0015] discloses that when a locking detector (LD) detects that a PLL1 (i.e. a second PLL) is locked, the input of PLL2 is switched through switch S2 so that the VCO1 (i.e. a second clock) is provided to the input of PLL2 (i.e. as a reference clock).).
Therefore, it would have been obvious to someone having ordinary skill in the art prior to the effective filing date of the claimed invention to have a method comprising a step in which a first phase locked loop (PLL) generates a first clock based on a reference clock; and step in which a second PLL generates a second clock based on the first clock generated by the first PLL, wherein a carrier frequency used for demodulating the reception signal is determined by the first clock, wherein the second PLL is configured based on a baseband signal generated by demodulating a reception signal, and wherein phase synchronization is implemented by synchronization of a phase of the first clock with a phase of the baseband signal, as disclosed by Wood in view of Hormis, wherein, when the first PLL is in an initial state, the first clock that determines an initial carrier frequency is generated, in response to an arbitrary initial clock being provided to a reference clock input path of the first PLL as the reference clock, and when a frequency locking is detected, the reference clock input path of the first PLL is switched so that the second clock is provided to the reference clock input path of the first PLL as the reference clock, as further taught by Drexler. The motivation to do so would be to have a method where a first PLL generates an initial RF frequency carrier, based on an arbitrary reference frequency signal being input to the first PLL, that feeds a second PLL that generates a second RF frequency carrier based on the initial frequency carrier and a baseband signal generated by demodulating a reception signal using the initial frequency carrier, and when locking of the second PLL is detected, switch the input to the first PLL to an RF frequency carrier generated by the second PLL, in order to stabilize and reduce jitter in the initial frequency carrier output from the first PLL.
Wood fails to disclose but McCollum further teaches wherein frequency locking is in which a difference between the initial carrier frequency and a target carrier frequency is less than a predetermined value (Figs 3-5 & col 5, lines 20-65 disclose switching the input to an analog PLL when VCO 240 (i.e. an initial carrier frequency) is locked to a reference signal oscillator 100 (i.e. a target carrier frequency), wherein locking is determined by a mismatch (i.e. a difference) between VCO 240 and reference signal oscillator 100 is within a predefined tolerance +/- Df1.).
Therefore, it would have been obvious to someone having ordinary skill in the art prior to the effective filing date of the claimed invention to have a method comprising a step in which a first phase locked loop (PLL) generates a first clock based on a reference clock; and step in which a second PLL generates a second clock based on the first clock generated by the first PLL, wherein a carrier frequency used for demodulating the reception signal is determined by the first clock, wherein the second PLL is configured based on a baseband signal generated by demodulating a reception signal, and wherein phase synchronization is implemented by synchronization of a phase of the first clock with a phase of the baseband signal, wherein, when the first PLL is in an initial state, the first clock that determines an initial carrier frequency is generated, in response to an arbitrary initial clock being provided to a reference clock input path of the first PLL as the reference clock, and when a frequency locking is detected, the reference clock input path of the first PLL is switched so that the second clock is provided to the reference clock input path of the first PLL as the reference clock, as disclosed by Wood in view of Hormis and Drexler, wherein frequency locking is in which a difference between the initial carrier frequency and a target carrier frequency is less than a predetermined value, as further taught by McCollum. The motivation to do so would be to have a method where a first PLL generates an initial RF frequency carrier, based on an arbitrary reference frequency signal being input to the first PLL, that feeds a second PLL that generates a second RF frequency carrier based on the initial frequency carrier and a baseband signal generated by demodulating a reception signal using the initial frequency carrier, and when locking of the first PLL is detected based on the initial frequency carrier mismatch with a target carrier frequency being within a predefined tolerance, switch the input to the first PLL to an RF frequency carrier generated by the second PLL, in order to stabilize reduce jitter in the initial frequency carrier output from the first PLL when it is detected that the initial frequency carrier is close enough to the target carrier frequency to benefit from serially cascading the first PLL and second PLL.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Herbeck et al. (US 9413361) discloses a Closed Loop Clock Generator with Multiple Reference Clocks.
Kanno et al. (US 6369625) discloses a Phase Locked Loop Circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES P SEYMOUR whose telephone number is (571)272-7654. The examiner can normally be reached M-F 8-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nishant Divecha can be reached at 571-270-3125. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES P SEYMOUR/Examiner, Art Unit 2419
/Nishant Divecha/Supervisory Patent Examiner, Art Unit 2419
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