DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending. Claims 15 have been amended as per Applicants' request.
Papers Submitted
It is hereby acknowledged that the following papers have been received and placed of record in the file:
Amended Claims as filed on September 01, 2026
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on September 01, 2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8-13, and 15-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shen et al. (US 2021/0390071) (hereinafter Shen) (published December 16, 2021).
Regarding Claims 1 and 8, taking claim 8 as exemplary, Shen discloses a data processing system, comprising: a data processor; a memory; a memory controller coupled to the data processor and the memory, comprising:
“FIG. 1 illustrates in block diagram form an accelerated processing unit (APU) 100 and memory system 130 known in the prior art. APU 100 is an integrated circuit suitable for use as a processor in a host data processing system, and includes generally a central processing unit (CPU) core complex 110, a graphics core 120, a set of display engines 122, a memory management hub 140, a data fabric 125, a set of peripheral controllers 160, a set of peripheral bus controllers 170, and a system management unit (SMU) 180” (Shen [0015])
“Memory management hub 140 and its associated physical interfaces (PHYs) 151 and 152 are integrated with APU 100 in this embodiment. Memory management hub 140 includes memory channels 141 and 142 and a power engine 149. Memory channel 141 includes a host interface 145, a memory channel controller 143, and a physical interface 147” (Shen [0023] see fig. 1 the memories in memory system 130 is connected to the memory controllers)
a command queue for receiving memory access requests; and
“FIG. 2 illustrates in block diagram form a memory controller 200 that is suitable for use in an APU like that of FIG. 1. Memory controller 200 includes generally a memory channel controller 210 and a power controller 250. Memory channel controller 210 includes generally an interface 212, a memory interface queue 214, a command queue 220, an address generator 222, a content addressable memory (CAM) 224, replay control logic 231 including a replay queue 230, a refresh control logic block 232, a timing block 234, a page table 236, an arbiter 238, an error correction code (ECC) check circuit 242, an ECC generation block 244, a data buffer 246, and refresh logic 247” (Shen [0028])
an arbiter operable to:
“FIG. 2 illustrates in block diagram form a memory controller 200 that is suitable for use in an APU like that of FIG. 1. Memory controller 200 includes generally a memory channel controller 210 and a power controller 250. Memory channel controller 210 includes generally an interface 212, a memory interface queue 214, a command queue 220, an address generator 222, a content addressable memory (CAM) 224, replay control logic 231 including a replay queue 230, a refresh control logic block 232, a timing block 234, a page table 236, an arbiter 238, an error correction code (ECC) check circuit 242, an ECC generation block 244, a data buffer 246, and refresh logic 247” (Shen [0028])
allow cross-mode activations during a streak of accesses of a current mode in response to a number of cross-mode accesses present in the command queue exceeding an adaptive threshold.
“The arbiter has a current mode indicating the type of commands currently being transacted, and a cross mode indicating the other type. The arbiter is operable to monitor commands in the command queue for the current mode and the cross mode, and in response to designated conditions including a designated minimum threshold of cross mode commands being available at the arbiter, send an available cross mode ACT command for a cross-mode command to the memory interface queue while continuing to operate in the current mode” (Shen [0014] cross mode activate is during the streak of a current mode)
“While in this embodiment a low efficiency threshold is adjusted to a high efficiency threshold (block 412), in other embodiments the efficiency threshold is adjusted after each command sent in the streak. In such case, the efficiency threshold is updated at block 416 before calculating the efficiency indicator value. In some embodiments, a counter is employed to track the length of the current streak, and the efficiency threshold is adjusted to require a higher efficiency after each command sent based on the value of the counter” (Shen [0057] the threshold is adaptive since it is adjustable)
“In some embodiments, the depicted process is employed together with efficiency monitoring techniques such as those of FIG. 4 or FIG. 5. Generally, the process improves the efficiency of command streaks by allowing row activate (ACT) commands from the cross-mode to occur toward the end of a streak of current-mode commands, in order to hide page open latency of a page miss/conflict request for the cross mode” (Shen [0065])
Regarding Claim 15, Shen discloses a method for use in a memory controller, comprising:
“FIG. 2 illustrates in block diagram form a memory controller 200 that is suitable for use in an APU like that of FIG. 1. Memory controller 200 includes generally a memory channel controller 210 and a power controller 250. Memory channel controller 210 includes generally an interface 212, a memory interface queue 214, a command queue 220, an address generator 222, a content addressable memory (CAM) 224, replay control logic 231 including a replay queue 230, a refresh control logic block 232, a timing block 234, a page table 236, an arbiter 238, an error correction code (ECC) check circuit 242, an ECC generation block 244, a data buffer 246, and refresh logic 247” (Shen [0028])
selecting current-mode memory access requests from a command queue and sending them to a memory interface queue that causes them to be transmitted over a memory channel;
“An arbiter is connected to the command queue for selecting entries from the command queue, and placing them in the memory interface queue causing them to be transmitted over the memory channel. The arbiter is operable to transact streaks of consecutive read commands and streaks of consecutive write commands over the memory channel. The arbiter has a current mode indicating the type of commands currently being transacted, and a cross mode indicating the other type” (Shen [0014])
selecting cross-mode activations during a streak of accesses of a current mode in response to a number of cross-mode accesses in the command queue exceeding an adaptive threshold; and subsequently entering a cross mode.
“An arbiter is connected to the command queue for selecting entries from the command queue, and placing them in the memory interface queue causing them to be transmitted over the memory channel. The arbiter is operable to transact streaks of consecutive read commands and streaks of consecutive write commands over the memory channel. The arbiter has a current mode indicating the type of commands currently being transacted, and a cross mode indicating the other type. The arbiter is operable to monitor commands in the command queue for the current mode and the cross mode, and in response to designated conditions including a designated minimum threshold of cross mode commands being available at the arbiter, send an available cross mode ACT command for a cross-mode command to the memory interface queue while continuing to operate in the current mode. In response to an end streak condition, the arbiter swaps the current mode and the cross mode, and transacts the cross-mode command” (Shen [0014])
“While in this embodiment a low efficiency threshold is adjusted to a high efficiency threshold (block 412), in other embodiments the efficiency threshold is adjusted after each command sent in the streak. In such case, the efficiency threshold is updated at block 416 before calculating the efficiency indicator value. In some embodiments, a counter is employed to track the length of the current streak, and the efficiency threshold is adjusted to require a higher efficiency after each command sent based on the value of the counter” (Shen [0057] the threshold is adaptive since it is adjustable)
“In some embodiments, the depicted process is employed together with efficiency monitoring techniques such as those of FIG. 4 or FIG. 5. Generally, the process improves the efficiency of command streaks by allowing row activate (ACT) commands from the cross-mode to occur toward the end of a streak of current-mode commands, in order to hide page open latency of a page miss/conflict request for the cross mode” (Shen [0065])
Regarding Claims 2, 9, and 16, Shen further discloses wherein: the current mode comprises one of a read mode and a write mode; and
“In operation, arbiter 238 selects memory access commands from command queue 220 and refresh control logic 232 by taking into account the current mode (indicating whether a read streak or write streak is in progress), the page status of each entry, the priority of each memory access request, and the dependencies between requests” (Shen [0040])
a cross mode comprises another one of the read mode and the write mode.
“The arbiter has a current mode indicating the type of commands currently being transacted, and a cross mode indicating the other type” (Shen [0014])
Regarding Claims 3 and 10, Shen further discloses wherein: the arbiter subsequently switches to a cross mode in response to a number of current-mode low-cost accesses being zero.
“In some embodiments, the efficiency indicator is calculated as a “cost” indicator, in which a high cost indicates inefficiency and a low cost indicates an efficient command” (Shen [0054])
“At block 516, it checks whether there are high-efficiency commands available for the current mode. If so, the process continues the current streak. If not, the process goes to block 518 where it ends the current streak. Ending the streak in each depicted case causes a turnaround process in which a streak of the other mode is begun. The turnaround includes clearing in-process tags for the cross mode (former current mode) and clears a wait-in-progress tag for the new current mode” (Shen [0063])
Regarding Claims 4, 11, and 17, Shen further discloses wherein in response to switching to the cross mode, the arbiter is further operable to: take a snapshot of the number of cross-mode accesses in the command queue; and modify the adaptive threshold according to the snapshot to form a next adaptive threshold.
“The particular conditions that will cause a streak to end varies in different embodiments. For example, the process of FIG. 4 or FIG. 5 may be used, or other processes may be used. In an example alternative embodiment, the length of a streak is determined by a snapshot, or count, of how many commands are available to be used in the streak at the start of the streak. Such a snapshot is often a good indicator of how long a streak can be and remain efficient. In such case, the end of streak condition at block 614 would be the size of the streak was equal to the count made of available commands the time the streak began (the snapshot). In response to an end streak condition at block 614, the process goes to block 616 where it ends the current streak, swaps the current mode and the cross mode, and begins transacting the cross-mode commands including any cross-mode command for which an ACT command was sent at block 612” (Shen [0068] the snapshot is taken when the mode changes/streak begins)
“While in this embodiment a low efficiency threshold is adjusted to a high efficiency threshold (block 412), in other embodiments the efficiency threshold is adjusted after each command sent in the streak. In such case, the efficiency threshold is updated at block 416 before calculating the efficiency indicator value. In some embodiments, a counter is employed to track the length of the current streak, and the efficiency threshold is adjusted to require a higher efficiency after each command sent based on the value of the counter” (Shen [0057] the counter would be use to update the threshold until the count hits the number indicated by the snapshot)
Regarding Claims 5, 12, and 18, Shen further discloses wherein the arbiter is further operable to: allow the cross-mode activations during a subsequent streak of accesses of the current mode in response to a subsequent number of cross-mode accesses present in the command queue exceeding the next adaptive threshold.
“If not, the process goes to block 608, where it checks if available write commands, which are currently the cross mode, are greater than or equal to a designated minimum threshold. If so, the process is allowed to send cross-mode ACT commands, and block 610 checks whether there are available ACT commands associated with write commands. If so, a cross-mode ACT command is selected and sent at block 612” (Shen [0067])
“If not, the process goes to block 708, where it checks if available read commands, which are currently the cross mode, are greater than or equal to a designated minimum threshold. If so, the process is allowed to send cross-mode ACT commands, and block 710 checks whether there are available ACT commands associated with write commands. The designated minimum threshold is a read threshold when read commands are the cross mode, and a write threshold different from the read threshold when write commands are the cross mode (FIG. 6). The read threshold is preferably lower than the write threshold” (Shen [0070])
Regarding Claims 6, 13, and 19, Shen further discloses wherein the arbiter is further operable to: select a plurality of cross-mode activate commands to execute starting at a predetermined offset before changing from the current mode to the cross mode, wherein the predetermined offset is a number of commands based on at least one memory timing parameter; and
“Following certain selected commands, the command bus has available times in which ACT commands may be transmitted to perform row activates for read or write commands. The process needs to select from among ACT commands available at the arbiter to be sent in order to fill the available times and make efficient use of the command bus” (Shen [0066])
“If not, the process goes to block 608, where it checks if available write commands, which are currently the cross mode, are greater than or equal to a designated minimum threshold. If so, the process is allowed to send cross-mode ACT commands, and block 610 checks whether there are available ACT commands associated with write commands. If so, a cross-mode ACT command is selected and sent at block 612” (Shen [0067] the minimum threshold is the indicates the predetermined offset)
“Generally the calculated efficiency indicator is compared to a designated threshold to determine if the cross-mode command is high efficiency. If the indicator is the CAS-to-CAS interval calculated directly in clock cycles, this indicator may be treated as a cost function in which low cost signals high efficiency. The threshold to which the value is compared, in some embodiments, is based on at least partially the time it takes to turnaround the process to start a new streak” (Shen [0061] the threshold is based on the CAS timing parameter)
change to the cross mode when the command queue no longer stores any low-cost current-mode page hit commands.
“At block 516, it checks whether there are high-efficiency commands available for the current mode. If so, the process continues the current streak. If not, the process goes to block 518 where it ends the current streak. Ending the streak in each depicted case causes a turnaround process in which a streak of the other mode is begun” (Shen [0063])
Response to Arguments
Applicant's arguments filed September 01, 2026 have been fully considered but they are not persuasive.
Applicant Argues:
a) (page 8 top) For the avoidance of doubt, and in the interests of removing this issue from further proceedings, Applicant amends claim 15 to recite "selecting cross-mode activations during a streak of accesses of a current mode in response to a number of cross-mode accesses in the command queue exceeding an adaptive threshold". Thus the language that caused the Office to interpret this portion of claim 15 to be a contingent limitation has been amended so that the recited function must be performed and it is no longer even arguable a contingent limitation.
With respect to (a), this amendment does not fix the contingency in the claim. The claim limitation of allowing/selecting cross-mode activations … is still contingent upon “a number of cross mode accesses in the command queue exceeding an adaptive threshold”. If this threshold is never exceeded the limitation of allowing/selecting cross-mode activations never happen.
b) (page 9 middle) The Examiner's Answer repeated the rejection of claims 1-6, 8-13, and 15-19 under 35 U.S.C. §102(a)(1) over U.S. Patent Publication No. 2021/0390071 (Shen). Applicant again notes that the elements in the prior art Shen patent are not "arranged as in the claim" as in any of independent claims 1, 8, and 15, and thus Shen does not anticipate them, for the reasons set forth in the Appeal Brief. Applicant respectfully requests the reconsideration of its arguments to avoid a costly and lengthy appeal.
With respect to (b), Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
Applicant's assertion that the elements of independent claims 1, 8, and 15 are not “arranged as in the claim” has already been addressed in the Examiner's Answer to the Appeal Brief on page 10. Applicant does not present any new arguments or identify any specific deficiency in the Examiner's previous analysis. Accordingly, Applicant's argument does not overcome the rejection, and the rejection of claims 1-6, 8-13, and 15-19 under 35 U.S.C. § 102(a)(1) over Shen is maintained.
Allowable Subject Matter
Claims 7, 14, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 7, 14, and 20, includes the specific details of, “wherein the arbiter modifies the adaptive threshold further to based on: a minimum cross-mode threshold, wherein the minimum cross-mode threshold is a constant; and a difference between a first number of commands indicated by the snapshot and an offset, wherein the offset corresponds to a time that hides an overhead of changing to the cross mode and the offset is a second number of commands based on at least one memory timing parameter”, in combination with the other elements recited in the independent and intermediate claims, are not found in the prior art of record.
Conclusion
All claims are identical to or patentably indistinct from, or have unity of invention with claims in the application prior to the entry of the submission under 37 CFR 1.114 (that is, restriction (including a lack of unity of invention) would not be proper) and all claims could have been finally rejected on the grounds and art of record in the next Office action if they had been entered in the application prior to entry under 37 CFR 1.114. Accordingly, THIS ACTION IS MADE FINAL even though it is a first action after the filing of a request for continued examination and the submission under 37 CFR 1.114. See MPEP § 706.07(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.L./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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