Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/29/2025 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Balasubramanian et al. (US 11764664 B2 and Balasubramanian hereinafter.) in view of Tsai et al. (US 9432005 B2 and Tsai hereinafter.).
Regarding claim 1, Balasubramanian discloses [fig. 1] an apparatus comprising: a first transistor [158] coupled between a power input [Vbat] and a power output [102 driven by transistors], the first transistor having a first transistor control terminal [gate]; a second transistor [164] coupled between the power input and the power output [as shown], the second transistor having a second transistor control terminal [gate]; first driver circuitry [146] having an input and an output [as shown], the output of the first driver circuitry coupled to the first transistor control terminal [as shown]; second driver circuitry [152] having an input and an output [as shown], the output of the second driver circuitry
However, Tsai discloses [fig. 2] circuitry [221 and associated circuitry] coupled between the first [211] and second transistor [212] control terminals [as shown], the circuitry configurable to provide a current path between the first and second transistor control terminals [221 turned on, producing current through 221] responsive to the second transistor being enabled or the second transistor control terminal having a higher voltage than the first transistor control terminal [both 211 and 212 activated]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Balasubramanian to include circuitry coupled between the first and second transistor control terminals, the circuitry configurable to provide a current path between the first and second transistor control terminals responsive to the second transistor being enabled or the second transistor control terminal having a higher voltage than the first transistor control terminal as taught by Tsai to improve failsafe functionality in a power switching circuit.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Balasubramanian in view of Tsai further in view of Sugawara et al. (US 20200099285 A1 and Sugawara hereinafter.).
Regarding claim 2, Balasubramanian in view of Tsai discloses all the features regarding claim 1 as indicated above. Balasubramanian in view of Tsai does not explicitly disclose further comprising voltage clamp circuitry coupled between the power input and the first transistor control terminal.
However, Sugawara discloses [fig. 1] further comprising voltage clamp circuitry [35] coupled between the power input [VCC] and the first transistor control terminal [gate of 25]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Balasubramanian in view of Tsai to include further comprising voltage clamp circuitry coupled between the power input and the first transistor control terminal as taught by Sugawara to improve reliability in driving of switching device in wide range of voltage of high voltage system.
Regarding claim 3, Balasubramanian in view of Tsai further in view of Sugawara discloses further wherein the voltage clamp circuitry includes at least one Zener diode [as shown].
Allowable Subject Matter
Claims 4-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 8-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 8 is allowed because the prior art of record does not disclose nor render obvious “A system comprising: a first transistor having a first terminal, a second terminal, and a control terminal; a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor, the second terminal of the second transistor coupled to the second terminal of the first transistor; and gate balancing circuitry including: current source circuitry having a terminal; a resistor having a first terminal and a second terminal, the first terminal of the resistor coupled to the terminal of the current source circuitry, the second terminal of the resistor coupled to the control terminal of the second transistor; and a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor coupled to the control terminal of the first transistor, the second terminal of the third transistor coupled to the control terminal of the second transistor and the second terminal of the resistor, the control terminal of the third transistor coupled to the terminal of the current source circuitry and the first terminal of the resistor.” as cited with the rest of the claimed limitation.
Claim 15 is allowed because the prior art of record does not disclose nor render obvious “A device comprising: a first transistor having a first terminal, a second terminal, and a control terminal; a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor, the second terminal of the second transistor coupled to the second terminal of the first transistor; voltage clamp circuitry having a first terminal and a second terminal, the first terminal of the voltage clamp circuitry coupled to the first terminal of the first transistor and the first terminal of the second transistor, the second terminal of the voltage clamp circuitry coupled to the control terminal of the first transistor; and circuitry configurable to: set a first voltage of the control terminal of the first transistor equal to a second voltage of the control terminal of the second transistor; allow the voltage clamp circuitry to clamp the control terminal of the first transistor; and disconnect the voltage clamp circuitry from the control terminal of the second transistor.” as cited with the rest of the claimed limitation.
Dependent claims 9-14 and 16-20 are allowed.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES G YEAMAN whose telephone number is (571)272-5580. The examiner can normally be reached Mon - Fri 954 Schedule.
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/JAMES G YEAMAN/Examiner, Art Unit 2842
/LINCOLN D DONOVAN/Supervisory Patent Examiner, Art Unit 2842