Prosecution Insights
Last updated: October 04, 2026
Application No. 18/374,262

COMPILING METHOD, RUNNING METHOD, AND RELATED PRODUCT

Non-Final OA §103§112
Filed
Sep 28, 2023
Priority
Dec 28, 2022 — CN 202211700640.4
Examiner
VO, TED T
Art Unit
2144
Tech Center
2100 — Computer Architecture & Software
Assignee
Shanghai Cambricon Information Technology Co. Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
669 granted / 824 resolved
+26.2% vs TC avg
Moderate +9% lift
Without
With
+9.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
10 currently pending
Career history
839
Total Applications
across all art units

Statute-Specific Performance

§101
15.9%
-24.1% vs TC avg
§103
40.5%
+0.5% vs TC avg
§102
15.0%
-25.0% vs TC avg
§112
15.2%
-24.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 824 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This action is in response to the claimed listing filed on 09/28/2023. Claims 1-15 are pending. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As per claims 1-12: Claim 1 recites “A compiling method for a computing graph” set forth in the claimed preamble. Thus, the claim sets for “a computing graph” performed in the method. Claim 1 then recites "a computing graph" in line indicated as 5. Thus, it recites two different computing graphs. The claim recites "the computing graph" in lines 5, 6, in lines 7,8, and in line 11. With the limitations of "the computing graph" recited in various lines after line 5, there are insufficient antecedent basis for "the computing graph", in the claim, and thus the claim would be rejected under 35 USC 112(b). It would require amending the claim for having sufficient antecedent basis in the limitations. For expediting the claimed examination, "a computing graph" in line 5 is interpreted with "the computing graph". - Claims 2-12 are dependent, and thus they bear the limitations addressed above in claim 1, and would be rejected the same under 35 USC 112(b). As per claims 13-14: Claim 13 recites “A running method for a computing graph” set forth in the claimed preamble. Thus, the claim sets for “a computing graph” performed in the method. At the line indicated as 5, claims recite “loading a runtime file of a computing graph”. At the line 12, claims recite “acquiring a computing graph of a neural network”. In a similar manner to claim 1, the limitations of "the computing graph" recited in various lines after line 5, there are insufficient antecedent basis for "the computing graph", in the claims. Claim 14 depends on claim 13, and thus the claims 13-14 would be rejected under 35 USC 112(b). It would require amending the claims for having sufficient antecedent basis in the limitations. For expediting the claimed examination, "a computing graph" in line 5 is interpreted with "the computing graph". It should be noted that the recitation “acquiring a computing graph of a neural network” if replaces “a” by “the”, it would still have the claim being indefinite for reciting a broad range “a/the computing graph (in the claimed preamble) together with a narrow range “computing graph of a neural network” fall within the broad range (See MPEP § 2173.05(c)). Therefore, the claimed limitation in line 12 should be amended to avoid broad range/narrow range and give the limitation a sufficient antecedent basis. As per claim 15: Claim 15 recites “A computing apparatus, configured to run a computing graph” set forth in the claimed preamble. Thus, the claim sets for “a computing graph” performed in the apparatus. At the line 7, claim recites “loading a runtime file of a computing graph”. At the line 14, claim recites “acquiring a computing graph of a neural network”. The claim would be rejected in the same manner in claims 13-14 and would require amending as being suggested in claims 13-14. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-8, 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn, "Compilation and Optimization Techniques for Machine Learning Workloads", 2022, Department of Computer Science and Engineering, University of California, San Diego, 13 pages, in view of Sivalingam et al., "Graph compilers for AI training and inference", 2020, https://www.sodalite.eu/sites/default/files/sodalite/public/content-files/articles/graph-compilers-proof2-blog.pdf , 6 pages. As per Claim 1: Ahn discloses the limitations in bold below: 1. A compiling method for a computing graph, implemented by a processing apparatus, the compiling method comprising: acquiring a computing graph of a neural network model (p. 2-3, Symbolic graph execution, DNN model, and Figure 2), wherein input data of the computing graph is configured with one or a plurality of groups of variable input ranges (Figure 2, and p. 5, Figure 3, with x, y in Code template/Optimized Code as inputs to Optimizing Compier) for each group of variable input range (Figure 3, x, y “in range(…)”), compiling and optimizing the computing graph to generate a corresponding performance optimization graph (Figure 3: Optimizing Compiler, Figure 1: Graph Optimizer) ; and storing each group of variable input range in association with a corresponding performance optimization graph (Figure 3, in Optimized Code, ky, kx in range(…), and Figure 1: Graph Optimizer) to generate a runtime file (Figure 3, in Optimized Code: output[y][x]) to be assigned to a computing apparatus to perform a task corresponding to the (Figure 1: Hardware; Figure 3: Optimized Code to Hardware). Ahn does not explicitly specify the graph as a “computing graph” of a neural network model, but Ahn acquired a graph representation of the Deep Neural Networks (DNN) model. DNN is a neural network model. Ahn shows the inputs determined in a group of variable ranges and performing graph optimization to generate runtime output as seen in Figures 1–3. Sivalingam discloses “computing graph” (p. 2 in DL Frameworks, second text portion: “DNN models are usually represented as computational graphs, with nodes representing tensor operators, and edges the data dependencies between them. This computational graph is then used to further optimise for different hardware back-ends. Optimisations may include operator fusion, memory latency hiding, and mapping to hardware primitives. ” and See Figure 1 in p. 1: Input as x1,..xr or i1…in). The input of the computing graph in Sivalingam representing nodes as variables x1,..xr and inputs in the Ahn with x, y into the graph optimizer suggest a regulation or requirement for implementing input data in the neural network model. Therefore, it would be obvious to an ordinary of skills in the art before the effective filing of the application to combine the compilation and optimization of graphs with a group of variables determined in range of Ahn and the mention of the compiling and optimizing computing graph in a neural network model. The combination would yield predictable results because it would be for conforming to regulations and requirements when using a neural network model. As per Claim 2: Ahn and combining Sivalingam, where Ahn further discloses the limitation in bold below: 2. The compiling method of claim 1, further comprising: adjusting the one or the plurality of variable input ranges based on hardware information of the computing apparatus that is to perform the computing graph (Ahn: Figure 3, Hardware Measurement and Optimized Code, and expression in Optimized Code in the box: input[y+ky][x+kx] * kernel[ky][kx] where y+ky, x+kx read on variable input ranges. See sec. 3.2 Model Compression, and referred to Pruning. It should be noted that Pruning is well-known as a machine learning optimized technique that adjusts to reduce model size, computation code and memory usage); and compiling and optimizing the computing graph to generate the corresponding performance optimization graph based on each group of adjusted variable input range. (Ahn, entire Figure 3) Ahn does not explicitly specify the graph as a “computing graph” and Sivalingam discloses “computing graph” as addressed in the combination rationale provided in claim 1. As per Claim 3: Ahn and combining Sivalingam, where Ahn further discloses: 3. The compiling method of claim 2, wherein the adjusting of the one of the plurality of variable input ranges comprises: based on hardware optimization characteristics of the computing apparatus, splitting the one or the plurality of groups of variable input ranges into a plurality of groups of variable input ranges suitable for the hardware optimization characteristics. (Ahn: Figure 3, Hardware measurement and Optimized code τ(Θ*) read on hardware optimization characteristics of the computing apparatus of the claim. Optimized Code in the box as well as input[y+ky][x+kx] * kernel[ky][kx] reads on claiming splitting the one or the plurality of groups of variable input ranges suitable for the hardware optimization characteristics.) As per Claim 4: Ahn and combining Sivalingam, where Ahn further discloses: 4. The compiling method of claim 1, wherein the one or the plurality of groups of variable input ranges are configured by: setting two mandatory fields for each input, which are min and max, to represent a variable input range of the input, wherein the min represents a minimum value of the variable input range, and the max represents a maximum value of the variable input range. (Ahn Figure 3: Optimized Code in the box with the range set to 0, kernel height, or 0, kernel_width read on claiming mandatory fields for each input, which are min and max ) As per Claim 5: Ahn and combining Sivalingam, where Ahn further discloses: 5. The compiling method of claim 4, wherein the one or the plurality of groups of variable input ranges are further configured as follows: the min and max fields comprise the setting of a corresponding group count to form a variable input range of the corresponding group count. (Ahn Figure 3: Optimized Code in the box with the input[y+ky][x+kx] and [y+ky][x+kx] in the range set from 0 to kernel_height, or 0 to kernel_width read on claiming the min and max fields comprise the setting of a corresponding group count to form a variable input range of the corresponding group count) As per Claim 6: Ahn and combining Sivalingam, where Ahn further discloses: 6. The compiling method of claim 4, wherein the one or the plurality of groups of variable input ranges are further configured by: setting an optional field for each input, which is opt, wherein the opt represents a preferred value in the variable input range that is set. (Ahn Figure 3: Template Code and Optimized Code in the boxes, where height.inner, width.inner read on optional field and set with 32, 16... etc.) As per Claim 7: Ahn and combining Sivalingam, where Ahn further discloses: 7. The compiling method of claim 6, wherein the one or the plurality of groups of variable input ranges are further configured by: for each group of variable input range, setting one or a plurality of groups of preferred values for the opt field through a two-dimensional array (Ahn: Figure 3, and expressions in boxes such as input[y+ky][x+kx] represent two dimension array ), wherein in the same group of variable input range, a group count of a preferred value of an opt set by each input is the same. (Ahn Figure 3: Template Code and Optimized Code in the boxes, where height.inner, width.inner read on optional field and set with 32, 16... etc.) As per Claim 8: Ahn and combining Sivalingam, where Ahn further discloses: 8. The compiling method of claim 1, wherein, for each group of variable input range, compiling and optimizing the computing graph comprises: deriving an output shape range of each node in the computing graph according to the variable input range to perform optimization based on the derived output shape range. (Ahn, see Figure 3 and Optimized Code in the box with the expression output[y][x] = input[y+ky][x+kx] * kernel[ky][kx] reads on a shape an array or square, etc.) As per Claim 13: Ahn discloses the limitations in bold below: 13. A running method for a computing graph, implemented by a computing apparatus, the running method (Figure 1 in p. 2) comprising: loading a runtime file of a computing graph, (In Figure 1, Output 1 of DNN model as Graph Representation is input to Graph Optimizer. Figure 3 in p. 5, code template to Optimizing compiler) wherein the runtime file has a plurality of groups of variable input ranges and corresponding performance optimization graphs that are stored in association with the plurality of groups of variable input ranges (Figure 3, in Code Template, and in Optimized Code, with y, x, ky, kx in range(…); according to an input value at runtime, selecting a performance optimization graph corresponding to a group of variable input range hit by the input value (Figure 1, and Figure 3, variables y, x, ky, kx in Figure 3); and running the selected performance optimization graph; (Figure 1, Graph Optimizer’s output to be input of Execution Engine) Regarding the limitations in bold below: wherein the runtime file is generated according to a compiling method of: acquiring a computing graph of a neural network model, wherein input data of the computing graph is configured with one or a plurality of groups of variable input ranges; for each group of variable input range, compiling and optimizing the computing graph to generate a corresponding performance optimization graph; and storing each group of variable input range in association with a corresponding performance optimization graph to generate the runtime file to be assigned to a computing apparatus to perform a task corresponding to the computing graph. The claimed limitations above recite the same as limitations of claim 1, and would be addressed the same in claim 1. Ahn does not explicitly specify the graph as a “computing graph” of a neural network model, but Ahn acquired a graph representation of the Deep Neural Networks (DNN) model. DNN is a neural network model. Ahn shows the inputs determined in a group of variable ranges and performing graph optimization to generate runtime output as seen in Figures 1–3. Sivalingam discloses “computing graph”. See rationales addressed in claim 1 as well as the motivation for combination. As per claim 14: Ahn and combining Sivalingam, where Ahn further discloses: 14. The running method of claim 13, wherein the group of variable input range hit by the input value comprises followings: the input value falls into the variable input range; or the input value equals the variable input range. (See Ahn, Figure 3, …in range(…) in Code Template and Optimized Code) As per claim 15: Claim 15 is directed to a computing apparatus and recites the limitations corresponding to the limitations of claim 13. The rejection of the claim is addressed the same to the rationales of claim 13. Allowable Subject Matter Claims 9-12 are rejected as being indefinite under 35 USC 112(b). The claims are objected to under the applied prior arts. The claims would be allowable if rewritten in independent form, including all the limitations of the base claim and any intervening claims, and provided with amendment to overcome the issue under 35 USC 112(b). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ted T Vo whose telephone number is (571)272-3706. The examiner can normally be reached 8am-4:30pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wei Y Mui can be reached at (571) 272-3708. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TTV September 18, 2026 /Ted T. Vo/ Primary Examiner, Art Unit 2191
Read full office action

Prosecution Timeline

Sep 28, 2023
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
90%
With Interview (+9.3%)
3y 2m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 824 resolved cases by this examiner. Grant probability derived from career allowance rate.

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