Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The present application having Application No. 18/374,263 filed on 9/28/2023.
Claims 1-20 are currently pending.
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 12/28/2023, 03/26/2024, 04/02/2025. and 10/07/2025 are acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
a scalable input/output virtualization (SIOV) device configured to receive a data structure… (e.g. Spec: (0064) the SIOV device 104, which receives and stores the data structure 302 at an address 306 in device memory 112. In addition, the host processor 102 generates a work descriptor 308 that includes a pointer 310 to the address 306 in the device memory 112 where the data structure 302 is stored.) store the data structure… (e.g. Spec: (0064) the SIOV device 104, which receives and stores the data structure 302 at an address 306 in device memory 112. In addition, the host processor 102 generates a work descriptor 308 that includes a pointer 310 to the address 306 in the device memory 112 where the data structure 302 is stored.) receive a work descriptor… (e.g. Spec: (0054) The scheduler 118 of the SIOV device 104 receives the batch work descriptors 204a, 204b and accepts (e.g., enqueues) the batch work descriptors 204a, 204b into the shared work queue 120. Notably, the batch work descriptors 204a, 204b are submitted and enqueued in accordance with the order 128, e.g., the first batch work descriptor 204a is enqueued before the second batch work descriptor 204b in the shared work queue 120.) and process the tasks… (e.g. Spec: (0055) Upon encountering the first batch work descriptor 204a in the shared work queue 120, the scheduler 118 retrieves the first task grouping 130a from the address 202a indicated by the pointer 206a of the first batch work descriptor 204a. Further, the SIOV device 104 processes the first task grouping 130a in accordance with the formatting performed by the host processor 102. To do so, the scheduler 1 18 dispatches the four tasks 124 (e.g., T1, T2, T3, T4) of the first task grouping 130a to the backend hardware resources 116 for processing, and then stalls until the four tasks 124 have completed based on the barrier 132a.) in claim 18
a SIOV device is configured to iteratively pop a task … (e.g. Spec: (0065) Here, "popping" a task 124 or barrier 132 means that the task 124 or the barrier 132 is obtained and subsequently deleted from the priority queue.) in claim 19
a SIOV device is configured to enqueue the work descriptor … (e.g. Spec: (0054) accepts (e.g., enqueues) the batch work descriptors 204a, 204b into the shared work queue 120. Notably, the batch work descriptors 204a, 204b are submitted and enqueued in accordance with the order 128, e.g., the first batch work descriptor 204a is enqueued before the second batch work descriptor 204b in the shared work queue 120.) in claim 20
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marolia et al. (US 20210004338 A1) (hereinafter Marolia) in view of Iorio et al (US 20120084789 A1).
As per claim 1, Marolia discloses a system, comprising: a scalable input/output virtualization (SIOV) device (e.g. Marolia: (0019) “multi-PASID” scalable IOV devices are provided. (0021) these IOV devices are called helper devices. Please note the multi-PASID scalable IOV device/helper devices correspond to the Applicant’s SIOV device.). and submitting [ ] to the SIOV device, thereby directing the SIOV device [ ] (e.g. Marolia: (0029) In a third operation (3), VDev 330 submits the work submission to multi-PASID helper device 310. Please note the multi-PASID helper device 310 corresponds to the Applicant’s SIOV device.).
Marolia does not disclose and a host processor, configured to perform operations including: receiving a task graph including tasks and indicating dependencies between the tasks; formatting the task graph, in part, by sorting the tasks of the task graph in an order based on the dependencies between the tasks; and submitting [ ] to the SIOV device, thereby directing the SIOV device [ ].
However, Iorio discloses and a host processor, configured to perform operations including: receiving a task graph including tasks and indicating dependencies between the tasks (e.g. Iorio: (Fig. 5A) (0038) the optimization engine 102 receives a task graph for optimization from the application 304. a task aggregation topology indicates which tasks in the task graph are to be aggregated into a macro-task and which tasks are independent of one another. Please note the optimization engine corresponds to the Applicant’s host processor, and the task graph corresponds to the Applicant’s task graph.); formatting the task graph, in part, by sorting the tasks of the task graph in an order based on the dependencies between the tasks (e.g. Iorio: (Figs. 2A and 2B) (0022) When optimizing the task graph, the optimization engine 102 performs multiple iterations of runtime optimization operations on the task graph. At each iteration, an optimized task graph is generated based on a different task aggregation topology. Please note optimizing the task graph corresponds to the Applicant’s sorting the tasks.); and submitting the formatted task graph (e.g. Iorio: (0034) The most optimal aggregation topology identified yet is used to generate an optimized task graph that is transmitted to the application 304 for execution. Please note the optimized task graph corresponds to the Applicant’s formatted task graph, and “that is transmitted” corresponds to the Applicant’s submitting step. ) [ ] to process the tasks of the task graph based on the order (e.g. Iorio: (0005) The task dependency graph indicates the dependency between each pair of tasks and the order in which tasks are to be executed. Please note the “to be executed” corresponds to the Applicant’s “process the tasks”, and “the order in which tasks are executed” corresponds to the Applicant’s “based on the order”.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method/system of the receiving and formatting of task graphs as taught by Iorio into -the “multi-PASID” scalable IOV device of Marolia to ensure more efficient processing of tasks and reduced overhead on a computing device (See Iorio: (0006) (0007) (0010)).
As per claim 2, the combination of Marolia and Iorio discloses the system of claim 1 (See rejection to claim 1 above), wherein sorting the tasks includes sorting the tasks of the task graph in the order using a topological sorting algorithm (e.g. Iorio: (0038) generates an initial task aggregation topology for the different tasks specified by the task graph.).
Claim(s) 3-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Marolia and Iorio in view of Kim et al (US 20190179670 A1) (hereinafter Kim).
As per claim 3, the combination of Marolia and Iorio discloses the system of claim 1, wherein formatting the task graph includes [ ], sorting the tasks includes sorting the tasks in the order across the task groupings (e.g. Iorio: (0023) the optimization engine 102 compiles tasks according to a pre-determined task aggregation topology to generate units of work associated with the tasks. The task aggregation topology indicates which tasks in the task graph are to be aggregated into a macro-task), one or more work descriptors (e.g. Marolia: (0029) smart controller 306 fetches the descriptor and prepares the corresponding descriptors for the helper device. Please note the descriptor corresponds to the Applicant’s descriptor.) identifying the task groupings (e.g. Iorio: (0029) the nodes 204 and 206 in FIG. 2A are aggregated to generate a corresponding macro-node 210. Please note the nodes 204 and 206 corresponds to the Applicant’s tasks, and the macro-node 210 corresponds to the Applicant’s task grouping.).
The combination of Mario and Iorio does not disclose partitioning the task graph into task groupings each including one or more tasks [ ] and submitting the formatted task graph includes submitting, to a shared work queue of the SIOV device.
However, Kim discloses partitioning the task graph into task groupings each including one or more tasks (e.g. Kim: (Fig. 7) (0087) may set a wait task considering the dependency between tasks. (0088) the arbiter circuit 821 of the SCQ circuit 800 may designate wait task2 835 for the queue storage device 822 so that the other tasks are not processed until the tasks corresponding to blocks 721 and 722 of FIG. 7 are processed. Please note “set a wait task” corresponds to the Applicant’s portioning step. ) [ ] and submitting the formatted task graph includes submitting, to a shared work queue of the SIOV device (e.g. Kim: (0054) the control circuit 210 is defined as a shared command queue (SCQ) circuit. (0077) the plurality of cores 230 may be configured to transmit a task processing request to the SCQ circuit 300. Please note the shared command queue corresponds to the Applicant’s shared work queue.),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method/system of -a shared work queue as taught by Kim into the SIOV device and formatted task graphs of the combination of Marolia and Iorio because it increases processing speed and efficiency by allowing for a centralized load balancing helping reduce bottleneck problems with multiple queues and starvation that slow down processing (See Kim: (0006) (0051) (0054)).
As per claim 4, the combination Marolia, Iorio, and Kim discloses the system of claim 3 (See rejection to claim 3 above), wherein a respective task grouping of the task groupings includes multiple tasks and one or more dependencies between the multiple tasks (e.g. Iorio: (Figs. 2A and 2B) (0028) node 204 is associated with Task 4 and node 206 is associated with Task 4a. (0029) the nodes 204 and 206 in FIG. 2A are aggregated to generate a corresponding macro-node 210. Please note the macro-node 210 corresponds to the Applicant’s task grouping, and the associated nodes corresponds to the Applicant’s dependency between tasks.), and formatting the task graph includes inserting barriers in between the multiple tasks of the respective task grouping based on the one or more dependencies (e.g. Kim: (0087) the SCQ circuit 800 may designate wait task1 832 for a queue storage device 822 (e.g., 314 in FIG. 3) so that the other tasks are not processed until the task corresponding to block 711 of FIG. 7 is processed. Please note the wait task corresponds to the Applicant’s barrier.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method/system of -inserting wait tasks as taught by Kim into the SIOV device and formatted task graphs of the combination of Marolia and Iorio because it helps avoid any runtime and dependency errors allowing for better resiliency in the system as the SIOV device enforces the dependencies strictly without constant synchronization calls back to the CPU (See Kim: (0006) (0053)).
As per claim 5, the combination Marolia, Iorio, and Kim discloses the system of claim 3 (See rejection to claim 3 above), wherein a first task grouping includes a first set of tasks that are independent of one another (e.g. Kim: (Fig. 7) (0090) the other tasks are not processed until the tasks corresponding to blocks 741, 742, 743, and 744 are processed. Please note tasks corresponding to blocks 741, 742, 743, and 744 corresponds to the Applicant’s first task grouping.), and a second task grouping includes a second set of tasks having multiple dependencies on the first set of tasks of the first task grouping (e.g. Kim: (Fig. 7) (0086) tasks corresponding to block 751 and block 752 may have to be processed after the tasks corresponding to block 741, block 742, block 743, and block 744 are processed. Please note tasks correspond to block 751 and block 752 corresponds to a second task grouping.).
As per claim 6, the combination Marolia, Iorio, and Kim discloses the system of claim 5 (See rejection to claim 5 above), wherein formatting the task graph includes replacing the multiple dependencies with a single dependency between the first task grouping and the second task grouping (e.g. Kim: (Fig. 7) (0087) an SCQ circuit 800 may set a wait task considering the dependency between tasks. (0088) the arbiter circuit 821 of the SCQ circuit 800 may designate wait task2 835 for the queue storage device 822 so that the other tasks are not processed until the tasks corresponding to blocks 721 and 722 of FIG. 7 are processed. Please note “other tasks are not processed until block 721 and block 722 are processed” corresponds to the Applicant’s multiple dependencies, the wait task corresponds to the Applicant’s single dependency, and the “set a wait task” corresponds to the Applicant’s “replacing” step.), the single dependency represented by one barrier directing the SIOV device to stall until the first set of tasks have completed before processing the second set of tasks (e.g. Kim: (0088) the SCQ circuit 800 may designate wait task2 835 for the queue storage device 822 so that the other tasks are not processed until the tasks corresponding to blocks 721 and 722 of FIG. 7 are processed. Please note the wait task corresponds to the Applicant’s single dependency represented by one barrier.).
Claim(s) 7-9, 12, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Marolia and Iorio in view of Bachmutsky et al. (US 20190317802 A1) (hereinafter Bachmutsky).
As per claim 7, the combination Marolia and Iorio discloses the system of claim 1 (See rejection to claim 1 above), wherein formatting the task graph includes generating a data structure in which the tasks are arranged in the order (e.g. Iorio: (Figs. 2A and 2B) (0022) When optimizing the task graph, the optimization engine 102 performs multiple iterations of runtime optimization operations on the task graph. At each iteration, an optimized task graph is generated based on a different task aggregation topology. Please note the optimization operations corresponds the Applicant’s formatting, and the optimized task graph corresponds to the Applicant’s data structure.), and submitting the formatted task graph includes communicating the data structure (e.g. Iorio: (0034) the optimized task graph is transmitted to the application 302 for execution. Please note the optimized task graph corresponds to the Applicant’s data structure. Please note the graph is transmitted corresponds to the Applicant’s communicating step.).
The combination of Marolia and Iorio does not disclose for storage in device memory of the SIOV device.
However, Bachmutsky discloses for storage in device memory of the SIOV device (e.g. Bachmutsky: (0079) A work scheduler … store the descriptor items in memory. (0033) work scheduler 150 can be used in a single root input/output virtualization (SR-IOV) or Scalable I/O Virtualization (SIOV) virtual machine (VM)-enabled. Please note the work scheduler corresponds to the Applicant’s SIOV device.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method/system of -storing data in a memory on a SIOV device by Bachmutsky into the SIOV device and formatted task graphs of the combination of Marolia and Iorio because it helps reduce latency and processing speeds by reducing the need to access other computing devices or resources because the data is stored locally (See Bachmutsky: (0089) (0097) (0101)).
As per claim 8, the combination of Marolia, Iorio, and Bachmutsky discloses the system of claim 7 (See rejection to claim 7 above), wherein submitting the formatted task graph includes submitting a work descriptor (e.g. Marolia: (Fig. 3) (0029) guest VM 316 prepares descriptor in descriptor queue 320 and submits it to virtual device (VDev) 330 in smart controller 306. Please note the descriptor corresponds to the Applicant’s work descriptor), including a pointer to the data structure in the device memory (e.g. Bachmutsky: (0080) the work scheduler can access a pointer from work descriptor 602. At Action (2), the pointer can be used to access a UWD 604 from memory. UWD 604 can include an array of work commands[0]-[2]. Please note the pointer corresponds to the Applicant’s pointer, and the array of work commands corresponds to the Applicant’s data structure.), the pointer directing the SIOV device to obtain (e.g. Bachmutsky: (0080) the work scheduler can access a pointer from work descriptor 602. At Action (2), the pointer can be used to access a UWD 604 from memory. UWD 604 can include an array of work commands[0]-[2]. (0033) work scheduler 150 can be used in a single root input/output virtualization (SR-IOV) or Scalable I/O Virtualization (SIOV) virtual machine (VM)-enabled. Please note the pointer corresponds to the Applicant’s pointer, and the work scheduler corresponds to the Applicant’s SIOV device.) one or more tasks for processing, in part, by accessing the data structure in the device memory (e.g. Bachmutsky: (0080) the work scheduler can access a pointer from work descriptor 602. At Action (2), the pointer can be used to access a UWD 604 from memory. UWD 604 can include an array of work commands[0]-[2]. (0081) a work command is prepared for execution and in Action (5), the command is dispatched to accelerator[0] that executes the command. Please note the array of work commands corresponds to the Applicant’s data structure, and the work command corresponds to the Applicant’s one or more tasks.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method/system of utilizing pointers to point to addresses in memory as taught by Bachmutsky into the SIOV device and formatted task graphs of the combination of Marolia and Iorio because it reduces latency and bottleneck issues by accessing addresses in memory using lightweight pointers that are more efficient to parse (See Bachmutsky: (0089) (0097) (0101)).
As per claim 9, the combination of Marolia and Iorio discloses the system of claim 1 (See rejection to claim 1 above), wherein formatting the task graph includes generating a work descriptor (e.g. Marolia: (0029) smart controller 306 fetches the descriptor and prepares the corresponding descriptors for the helper device, as depicted by descriptor queue 328 in smart controller local memory 328. Please note the corresponding descriptors corresponds to the Applicant’s work descriptor.), but does not expressly disclose including one or more tasks and a pointer to one or more subsequent tasks in the order, the pointer directing the SIOV device to process the one or more subsequent tasks upon completion of the one or more tasks of the work descriptor.
However, Bachmutsky discloses including one or more tasks and a pointer to one or more subsequent tasks in the order (e.g. Bachmutsky: (0072) the work scheduler processes work descriptor (a) and provides work descriptor (a) in format for accelerator[0] to recognize and execute as intended. Descriptor (a) includes a pointer to next descriptor and its private metadata (b). Please note the next descriptor corresponds to the Applicant’s one or more subsequent tasks.), the pointer directing the SIOV device (e.g. Bachmutsky: (0033) work scheduler 150 can be used in a single root input/output virtualization (SR-IOV) or Scalable I/O Virtualization (SIOV) virtual machine (VM)-enabled example usage. Please note the Scalable I/O Virtualization (SIOV) virtual machine corresponds to the Applicant’s SIOV device.) to process the one or more subsequent tasks upon completion of the one or more tasks of the work descriptor (e.g. Bachmutsky: (0053) Tasks can be queued and delivered when previous task is completed so that tasks are not switched and context need not be saved or switched between task switching.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method/system of including subsequent tasks in a descriptor as taught by Bachmutsky into the SIOV device and formatted task graphs of the combination of Marolia and Iorio because it decreases latency and increases processing efficiency by reducing repetitive communication across the system BUS to fetch and parse descriptors (See Bachmutsky: (0002)).
As per claim 12, the combination of Marolia, Iorio, and Bachmutsky the system of claim 1 (See rejection to claim 1 above), wherein formatting the task graph includes generating a work descriptor (e.g. Marolia: (0029) smart controller 306 fetches the descriptor and prepares the corresponding descriptors for the helper device, as depicted by descriptor queue 328 in smart controller local memory 328. Please note the corresponding descriptors corresponds to the Applicant’s work descriptor.)
The combination of Marolia and Iorio does not expressly disclose that includes a pointer to a metadata object in memory, the pointer directing the SIOV device to obtain metadata from the metadata object and process the tasks of the task graph in accordance with the metadata.
However, Bachmutsky discloses that includes a pointer to a metadata object in memory (e.g. Bachmutsky: (0071) the work scheduler uses pointer in chain descriptor 502 to access global metadata 504 from memory. Please note the pointers corresponds to the Applicant’s pointer, and the global metadata 504 corresponds to the Applicant’s metadata object.), the pointer directing the SIOV device to obtain metadata from the metadata object and process the tasks of the task graph in accordance with the metadata (e.g. Bachmutsky: (0071) the work scheduler uses pointer in chain descriptor 502 to access global metadata 504 from memory. (0070) Global metadata 504 can indicate how accelerators should work on data and which phase of work has completed or is incomplete.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method/system of including a metadata object in memory as taught by Bachmutsky into the SIOV device and formatted task graphs of the combination of Marolia and Iorio because it decreases latency and increases processing efficiency by utilizing global metadata reducing the need to continuously stall and parse metadata for each task (See Bachmutsky: (0002)).
As per claim 18, Marolia discloses A scalable input/output virtualization (SIOV) device (e.g. Marolia: (0019) “multi-PASID” scalable IOV devices are provided. Please note the multi-PASID scalable IOV device corresponds to the Applicant’s SIOV device.), configured to [ ] receive a work descriptor from the host processor (e.g. Marolia: (0029) guest VM 316 prepares descriptor in descriptor queue 320 and submits it to virtual device (VDev) 330 in smart controller 306. smart controller 306 fetches the descriptor and prepares the corresponding descriptors for the helper device. Please note the descriptor corresponds to the Applicant’s work descriptor.).
Marolia does not disclose receive a data structure from a host processor communicatively coupled to the SIOV device, the data structure including tasks of a task graph having been arranged in an order by the host processor based on dependencies between the tasks; [ ] and process the tasks of the task graph in the order by accessing the data structure in the device memory based on the pointer [ ].
However, Iorio does disclose receive a data structure from a host processor communicatively coupled to the SIOV device e.g. Iorio: (Fig. 5A) (0038) the optimization engine 102 receives a task graph), the data structure including tasks of a task graph having been arranged in an order by the host processor based on dependencies between the tasks (e.g. Iorio: (Figs. 2A and 2B) (0022) When optimizing the task graph, the optimization engine 102 performs multiple iterations of runtime optimization operations on the task graph. At each iteration, an optimized task graph is generated based on a different task aggregation topology. Please note optimizing the task graph corresponds to the Applicant’s “arranged in an order”.); [ ] and process the tasks of the task graph in the order (e.g. Iorio: (0005) The task dependency graph indicates the dependency between each pair of tasks and the order in which tasks are to be executed. Please note the “to be executed” corresponds to the Applicant’s “process the tasks”, and “the order in which tasks are executed” corresponds to the Applicant’s “in the order”.) [ ].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method/system of the receiving and formatting of task graphs as taught by Iorio into -the “multi-PASID” scalable IOV device of Marolia to ensure more efficient processing of tasks and reduced overhead on a computing device (See Iorio: (0006) (0007) (0010)).
The combination of Marolia and Iorio does not disclose the work descriptor including a pointer to the data structure in the device memory; [ ] by accessing the data structure in the device memory based on the pointer.
However, Bachmutsky does disclose the work descriptor including a pointer to the data structure in the device memory (e.g. Bachmutsky: (0080) the work scheduler can access a pointer from work descriptor 602. At Action (2), the pointer can be used to access a UWD 604 from memory. UWD 604 can include an array of work commands[0]-[2]. Please note work descriptor corresponds to the Applicant’s work descriptor, the pointer corresponds to the Applicant’s pointer, and the array of work commands corresponds to the Applicant’s data structure.); [ ] by accessing the data structure in the device memory based on the pointer (e.g. Bachmutsky: (0080) the work scheduler can access a pointer from work descriptor 602. At Action (2), the pointer can be used to access a UWD 604 from memory. UWD 604 can include an array of work commands[0]-[2]. Please note the array of work commands corresponds to the Applicant’s data structure, and the pointer corresponds to the Applicant’s pointer.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method/system of -storing data in a memory on a SIOV device by Bachmutsky into the SIOV device and formatted task graphs of the combination of Marolia and Iorio because it helps reduce latency and processing speeds by reducing the need to access other computing devices or resources because the data is stored locally (See Bachmutsky: (0089) (0097) (0101)).
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Marolia and Iorio in view of Gurfinkel et al. (US 12443449 B2) (hereinafter Gurfinkel) in further view of Hosmani et al. (US 20180276040 A1) (hereinafter Hosmani).
As per claim 10, the combination of Marolia and Iorio discloses the system of claim 1 (See rejection to claim 1 above), but does not express disclose the operations further comprising: generating one or more additional tasks after the SIOV device has begun processing the tasks of the task graph, the one or more additional tasks having one or more formatting the one or more additional tasks based on the one or more dependencies; and dependencies on the tasks of the formatted task graph; submitting the one or more additional tasks for processing by the SIOV device.
However, Gurfinkel discloses the operations further comprising: generating one or more additional tasks (e.g. Gurfinkel: (Col. 62 Lines 60-61) at a step 3240, another task graph for another workload is built. Please note the “another workload” corresponds to the Applicant’s additional tasks.) after the SIOV device has begun processing the tasks of the task graph (e.g. Gurfinkel: (Col. 62 Lines 36-38) at a step 3230, an executable graph is launched one or more times to cause a workload to be performed. Please note the “executable graph is launched” corresponds to the Applicant’s begun processing the tasks.), and submitting the one or more additional tasks for processing by the SIOV device (e.g. Gurfinkel: (Col. 63 Lines 1-2) at a step 3250, another task graph is applied to executable graph.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method/system of -generating additional tasks for an already executed workload as taught by Gurfinkel into the SIOV device and formatted task graphs of the combination of Marolia and Iorio because it decreasing computing costs as it allows for multiple workloads to use the same task graph rather than building multiple task graphs (See Gurfinkel: (Col. 1 Lines 33-44) (Col. 63 Lines 2-14)).
The combination of Marolia, Iorio, and Gurfinkel does not disclose the one or more additional tasks having one or more dependencies on the tasks of the formatted task graph; formatting the one or more additional tasks based on the one or more dependencies.
However, Hosmani discloses the one or more additional tasks having one or more dependencies on the tasks of the formatted task graph (e.g. Hosmani: (0052) one or more later-submitted nodes that are dependent on the executed job. Please note the later-submitted node corresponds to the Applicant’s additional task.); formatting the one or more additional tasks based on the one or more dependencies (e.g. Hosmani: (0051) a new node that represents the new job may be added to the graph. One or more edges representing the dependency relationships may also be added to the graph. Please note the added edges corresponds the Applicant’s formatting.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method/system of -additional tasks being dependent on the formatted task graph as taught by Hosmani into the SIOV device and formatted task graph including later submitted tasks of the combination of Marolia, Iorio, and Gurfinkel because reduces latency and optimizes computing resources by allowing for higher utilization and dynamic load balancing without waiting for the CPU create a new task graph for the newly submitted tasks. (See Hosmani: (0014) (0019) (0051)).
As per claim 11, the combination of Marolia, Iorio, Gurfinkel, and Hosmani discloses the system of claim 10 (See rejection to claim 10 above), obtaining a list of completed tasks of the formatted task graph from the SIOV device (e.g. Hosmani: (0051) a relevant portion of the directed acyclic graph may be analyzed automatically and programmatically. Please note a relevant portion of the directed acyclic graph corresponds to the Applicant’s list of completed tasks. Please note that in order for the graph to be analyzed it must inherently be obtained first.); and inserting barriers (e.g. Kim: (Fig. 8) (0087) SCQ circuit 800 may set a wait task considering the dependency between tasks. Please note the wait task corresponds to the Applicant’s barrier.) in between the one or more additional tasks based (e.g. Gurfinkel: (Col. 62 Lines 60-61) at a step 3240, another task graph for another workload is built. Please note the “another workload” corresponds to the Applicant’s additional tasks.) tasks based on the one or more dependencies on uncompleted tasks of the formatted task graph that are absent from the list of completed tasks (e.g. Hosmani: (0051) a relevant portion of the directed acyclic graph may be analyzed automatically and programmatically. Please note a relevant portion of the directed acyclic graph corresponds to the Applicant’s list of completed tasks.).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iorio in view of Marolia.
As per claim 13, Iorio discloses a method, comprising: receiving, by a host processor, a task graph including tasks and indicating dependencies between the tasks (e.g. Iorio: (Fig. 5A) (0038) the optimization engine 102 receives a task graph for optimization from the application 304. a task aggregation topology indicates which tasks in the task graph are to be aggregated into a macro-task and which tasks are independent of one another. Please note the optimization engine corresponds to the Applicant’s host processor, and the task graph corresponds to the Applicant’s task graph.); sorting, by the host processor, the tasks of the task graph in an order based on the dependencies between the tasks (e.g. Iorio: (Figs. 2A and 2B) (0022) When optimizing the task graph, the optimization engine 102 performs multiple iterations of runtime optimization operations on the task graph. At each iteration, an optimized task graph is generated based on a different task aggregation topology. Please note optimizing the task graph corresponds to the Applicant’s sorting the tasks. ); generating, by the host processor, batch work descriptors each including a pointer to a task grouping stored in memory of the host processor (e.g. Iorio: (0023) Tasks that are included in the same macro-task are compiled by the runtime task aggregator into the same unit of work. Tasks that are within the same unit of work are called via a single function pointer. Please note the function pointer corresponds to the Applicant’s batch work descriptor and pointer.); [ ] based on the order, the batch work descriptors directing the SIOV device to fetch and process respective task groupings (e.g. Iorio: (0023) Tasks that are within the same unit of work are called via a single function pointer, easily share inputs and outputs and are scheduled for processing within a processing engine via a single scheduling operation.).
Iorio does not disclose and submitting, by the host processor, the batch work descriptors to a shared work queue of a scalable input/output virtualization (SIOV) device.
However, Marolia discloses and submitting, by the host processor, the batch work descriptors to a shared work queue of a scalable input/output virtualization (SIOV) device (e.g. Marolia: (0029) guest VM 316 prepares descriptor in descriptor queue 320 and submits it to virtual device (VDev) 330 in smart controller 306. Please note the descriptor queue corresponds to the Applicant’s shared work queue.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method/system of -the work descriptors as taught by Marolia into the receiving and formatting of task graphs of Iorio to ensure more efficient resource management and decreasing bandwidth by allowing the SIOV device to rely on minimal and lightweight descriptors. (See Marolia: (0023) (0024)).
Claim(s) 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Iorio and Marolia in view of Kim et al (US 20190179670 A1) (hereinafter Kim).
As per claim 14, the combination of Iorio and Marolia disclose the method of claim 13 (See rejection to claim 13 above), wherein sorting the tasks includes sorting the tasks of the task graph in the order using a topological sorting algorithm (e.g. Iorio: (0038) generates an initial task aggregation topology for the different tasks specified by the task graph. Please note the generates an initial aggregation topology corresponds to using a topological sorting algorithm. Please note the generates an initial aggregation topology corresponds to the Applicant’s sorting the tasks.)
The combination of Iorio and Marolia does not disclose based on one or more priority factors.
However, Kim discloses based on one or more priority factors (e.g. Kim: (0051) the control circuit 210 may determine a priority for the task based on a user's settings.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method/system of -including priority factors to tasks as taught by Kim into the SIOV device and formatted task graphs of the combination of Marolia and Iorio because it helps reduce bottlenecks and starvation of higher priority tasks that need to be processed also helping increase processing speeds (See Kim: (0051)).
As per claim 15, the combination of Iorio, Marolia, and Kim discloses the method of claim 13 (See rejection to claim 13 above), wherein generating the batch work descriptors (e.g. Iorio: (0023) Tasks that are included in the same macro-task are compiled by the runtime task aggregator into the same unit of work. Tasks that are within the same unit of work are called via a single function pointer. Please note the function pointer corresponds to the Applicant’s batch work descriptor and pointer.) includes inserting barriers in the respective task groupings based on the dependencies between the tasks in the respective task groupings (e.g. Kim: (0087) the SCQ circuit 800 may designate wait task1 832 for a queue storage device 822 (e.g., 314 in FIG. 3) so that the other tasks are not processed until the task corresponding to block 711 of FIG. 7 is processed. Please note the wait task corresponds to the Applicant’s barrier.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method/system of -inserting wait tasks as taught by Kim into the SIOV device and formatted task graphs of the combination of Marolia and Iorio because it helps avoid any runtime and dependency errors allowing for better resiliency in the system as the SIOV device enforces the dependencies strictly without constant synchronization calls back to the CPU (See Kim: (0006) (0053)).
As per claim 16, the combination of Iorio, Marolia, and Kim discloses the method of claim 13 (See rejection to claim 13 above), wherein a first task grouping includes a first set of tasks that are independent of one another (e.g. Kim: (Fig. 7) (0090) the other tasks are not processed until the tasks corresponding to blocks 741, 742, 743, and 744 are processed. Please note tasks corresponding to blocks 741, 742, 743, and 744 corresponds to the Applicant’s first task grouping.), and a second task grouping includes a second set of tasks having multiple dependencies on the first set of tasks of the first task grouping (e.g. Kim: (Fig. 7) (0086) tasks corresponding to block 751 and block 752 may have to be processed after the tasks corresponding to block 741, block 742, block 743, and block 744 are processed. Please note tasks correspond to block 751 and block 752 corresponds to a second task grouping.).
As per claim 17, the combination of Iorio, Marolia, and Kim discloses the method of claim 16 (See rejection to claim 16 above), wherein generating the batch work descriptors includes replacing the multiple dependencies with a single dependency between the first task grouping and the second task grouping (e.g. Kim: (Fig. 7) (0086) tasks corresponding to block 721 and block 722 may have to be processed after a task corresponding to block 711 is processed. (0087) an SCQ circuit 800 may set a wait task considering the dependency between tasks. Please note block 721 and block 722 corresponds to the Applicant’s multiple dependencies, the wait task corresponds to the Applicant’s single dependency, and the “set a wait task” corresponds to the Applicant’s “replacing” step. ), the single dependency represented by one barrier directing the SIOV device to stall until the first set of tasks have completed before processing the second set of tasks (e.g. Kim: (0088) the SCQ circuit 800 may designate wait task2 835 for the queue storage device 822 so that the other tasks are not processed until the tasks corresponding to blocks 721 and 722 of FIG. 7 are processed. Please note the wait task corresponds to the Applicant’s single dependency represented by one barrier.).
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Marolia, Iorio, and Bachmutsky in view of Kim et al. (US 2019/0179670 A1) (hereinafter Kim).
As per claim 19, the combination of Marolia, Iorio, and Bachmutsky discloses the SIOV device of claim 18 (See rejection to claim 18 above), but does not expressly disclose wherein the data structure is a priority queue in which the order is indicated by priorities assigned to the tasks, and to process the tasks, the SIOV device is configured to iteratively pop a task having a highest relative priority from the priority queue for processing.
However, Kim discloses wherein the data structure is a priority queue in which the order is indicated by priorities assigned to the tasks (e.g. Kim: (0051) the control circuit 210 may receive a request to process a fourth task having priority. The control circuit 210 may adjust a queue order so that the fourth task is processed prior to the first to third tasks. Please note the control circuit corresponds to the Applicant’s priority queue), and to process the tasks, the SIOV device is configured to iteratively pop a task having a highest relative priority from the priority queue for processing (e.g. Kim: (0051) the control circuit 210 may receive a request to process a fourth task having priority. The fourth task is processed prior to the first to third tasks.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method/system of -priority queue as taught by Kim into formatted task graphs of the combination of Marolia and Iorio to ensure more efficient processing by having fast insertion and enqueuing time complexities while avoiding starving high priority tasks (See Kim: (0006) (0051) (0054)).
As per claim 20, the SIOV device of claim 18 (See rejection to claim 18 above), the combination of Marolia, Iorio, and Bachmutsky. discloses further comprising a shared work queue (e.g. Kim: (0054) the control circuit 210 is defined as a shared command queue (SCQ) circuit. Please note the shared command queue corresponds to the shared work queue.), wherein to process the tasks, the SIOV device is configured to enqueue the work descriptor (e.g. Marolia: (0029) Second (2), smart controller 306 fetches the descriptor and prepares the corresponding descriptors for the helper device, as depicted by descriptor queue 328 in smart controller local memory 328. Please note the descriptor corresponds to the Applicant’s work descriptor.) in the shared work queue (e.g. Kim: (0054) the control circuit 210 is defined as a shared command queue (SCQ) circuit. Please note the shared command queue corresponds to the shared work queue.) and process the tasks of the task graph based on the work descriptor being encountered in (e.g. Bachmutsky: (0080) the work scheduler can access a pointer from work descriptor 602. At Action (2), the pointer can be used to access a UWD 604 from memory. UWD 604 can include an array of work commands[0]-[2]. Please note the array of work commands corresponds to the Applicant’s tasks of the task graph, and the work descriptor corresponds to the Applicant’s work descriptor.) the shared work queue (e.g. Kim: (0054) the control circuit 210 is defined as a shared command queue (SCQ) circuit. Please note the shared command queue corresponds to the shared work queue.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tovey et al. (US 20210373892 A1) discloses generating a task graph for execution (Abstract)
Narayanan (US 20070230491 A1) discloses queue descriptors having pointers to a queue (Abstract)
Coleman et al. (US 20100058120 A1) discloses metadata and descriptors for a workload (0078)
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/A.M.E./Examiner, Art Unit 2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
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