Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hourani US Patent Application (20210090990), hereinafter “Hourani”
Regarding claim 1 Hourani teaches an integrated circuit structure, the semiconductor structure or device 200 [Hourani para 0040] comprising: a plurality of gate structures above a substrate Referring to FIG. 5A, a starting structure includes a plurality of gate structures 302 (e.g., structures including a gate dielectric and gate electrode) over a substrate 300 (such as a silicon substrate or silicon fin protruding from a silicon substrate) [Hourani para 0062]; a plurality of conductive trench contact structures alternating with the plurality of gate structures A conductive trench contact structure 308 is between the dielectric sidewall spacers 304 of adjacent gate structures 302. [Hourani para 0062] and have an uppermost surface above an uppermost surface of gate electrodes of the plurality of gate structures An inter-layer dielectric (ILD) layer 310 is over the gate structures 302 and conductive trench contact structures 308. [Hourani para 0062] ; a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures Dielectric sidewall spacers 304 are along sides of the gate structures 302 [Hourani para 0062 and see Fig. 5a showing the dielectric 304 between the trenches 308 and the gates 302]; a dielectric-on-metal (DoM) layer on and confined to the uppermost surface of the conductive trench contact structures An inter-layer dielectric (ILD) layer 310 is over the gate structures 302 and conductive trench contact structures 308. [Hourani para 0062] Referring to FIG. 5C, a metal oxide layer 514 is selectively grown on … two adjacent trench contact structures 308 [Hourani para 0065] hardmask materials are composed of dielectric materials different from the interlayer dielectric material. … different hardmask materials may be used in different regions … to the underlying dielectric and metal layers [Hourani para 0089]; and a gate contact via on a gate electrode of one of the plurality of gate structures. The openings 312 expose portions of the plurality of gate structures 302 at locations where conductive gate contacts or vias are to make contact to an underlying gate structure 302. [Hourani para 0089]
Regarding claim 2 Hourani teaches claim 1 in addition Hourani teaches wherein the gate contact via is in contact with the DoM layer on a neighboring one of the plurality of conductive trench contact structures An inter-layer dielectric (ILD) layer 310 is over the gate structures 302 and conductive trench contact structures 308. [Houranio para 0062] but is electrically isolated from the one of the plurality of conductive trench contact structures. the intervening trench contact 810B may be isolated from the contact 880 by using an intervening metal oxide layer as described above [Hourani para 0080]
Regarding claim 3 Hourani teaches claim 1 in addition Hourani teaches further comprising: a trench contact via extending through the DoM layer on one of the plurality of conductive trench contact structures, the trench contact via in contact with the one of the plurality of conductive trench contact structures. Trench contact vias 112A and 112B provide contact to trench contacts 110A and 110B, respectively. A separate gate contact 114, and overlying gate contact via 116, provides contact to gate line 108B. In contrast to the source or drain trench contacts 110A or 110B, the gate contact 114 is disposed, from a plan view perspective, over isolation region 106, but not over diffusion or active region 104. Furthermore, neither the gate contact 114 nor gate contact via 116 is disposed between the source or drain trench contacts 110A and 110B. [Hourani para 0034]
Regarding claim 4 Hourani teaches claim 1 in addition Hourani teaches wherein the DoM layer comprises aluminum and oxygen. the metal oxide layer 514 is or includes hafnium oxide, zirconium oxide, titanium oxide, aluminum oxide, or the like [Hourani para 0085]
Regarding claim 5 Hourani teaches claim 1 in addition Hourani teaches wherein the DoM layer has a thickness in the range of 1-5 nm. One or more embodiments may be particularly useful for fabricating semiconductor devices at a 10 nanometer (10 nm) technology node sub-10 nanometer (10 nm) technology node. [Hourani para 0098]
At the time of the invention it would have been obvious to one skilled in the art to use the teachings of Hourani to design a thickness of a dielectric on metal layer between 1-5 nm in creating 10nm semiconductors
Regarding claim 6 Hourani teaches an integrated circuit structure, the semiconductor structure or device 200 [Hourani para 0040] comprising: a plurality of gate structures above a substrate Referring to FIG. 5A, a starting structure includes a plurality of gate structures 302 (e.g., structures including a gate dielectric and gate electrode) over a substrate 300 (such as a silicon substrate or silicon fin protruding from a silicon substrate) [Hourani para 0062]; a plurality of conductive trench contact structures alternating with the plurality of gate structures A conductive trench contact structure 308 is between the dielectric sidewall spacers 304 of adjacent gate structures 302. [Hourani para 0062] and have an uppermost surface below an uppermost surface of gate electrodes of the plurality of gate structures An inter-layer dielectric (ILD) layer 310 is over the gate structures 302 and conductive trench contact structures 308. [Hourani para 0062]; a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures Dielectric sidewall spacers 304 are along sides of the gate structures 302 [Hourani para 0062 and see Fig. 5a showing the dielectric 304 between the trenches 308 and the gates 302]; a dielectric-on-metal (DoM) layer on and confined to the uppermost surface of the gate electrodes of the plurality of gate structures An inter-layer dielectric (ILD) layer 310 is over the gate structures 302 and conductive trench contact structures 308. [Hourano para 0062] Referring to FIG. 5C, a metal oxide layer 514 is selectively grown on … two adjacent trench contact structures 308 [Hourani para 0065] hardmask materials are composed of dielectric materials different from the interlayer dielectric material. … different hardmask materials may be used in different regions … to the underlying dielectric and metal layers [Hourani para 0089]; and a trench contact via on one of the plurality of conductive trench contact structures. Trench contact vias 112A and 112B provide contact to trench contacts 110A and 110B, respectively. [Hourani para 0034]
Regarding claim 7 Hourani teaches claim 6 in addition Hourani teaches wherein the trench contact via is in contact with the DoM layer on a neighboring one of the gate electrodes An inter-layer dielectric (ILD) layer 310 is over the gate structures 302 and conductive trench contact structures 308. [Hourani para 0062] of the plurality of gate structures but is electrically isolated from the one of the gate electrodes of the plurality of gate structures. the intervening trench contact 810B may be isolated from the contact 880 by using an intervening metal oxide layer as described above [Hourani para 0080]
Regarding claim 8 Hourani teaches claim 6 in addition Hourani teaches further comprising: a gate contact via extending through the DoM layer on one of the gate electrodes of the plurality of gate structures, the gate contact via in contact with the one of the gate electrodes of the plurality of gate structures. Trench contact vias 112A and 112B provide contact to trench contacts 110A and 110B, respectively. A separate gate contact 114, and overlying gate contact via 116, provides contact to gate line 108B. In contrast to the source or drain trench contacts 110A or 110B, the gate contact 114 is disposed, from a plan view perspective, over isolation region 106, but not over diffusion or active region 104. Furthermore, neither the gate contact 114 nor gate contact via 116 is disposed between the source or drain trench contacts 110A and 110B. [Hourani para 0034]
Regarding claim 9 Hourani teaches claim 6 in addition Hourani teaches wherein the DoM layer comprises aluminum and oxygen. the metal oxide layer 514 is or includes hafnium oxide, zirconium oxide, titanium oxide, aluminum oxide, or the like [Hourani para 0085]
Regarding claim 10 Hourani teaches claim 6 in addition Hourani teaches wherein the DoM layer has a thickness in the range of 1-5 nm. One or more embodiments may be particularly useful for fabricating semiconductor devices at a 10 nanometer (10 nm) technology node sub-10 nanometer (10 nm) technology node. [Hourani para 0098]
At the time of the invention it would have been obvious to one skilled in the art to use the teachings of Hourani to design a thickness of a dielectric on metal layer between 1-5 nm in creating 10nm semiconductors
Regarding claim 11 Hourani teaches computing device, comprising: a board; and a component coupled to the board, The board 902 may include a number of components, including but not limited to a processor 904 and at least one communication chip 906. [Hourani para 0101] the component including an integrated circuit structure, the chipset, may potentially be manufactured using the approaches disclosed herein. [Hourani para 0100] comprising: a plurality of gate structures above a substrate Referring to FIG. 5A, a starting structure includes a plurality of gate structures 302 (e.g., structures including a gate dielectric and gate electrode) over a substrate 300 (such as a silicon substrate or silicon fin protruding from a silicon substrate) [Hourani para 0062]; a plurality of conductive trench contact structures alternating with the plurality of gate structures A conductive trench contact structure 308 is between the dielectric sidewall spacers 304 of adjacent gate structures 302. [Hourani para 0062] and have an uppermost surface above an uppermost surface of gate electrodes of the plurality of gate structures An inter-layer dielectric (ILD) layer 310 is over the gate structures 302 and conductive trench contact structures 308. [Hourani para 0062] a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures Dielectric sidewall spacers 304 are along sides of the gate structures 302 [Hourani para 0062 and see Fig. 5a showing the dielectric 304 between the trenches 308 and the gates 302]; a dielectric-on-metal (DoM) layer on and confined to the uppermost surface of the conductive trench contact structures An inter-layer dielectric (ILD) layer 310 is over the gate structures 302 and conductive trench contact structures 308. [Hourani para 0062] Referring to FIG. 5C, a metal oxide layer 514 is selectively grown on … two adjacent trench contact structures 308 [Hourani para 0065] hardmask materials are composed of dielectric materials different from the interlayer dielectric material. … different hardmask materials may be used in different regions … to the underlying dielectric and metal layers [Hourani para 0089]; and a gate contact via on a gate electrode of one of the plurality of gate structures. The openings 312 expose portions of the plurality of gate structures 302 at locations where conductive gate contacts or vias are to make contact to an underlying gate structure 302. [Hourani para 0089]
Regarding claim 12 Hourani teaches claim 11 in addition Hourani teaches further comprising: a memory coupled to the board. a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein. [Hourani para 0100] computing device 900 may include other components that may or may not be physically and electrically coupled to the board 902. [Hourani para 0102]
Regarding claim 13 Hourani teaches claim 11 in addition Hourani teaches further comprising: a communication chip coupled to the board. The board 902 may include a number of components, including but not limited to a processor 904 and at least one communication chip 906. [Hourani para 0101]
Regarding claim 14 Hourani teaches claim 11 in addition Hourani teaches further comprising: a camera coupled to the board. These other components include, but are not limited to, …. a battery, …[Hourani para 0102]
Regarding claim 15 Hourani teaches claim 11 in addition Hourani teaches further comprising: a battery coupled to the board. These other components include, but are not limited to, …. a camera …[Hourani para 0102]
Regarding claim 16 Hourani teaches claim 11 in addition Hourani teaches further comprising: a display coupled to the board. These other components include, but are not limited to, …. a display…[Hourani para 0102]
Regarding claim 17 Hourani teaches claim 11 in addition Hourani teaches further comprising: a speaker coupled to the board. These other components include, but are not limited to, …. a speaker…[Hourani para 0102]
Regarding claim 18 Hourani teaches claim 11 in addition Hourani teaches further comprising: a compass coupled to the board. These other components include, but are not limited to, …. a compass, …[Hourani para 0102]
Regarding claim 19 Hourani teaches claim 11 in addition Hourani teaches further comprising: a GPS coupled to the board. These other components include, but are not limited to, …. a global positioning system (GPS) device, …[Hourani para 0102]
Regarding claim 20 Hourani teaches claim 11 in addition Hourani teaches wherein the component is a packaged integrated circuit die. the processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. In some implementations of embodiments of the disclosure, the integrated circuit die of the processor 904 includes one or more structures, such as integrated circuit structures built in accordance with implementations of the disclosure. [Hourani para 0102]
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT J MICHAUD whose telephone number is (571)270-3981. The examiner can normally be reached 8:30 - 5:00.
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/ROBERT J MICHAUD/Examiner, Art Unit 2622