DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This non-final office action is responsive to Applicants' application filed on 09/29/23. Claims 1-20 are presented for examination and are pending for the reasons indicated herein below.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claim 1 objected to because of the following informalities: change “a current” to “a first current”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5-6, 18 rejected under 35 U.S.C. 102(a)(1) as being anticipated by D'Souza et al. (US 20220352818 A1 and hereinafter as Sou)
Regarding claim 1. Sou teaches an apparatus [fig 2, coupled is interpreted as connected between intervening elements] comprising: a low-dropout (LDO) voltage node [vout];
a driver [240] including an output node [i.e. vout] coupled to the LDO voltage node to provide a current [i.e. Iout] at the LDO voltage node;
a comparator [210] including an input node [Vfb] coupled to the output node of the driver, and an output node [213] coupled to an input node [gate of driver] of the driver;
a current generator [see 236] coupled to the driver to generate a second current based on the first current;
and a frequency compensation network [280 w/ 220] coupled to the comparator and the current generator [¶32].
Regarding claim 5. Sou teaches the apparatus of claim 1, wherein the comparator includes: a differential amplifier [i.e. 210] including an input node coupled to the output node of the driver, and an output node coupled to the frequency compensation network [see claim 1];
and a buffer [230] including an input node coupled to the output node of the differential amplifier, and an output node coupled to the input node of the driver.
Regarding claim 6. The apparatus of claim 5, wherein the frequency compensation network includes: a capacitor [250] including a first plate coupled to the input node of the driver;
and a transistor [350] including a first terminal coupled to a second plate of the capacitor, and a second terminal coupled to the input node of the buffer.
Regarding claim 18. Sou teaches a method [method by fig 2] comprising: generating a signal at an output node of a low-dropout (LDO) voltage regulator [see vout];
controlling the signal at the output node based on a feedback loop [see 210 Vfb] coupled to the output node; providing a first current [current to vout] at the output node;
generating a second current based on the first current [current in 260];
and controlling the signal at the output node based on the second current [function of 210, ¶27-¶30].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 8-13, 15 rejected under 35 U.S.C. 103 as being unpatentable over D'Souza et al. (US 20220352818 A1 and hereinafter as Sou) in view of Mandal et al. (US 9256233 B2)
Regarding claim 2. Sou teaches the apparatus of claim 1, wherein the current generator includes a current mirror circuit [232 w/ 233], the current mirror circuit includes a first branch [branch of 232] to conduct the second current, and a second branch [branch of 233] coupled to the first branch.
However, Sou does not explicitly mention a circuit wherein the frequency compensation network includes a capacitor coupled to the second branch and the output node of the comparator.
Mandal teaches a circuit wherein the frequency compensation network includes a capacitor [CM] coupled to the second branch and the output node of the comparator.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Mandal in order to provide a better control of the mosfet gate by a faster transient response, yielding a more efficient circuit.
Regarding claim 3. Sou as modified teaches the apparatus of claim 2, wherein: the driver includes a first transistor [Sou 240] including a first terminal coupled to a supply node, a second terminal coupled to the LDO voltage node;
and the current generator includes a second transistor [Sou 232] including a gate coupled to a gate of the first transistor, and a terminal coupled to the LDO voltage node.
Regarding claim 4. Sou as modified teaches the apparatus of claim 3, wherein the frequency compensation network includes an additional capacitor [Mandal C1] coupled to the output node of the comparator.
Regarding claim 8. Sou teaches an apparatus [fig 2, coupled is interpreted as connected between intervening elements] comprising: a voltage regulator [see fig 2] including a transistor [240], the transistor including a first terminal coupled to a supply node [201] and a second terminal coupled to an output node [see 245] of the voltage regulator;
and a voltage sensor [210 w/ 260/270] including a comparator, the comparator including a first input node coupled to the output node and a second input node coupled to a reference voltage generator [see 211 and 271].
However, Sou does not explicitly mention a circuit comprising: measurement circuitry to measure a first current based on a second current between the supply node and the output node.
Mandal teaches a circuit comprising: measurement circuitry [M5] to measure a first current [i.e. Ifb] based on a second current [Iout] between the supply node and the output node.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Mandal in order to provide additional stability, transient protection.
Regarding claim 9. Sou as modified teaches the apparatus of claim 8, wherein the transistor is a first transistor [i.e. 240 Sou], and wherein: the voltage regulator includes a second transistor [220 Sou], the second transistor including a gate coupled to a gate of the first transistor, and a terminal coupled to the output node of the voltage regulator;
and the measurement circuitry includes a third transistor [i.e. M5 Mandal], the third transistor including a gate coupled to a gate of the first transistor, and a terminal coupled to the output node of the voltage regulator.
Regarding claim 10. Sou as modified teaches the apparatus of claim 8, wherein the transistor is a first transistor [Sou 240], and wherein: the voltage regulator includes a second transistor [220 Sou], the second transistor including a gate coupled to a gate of the first transistor, and a terminal coupled to the supply node;
the measurement circuitry includes a third transistor [M5 Mandal];
and the third transistor including a gate coupled to a gate of the first transistor, and a terminal coupled to the supply node [components included in M5].
Regarding claim 11. Sou as modified teaches the apparatus of claim 8, wherein the voltage regulator includes a current mirror circuit [232/233 Sou] coupled to the transistor.
Regarding claim 12. Sou as modified teaches the apparatus of claim 11, wherein the voltage regulator includes a capacitor [Mandal CM] coupled to the current mirror circuit.
Regarding claim 13. Sou as modified teaches the apparatus of claim 8, wherein the voltage regulator includes: a differential amplifier [210 Sou] including an input node coupled to the output node of the voltage regulator [see terminals of 210 Sou];
and a buffer [230 Sou] including an input node coupled to an output node of the differential amplifier, and an output node coupled to a gate of the transistor.
Regarding claim 15. Sou as modified teaches the apparatus of claim 8, wherein the voltage regulator includes circuit paths [see path 202 and 245 Sou] coupled in parallel between an additional supply node and the output node of the voltage regulator.
Claims 14, 16 rejected under 35 U.S.C. 103 as being unpatentable over D'Souza et al. (US 20220352818 A1 and hereinafter as Sou) in view of Mandal et al. (US 9256233 B2) and further in view of Cook et al. (US 20090243571 A1)
Regarding claim 14. Sou as modified teaches the apparatus of claim 8.
However, Sou as modified does not explicitly mention a circuit wherein the voltage sensor includes a counter coupled to an output node of the comparator.
Cook teaches a circuit wherein the voltage sensor includes a counter coupled to an output node of the comparator [39 of fig 2].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Huang in order to provide a track of how often the control loops work, enabling smarter adaptive biasing and early detection.
Regarding claim 16. Sou as modified teaches the apparatus of claim 8.
However, Sou as modified does not explicitly mention a circuit wherein the measurement circuitry includes a circuit to provide digital information based on measurement of the first current.
Cook teaches a circuit wherein the measurement circuitry includes a circuit to provide digital information [counter provides digital code, ¶23] based on measurement of the first current [current going through 37].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Huang in order to provide a track of how often the control loops work, enabling smarter adaptive biasing and early detection.
Claim 7 rejected under 35 U.S.C. 103 as being unpatentable over D'Souza et al. (US 20220352818 A1 and hereinafter as Sou) in view of Schenkel (5841643)
Regarding claim 7. Sou teaches the apparatus of claim 1, however, wherein the apparatus comprises a system on chip (SoC), the SoC including an integrated circuit (IC) die, and wherein the driver, the comparator, the current generator, and the frequency compensation network are included in the IC die.
Schenkel teaches a circuit wherein the apparatus comprises a system on chip (SoC), the SoC including an integrated circuit (IC) die, and wherein the driver, the comparator, the current generator, and the frequency compensation network are included in the IC die [col 1 lines 10-25].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Schenkel in order to assemble components as an integrated circuit components, which advantageously reduces the size and complexity of the overall switching regulator circuit [col 1 lines 10-25].
Claim 17 rejected under 35 U.S.C. 103 as being unpatentable over D'Souza et al. (US 20220352818 A1 and hereinafter as Sou) in view of Mandal et al. (US 9256233 B2) and further in view of Schenkel (5841643)
Regarding claim 17. Sou as modified teaches the apparatus of claim 8.
However, Sou as modified does not explicitly mention a circuit wherein the apparatus comprises a system in a package (SiP), the SiP including an integrated circuit (IC) die, and wherein the driver is included in the IC die.
Schenkel teaches a circuit wherein the apparatus comprises a system in a package (SiP), the SiP including an integrated circuit (IC) die, and wherein the driver is included in the IC die [col 1 lines 10-25].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Schenkel in order to assemble components as an integrated circuit components, which advantageously reduces the size and complexity of the overall switching regulator circuit [col 1 lines 10-25].
Claims 19-20 rejected under 35 U.S.C. 103 as being unpatentable over D'Souza et al. (US 20220352818 A1 and hereinafter as Sou) in view of Cook et al. (US 20090243571 A1)
Regarding claim 19. Sou teaches the method of claim 18.
However, Sou does not explicitly mention a method further comprising: providing code information to a circuit coupled between the output node and a supply node; and controlling the signal at the output node based on the code information.
Cook teaches a method further comprising: providing code information [i.e. 39, ¶23] to a circuit coupled between the output node and a supply node [i.e. fig 2 supply to 36]; and controlling the signal at the output node based on the code information [function 34 w/ 39, ¶23].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Huang in order to provide a track of how often the control loops work, enabling smarter adaptive biasing and early detection.
Regarding claim 20. Sou teaches the method of claim 18, further comprising: generating a third current based on the first current; and generating digital information based on the third current.
Cook teaches a method further comprising: generating a third current [current through 37] based on the first current; and generating digital information based on the third current.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Huang in order to provide a track of how often the control loops work, enabling smarter adaptive biasing and early detection.
Examiner Note
The examiner cites particular columns and lines numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bryan Perez whose telephone number is (571)272-8837. The examiner can normally be reached on Mon.-Fri. (7:30 – 5:00).
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Crystal Hammond, can be reached on (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R PEREZ/Examiner, Art Unit 2838
