DETAILED ACTION
The instant application having Application No. 18/374837 filed on 09/29/2023 is presented for examination by the examiner.
Claim 1-20 is/are pending in the application.
Claims 1, 8 and 20 is/are independent claims.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Information Disclosure Statement
As required by M.P.E.P. 609, the applicant’s submissions of the Information Disclosure Statement dated 10/24/2025 and 08/20/2024 are acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 8-9 and 11-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
Regarding claim 8, the claim calls for a processing device; however, there is no hardware element found within the claimed system. As recited in the body of the claim, the claimed processing device contains “a hardware scheduler”, and “queue unit” The specification does not explicitly define how “a hardware scheduler”, and “queue unit” are implemented. One of ordinary skill in the art would understand that “a hardware scheduler”, and “queue unit” could be implemented in software, which is non-statutory subject matter. It is suggested that the claim be further amended to positively recite at least one hardware embodiment in the body of the claim to make the claim statutory under 35. U.S.C. 101.
Regarding claims 2-9 and 11-19; Claims 2-9 and 11-19 are also rejected under 35 U.S.C 101 as being directed to non-statutory subject matter for the same reasons.
Regarding claim 20, the claim calls for a processing device; however, there is no hardware element found within the claimed system. As recited in the body of the claim, the claimed processing device contains “a hardware scheduler”, a mapping data structure”, and “queue unit”. The specification does not explicitly define how “a hardware scheduler”, a mapping data structure”, and “queue unit” are implemented. One of ordinary skill in the art would understand that “a hardware scheduler”, a mapping data structure”, and “queue unit” could be implemented in software, which is non-statutory subject matter. It is suggested that the claim be further amended to positively recite at least one hardware embodiment in the body of the claim to make the claim statutory under 35. U.S.C. 101.
Allowable Subject Matter
Claims 6-7 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 is allowed.
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
Prior art:
US 2021/0303344 to Li
In some embodiments, control device 110 determines whether an unscheduled historical task exists in the task processing system and creates the current to-be-scheduled task queue according to a determination that no to-be-scheduled historical task exists.
US 2021/0034526 to Pope
A doorbell may typically be generated by a host CPU executing load/store like instructions to a destination address which is mapped to cause target bus writes to be issued. The bus mapping attributes (e.g. write combining) and the particular instructions used (e.g. write memory barrier) influence the bus transactions generated.
US 2017/0075834 to Cha
the host interface 212 may include a first doorbell register 213 for writing a tail pointer doorbell of the submission queue 123 of the host 100. The host interface 212 may further include a second doorbell register 214 at which the host 100 writes that a head pointer HP of the completion queue 125 is updated and an update position. In addition, the host interface 212 may further include an interrupt table 215 for managing interrupts to be generated according to a status of the second doorbell register 214.
US 2016/0065659 to Bloch
In alternative embodiments of the WAIT request, the CC may queue it in any WQ and condition it on any other WQ. In an embodiment, CC 152 polls the other WQ, or any other suitable indication, for verifying whether the wait condition has been met. In alternative embodiments, the indication may actively notify the CC when an awaited condition is met, by an interrupt, doorbell or any other suitable mechanism.
US 2006/0075119 to Hussain
Data is transferred to the buffer addresses supplied by the host driver in a descriptor (info/buffer pointer) queue implemented using a ring buffer. Each entry in the ring is an info/buffer pointer pair as shown in FIG. 6. Through the use of PCI instruction, the host driver rings a --doorbell" to indicate space availability in a ring to the network services processor.
The prior art of record does not disclose and/or fairly suggest at least claimed limitations recited in such manners in dependent claims 6-7 and 17-19.
The prior art of record does not disclose and/or fairly suggest at least claimed limitations recited in such manners in independent claim 20 "... detect an unmapped queue doorbell associated with a queue currently unmapped to a hardware queue of the processing device; responsive to the detected unmapped queue doorbell, update at least one bit mapped to the unmapped queue doorbell in a register array of the plurality of register arrays; and send a signal indicating to the hardware scheduler to process the mapping data structure, wherein the hardware scheduler is configured to: responsive to the signal, determine the queue has work based on the updated at least one bit …”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, and 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0191730 to Mccrary and in further view of US 2013/0060981 to Horn et al. (hereafter “Horn”)
As per claim 1, Mccrary discloses a method implemented at a processing device, the method comprising:
responsive to a queue doorbell being an unmapped queue doorbell (FIGs. 2; paragraphs 0019-0025: “The scheduling system 200 also includes an unmapped queue list 255 that indicates the queues 214-220 that are not mapped (e.g., on a one-to-one basis) to individual doorbells and are instead collectively associated with one of the aggregate doorbells 229, 230. In some embodiments, queues are added to or removed from the mapped queue list 250 and the unmapped queue list 255 by modifying an associated index that indicates either the mapped queue list 250 or the unmapped queue list 255. The scheduler 205 uses the mapped queue list 250 to determine which doorbells to monitor. Some embodiments of the scheduler 205 move queues from the mapped queue list 250 to the unmapped queue list 255 in response to the queues becoming empty, e.g., by modifying a value of an associated index.” And “At block 320, a scheduler detects the interrupt and, in response, polls the unmapped queues associated with the aggregated doorbell that was written. For example, if several unmapped queues are associated with the aggregated doorbell, the scheduler polls each of the several unmapped queues to determine which of the unmapped queues received the command buffer. Polling the unmapped queues includes clearing the aggregate doorbell, making a pass through the unmapped queues to identify the unmapped queue that receives the command buffer, popping the command buffer from the unmapped queue, and then making another pass through the unmapped queues to detect any unmapped queues that have been written since the aggregate doorbell was cleared.”[Wingdings font/0xE0] aggregate queue doorbell associating with unmapped queue [Wingdings font/0xE0] aggregate doorbell (unmapped doorbell as claimed), signaling a hardware scheduler (FIGs. 1-2: scheduler 155/205 in a GPU) of the processing device indicating work has been placed into a command buffer (FIGs. 1-2; in view of paragraph 0028 of the specification [Wingdings font/0xE0] commands/works are in command buffers which are queues [Wingdings font/0xE0] Mccrary (paragraphs 0001, 0018, 0021 and 0025) [Wingdings font/0xE0] commands are placed in command buffers) currently unmapped to a hardware queue of the processing device (FIGs. 2; paragraphs 0019-0025: “Polling the unmapped queues includes clearing the aggregate doorbell, making a pass through the unmapped queues to identify the unmapped queue that receives the command buffer, popping the command buffer from the unmapped queue, and then making another pass through the unmapped queues to detect any unmapped queues that have been written since the aggregate doorbell was cleared. If an unmapped queue has been written, the aggregate doorbell is written and the method 300 is repeated for the newly written aggregate doorbell. At block 325, the scheduler schedules the command buffer from the non-empty queue or adds the command buffer to a pool of command buffers that are available for scheduling.” [Wingdings font/0xE0] the command buffers are added/mapped into empty queue which is not one-to-one queue/mapped queue [Wingdings font/0xE0] the command buffers are not mapped to the one-to-one/mapped queue).
Mccrary discloses work has been placed into a command buffer, however, Mccrary does not explicitly disclose the command buffer is a queue.
Horn further discloses the command buffer is a queue (paragraph 0047: “The admin queue 258 may be implemented in a fashion that is similar to the command queue, such as through full hardware automation or ring buffer.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Horn into Mccrary’s teaching because it would provide for the purpose of the controller may also have several queues to enable the bridge to return information related to data commands (completion, error, etc.). In addition, the bridge can report other status, errors, and indicate non-critical information (i.e., info/health reports) related to the operation of the bridge and the NVM (Horn, paragraph 0056).
As per claim 2, Mccrary discloses responsive to the signaling, mapping, by the hardware scheduler (FIGs. 1-2; in view of paragraph 0028 of the specification [Wingdings font/0xE0] commands/works are in command buffers which are queues [Wingdings font/0xE0] Mccrary (paragraphs 0001, 0018, 0021 and 0025) [Wingdings font/0xE0] command buffers added in the empty queues are scheduled to be executed or add in the pool for a next scheduling [Wingdings font/0xE0] adding the command buffers to queues 210-213 which is mapped as one-to-one for execution), the command buffers/queue to a hardware queue of a plurality of hardware queues at the processing device (FIGs. 1-2; in view of paragraph 0028 of the specification [Wingdings font/0xE0] commands/works are in command buffers which are queues [Wingdings font/0xE0] Mccrary (paragraphs 0001, 0018, 0021 and 0025) [Wingdings font/0xE0] command buffers added in the empty queues are scheduled to be executed or add in the pool for a next scheduling [Wingdings font/0xE0] adding the command buffers to queues 210-213 which is mapped as one-to-one (pipeline) for execution).
Mccrary discloses work has been placed into a command buffer, however, Mccrary does not explicitly disclose the command buffer is a queue.
Horn further discloses the command buffer is a queue (paragraph 0047: “The admin queue 258 may be implemented in a fashion that is similar to the command queue, such as through full hardware automation or ring buffer.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Horn into Mccrary’s teaching because it would provide for the purpose of the controller may also have several queues to enable the bridge to return information related to data commands (completion, error, etc.). In addition, the bridge can report other status, errors, and indicate non-critical information (i.e., info/health reports) related to the operation of the bridge and the NVM (Horn, paragraph 0056).
As per claim 8, Mccrary discloses a processing device comprising:
a hardware scheduler (FIGs. 1-2: scheduler 155/205 in a GPU); and
an unmapped queue unit configured to:
responsive to a queue doorbell being an unmapped queue doorbell (FIGs. 2; paragraphs 0019-0025: “The scheduling system 200 also includes an unmapped queue list 255 that indicates the queues 214-220 that are not mapped (e.g., on a one-to-one basis) to individual doorbells and are instead collectively associated with one of the aggregate doorbells 229, 230. In some embodiments, queues are added to or removed from the mapped queue list 250 and the unmapped queue list 255 by modifying an associated index that indicates either the mapped queue list 250 or the unmapped queue list 255. The scheduler 205 uses the mapped queue list 250 to determine which doorbells to monitor. Some embodiments of the scheduler 205 move queues from the mapped queue list 250 to the unmapped queue list 255 in response to the queues becoming empty, e.g., by modifying a value of an associated index.” And “At block 320, a scheduler detects the interrupt and, in response, polls the unmapped queues associated with the aggregated doorbell that was written. For example, if several unmapped queues are associated with the aggregated doorbell, the scheduler polls each of the several unmapped queues to determine which of the unmapped queues received the command buffer. Polling the unmapped queues includes clearing the aggregate doorbell, making a pass through the unmapped queues to identify the unmapped queue that receives the command buffer, popping the command buffer from the unmapped queue, and then making another pass through the unmapped queues to detect any unmapped queues that have been written since the aggregate doorbell was cleared.”[Wingdings font/0xE0] aggregate queue doorbell associating with unmapped queue [Wingdings font/0xE0] aggregate doorbell (unmapped doorbell as claimed), transmit a signal to the hardware scheduler indicating work has been placed into a command buffer (FIGs. 1-2; in view of paragraph 0028 of the specification [Wingdings font/0xE0] commands/works are in command buffers which are queues [Wingdings font/0xE0] Mccrary (paragraphs 0001, 0018, 0021 and 0025) [Wingdings font/0xE0] commands are placed in command buffers) currently unmapped to a hardware queue of the processing device (FIGs. 2; paragraphs 0019-0025: “Polling the unmapped queues includes clearing the aggregate doorbell, making a pass through the unmapped queues to identify the unmapped queue that receives the command buffer, popping the command buffer from the unmapped queue, and then making another pass through the unmapped queues to detect any unmapped queues that have been written since the aggregate doorbell was cleared. If an unmapped queue has been written, the aggregate doorbell is written and the method 300 is repeated for the newly written aggregate doorbell. At block 325, the scheduler schedules the command buffer from the non-empty queue or adds the command buffer to a pool of command buffers that are available for scheduling.” [Wingdings font/0xE0] the command buffers are added/mapped into empty queue which is not one-to-one queue/mapped queue [Wingdings font/0xE0] the command buffers are not mapped to the one-to-one/mapped queue).
Mccrary discloses work has been placed into a command buffer, however, Mccrary does not explicitly disclose the command buffer is a queue.
Horn further discloses the command buffer is a queue (paragraph 0047: “The admin queue 258 may be implemented in a fashion that is similar to the command queue, such as through full hardware automation or ring buffer.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Horn into Mccrary’s teaching because it would provide for the purpose of the controller may also have several queues to enable the bridge to return information related to data commands (completion, error, etc.). In addition, the bridge can report other status, errors, and indicate non-critical information (i.e., info/health reports) related to the operation of the bridge and the NVM (Horn, paragraph 0056).
As per claim 9, it is processing device claim, which recite(s) the same limitations as those of claim 2. Accordingly, claim 9 is rejected for the same reasons as set forth in the rejection of claim 2.
As per claim 10, Mccrary discloses a plurality of compute units (FIGs. 1-2); and
a command processor configured to, responsive to the hardware scheduler mapping the command buffer to the hardware queue (FIGs. 1-2; paragraphs 0019-0021 and 0024-0026: command buffers are in queues 145-147), dispatch the work to one or more compute units of the plurality of compute units (FIGs. 1-2; paragraphs 0019-0021 and 0024-0026: sending command buffers to pipelines 141-143).
Mccrary discloses work has been placed into a command buffer, however, Mccrary does not explicitly disclose the command buffer is a queue.
Horn further discloses the command buffer is a queue (paragraph 0047: “The admin queue 258 may be implemented in a fashion that is similar to the command queue, such as through full hardware automation or ring buffer.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Horn into Mccrary’s teaching because it would provide for the purpose of the controller may also have several queues to enable the bridge to return information related to data commands (completion, error, etc.). In addition, the bridge can report other status, errors, and indicate non-critical information (i.e., info/health reports) related to the operation of the bridge and the NVM (Horn, paragraph 0056).
As per claim 11, Mccrary discloses wherein the unmapped queue doorbell is generated (paragraphs 0001, 0009 and 0011: aggregated doorbells) in response to a device driver placing work in the command buffer (paragraph 0001).
Mccrary discloses work has been placed into a command buffer, however, Mccrary does not explicitly disclose the command buffer is a queue.
Horn further discloses the command buffer is a queue (paragraph 0047: “The admin queue 258 may be implemented in a fashion that is similar to the command queue, such as through full hardware automation or ring buffer.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Horn into Mccrary’s teaching because it would provide for the purpose of the controller may also have several queues to enable the bridge to return information related to data commands (completion, error, etc.). In addition, the bridge can report other status, errors, and indicate non-critical information (i.e., info/health reports) related to the operation of the bridge and the NVM (Horn, paragraph 0056).
As per claim 12, Mccrary discloses wherein the unmapped queue doorbell is generated by writing to a doorbell register mapped to the command buffers (FIGs. 1-2; paragraphs 0019-0021 and 0024-0026: the command buffers added into the 214-220 associated with doorbells 240).
Mccrary discloses work has been placed into a command buffer, however, Mccrary does not explicitly disclose the command buffer is a queue.
Horn further discloses the command buffer is a queue (paragraph 0047: “The admin queue 258 may be implemented in a fashion that is similar to the command queue, such as through full hardware automation or ring buffer.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Horn into Mccrary’s teaching because it would provide for the purpose of the controller may also have several queues to enable the bridge to return information related to data commands (completion, error, etc.). In addition, the bridge can report other status, errors, and indicate non-critical information (i.e., info/health reports) related to the operation of the bridge and the NVM (Horn, paragraph 0056).
As per claim 13, Mccrary discloses responsive to a hardware queue mapping list indicating the queue is an unmapped queue (FIGs. 2; paragraphs 0020-0022 and 0025-0027), determine the queue doorbell is an unmapped queue doorbell (FIGs. 2; paragraphs 0020-0022 and 0025-0027).
Claims 4-5 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Mccrary in view of Horn, as applied to claims 1 and 8, and further in view of US 2008/0198671 to Wang et al. (hereafter Wang)
As per claim 4, Mccrary discloses responsive to the unmapped queue doorbell (FIGs. 2; paragraphs 0019-0025: “The scheduling system 200 also includes an unmapped queue list 255 that indicates the queues 214-220 that are not mapped (e.g., on a one-to-one basis) to individual doorbells and are instead collectively associated with one of the aggregate doorbells 229, 230. In some embodiments, queues are added to or removed from the mapped queue list 250 and the unmapped queue list 255 by modifying an associated index that indicates either the mapped queue list 250 or the unmapped queue list 255. The scheduler 205 uses the mapped queue list 250 to determine which doorbells to monitor. Some embodiments of the scheduler 205 move queues from the mapped queue list 250 to the unmapped queue list 255 in response to the queues becoming empty, e.g., by modifying a value of an associated index.” And “At block 320, a scheduler detects the interrupt and, in response, polls the unmapped queues associated with the aggregated doorbell that was written. For example, if several unmapped queues are associated with the aggregated doorbell, the scheduler polls each of the several unmapped queues to determine which of the unmapped queues received the command buffer. Polling the unmapped queues includes clearing the aggregate doorbell, making a pass through the unmapped queues to identify the unmapped queue that receives the command buffer, popping the command buffer from the unmapped queue, and then making another pass through the unmapped queues to detect any unmapped queues that have been written since the aggregate doorbell was cleared.”[Wingdings font/0xE0] aggregate queue doorbell associating with unmapped queue [Wingdings font/0xE0] aggregate doorbell (unmapped doorbell as claimed), the mapping data structure mapping each command buffer of a plurality of command buffers to a doorbell register of a plurality of doorbell registers at the processing device (FIGs. 1-2; in view of paragraph 0028 of the specification [Wingdings font/0xE0] commands/works are in command buffers which are queues [Wingdings font/0xE0] Mccrary (paragraphs 0001, 0018, 0021 and 0024-0026) [Wingdings font/0xE0] command buffers added in the empty queues are scheduled to be executed or add in the pool for a next scheduling [Wingdings font/0xE0] adding the command buffers to queues 210-213 which is mapped as one-to-one (pipeline) for execution).
Mccrary discloses work has been placed into a command buffer, however, Mccrary does not explicitly disclose the command buffer is a queue.
Horn further discloses the command buffer is a queue (paragraph 0047: “The admin queue 258 may be implemented in a fashion that is similar to the command queue, such as through full hardware automation or ring buffer.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Horn into Mccrary’s teaching because it would provide for the purpose of the controller may also have several queues to enable the bridge to return information related to data commands (completion, error, etc.). In addition, the bridge can report other status, errors, and indicate non-critical information (i.e., info/health reports) related to the operation of the bridge and the NVM (Horn, paragraph 0056).
Wang further discloses updating a mapping data structure (paragraphs 0023-0024: “ The write control logic 14 may select the write pointer corresponding to the command type (and potentially port) to provide to the command queue 10, and may update the selected pointer (e.g. increment). Alternatively, the write control logic 14 may provide all of the write pointers to the command queue 10, which may write the command into the correct location. The write control logic 14 may receive the command type and port number for the command, and may update the corresponding pointer) to indicate the queue has work (paragraphs 0023-0024: : “The enqueue event FIFO 16 passes a write event, indicating that a command has been enqueued in the command buffer 10, over the clock boundary to inform the read control logic 12 of the event so that it may update the corresponding write pointer.”)
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Wang into Mccrary’s teaching and Horn’s teaching because it would provide for the purpose of The queue is configured to store a plurality of data items, wherein each data item has a type which is one of a plurality of types of data items that can be stored in the queue (Wang, paragraph 0009).
As per claim 5, Mccrary discloses wherein updating the mapping data structure comprises changing a value of at least one bit in the mapping data structure mapped to a doorbell register of the plurality of doorbell registers associated with the unmapped queue doorbell (FIG. 4; paragraphs 0027-0030: “For example, the scheduler can change the value of the index from “0” to “1” to indicate that the queue is to be removed from the mapped queue list and added to the unmapped queue list so that the queue is associated with the aggregate doorbell”).
As per claim 15, it is a processing device claim, which recite(s) the same limitations as those of claim 4. Accordingly, claim 15 is rejected for the same reasons as set forth in the rejection of claim 4.
As per claim 16, it is a processing device claim, which recite(s) the same limitations as those of claim 5. Accordingly, claim 16 is rejected for the same reasons as set forth in the rejection of claim 5.
Claims 3 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Mccrary in view of Horn, as applied to claims 1 and 8, and further in view of US 2006/0143363 to Steffan.
As per claim 3, Mccrary discloses responsive to a hardware queue mapping list indicating the command buffer is an unmapped queue (FIGs. 1-2; paragraphs 0020-0021 and 0024-0026: the command buffer is added to empty queue associated with a list 240 (aggregate doobells) [Wingdings font/0xE0] unmapped command buffers), determining the queue doorbell is an unmapped queue doorbell (FIGs. 1-2; paragraphs 0020-0021 and 0024-0026: the command buffer is added to empty queue associated with a list 240 (aggregate doorbells) [Wingdings font/0xE0] aggregate doorbell which is not one to one doorbell 235 to the pipeline for execution [Wingdings font/0xE0] unmapped doorbells); and
responsive to the queue doorbell being a mapped queue doorbell, passing the queue doorbell to a command processor of the processing device (FIGs. 1-2; paragraphs 0020-0021 and 0024-0026: list doorbell 235 [Wingdings font/0xE0] mapped to the pipelines for execution);
responsive to the queue doorbell being a mapped queue doorbell, passing the command buffer to a command processor of the processing device (FIGs 1-2), and the doorbell is a queue doorbell (FIGs. 1-2)
Mccrary discloses work has been placed into a command buffer, however, Mccrary does not explicitly disclose the command buffer is a queue.
Horn further discloses the command buffer is a queue (paragraph 0047: “The admin queue 258 may be implemented in a fashion that is similar to the command queue, such as through full hardware automation or ring buffer.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Horn into Mccrary’s teaching because it would provide for the purpose of the controller may also have several queues to enable the bridge to return information related to data commands (completion, error, etc.). In addition, the bridge can report other status, errors, and indicate non-critical information (i.e., info/health reports) related to the operation of the bridge and the NVM (Horn, paragraph 0056).
Steffan further discloses responsive to the doorbell being a mapped doorbell (paragraph 0015: “The CPU can access status registers 18 via peripheral bus 28. Status registers 18 are memory mapped to allow the CPU to read the information contained therein directly without passing by CAN message handler 14. This allows an effective polling of CAN module status flags.” [Wingdings font/0xE0] the status register (doorbell as claimed) is memory mapped), passing the doorbell to a command processor of the processing device (paragraph 0015: “The CPU can access status registers 18 via peripheral bus 28. Status registers 18 are memory mapped to allow the CPU to read the information contained therein directly without passing by CAN message handler 14. This allows an effective polling of CAN module status flags.” [Wingdings font/0xE0] in respond to the status register (doorbell as claimed) is memory mapped [Wingdings font/0xE0] the CPU reads the information contained in the memory by accessing to the register).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Steffan into Mccrary’s teaching and Horn’s teaching because it would provide for the purpose of The CPU can access status registers 18 via peripheral bus 28. Status registers 18 are memory mapped to allow the CPU to read the information contained therein directly without passing by CAN message handler 14. This allows an effective polling of CAN module status flags (Steffan, paragraph 0056).
As per claim 14, Mccrary discloses responsive to the queue doorbell being a mapped queue doorbell, passing the command buffer to a command processor of the processing device (FIGs 1-2), and the doorbell is a queue doorbell (FIGs. 1-2)
Mccrary discloses work has been placed into a command buffer, however, Mccrary does not explicitly disclose the command buffer is a queue.
Horn further discloses the command buffer is a queue (paragraph 0047: “The admin queue 258 may be implemented in a fashion that is similar to the command queue, such as through full hardware automation or ring buffer.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Horn into Mccrary’s teaching because it would provide for the purpose of the controller may also have several queues to enable the bridge to return information related to data commands (completion, error, etc.). In addition, the bridge can report other status, errors, and indicate non-critical information (i.e., info/health reports) related to the operation of the bridge and the NVM (Horn, paragraph 0056).
Steffan further discloses responsive to the doorbell being a mapped doorbell (paragraph 0015: “The CPU can access status registers 18 via peripheral bus 28. Status registers 18 are memory mapped to allow the CPU to read the information contained therein directly without passing by CAN message handler 14. This allows an effective polling of CAN module status flags.” [Wingdings font/0xE0] the status register (doorbell as claimed) is memory mapped), passing the doorbell to a command processor of the processing device (paragraph 0015: “The CPU can access status registers 18 via peripheral bus 28. Status registers 18 are memory mapped to allow the CPU to read the information contained therein directly without passing by CAN message handler 14. This allows an effective polling of CAN module status flags.” [Wingdings font/0xE0] in respond to the status register (doorbell as claimed) is memory mapped [Wingdings font/0xE0] the CPU reads the information contained in the memory by accessing to the register).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Steffan into Mccrary’s teaching and Horn’s teaching because it would provide for the purpose of The CPU can access status registers 18 via peripheral bus 28. Status registers 18 are memory mapped to allow the CPU to read the information contained therein directly without passing by CAN message handler 14. This allows an effective polling of CAN module status flags (Steffan, paragraph 0056).
Conclusion
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/TUAN C DAO/ Primary Examiner, Art Unit 2198