SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF

§103 §112 §251 §DOUBLEPATENT

Notice of Pre-AIA or AIA Status The present application is being examined under the pre-AIA first to invent provisions. For reissue applications filed before September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the law and rules in effect on September 15, 2012. Where specifically designated, these are “pre-AIA ” provisions. For reissue applications filed on or after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions. NONFINAL OFFICE ACTION This Office Action addresses U.S. Patent Application No. 18/374,840, which is filed as a continuation of U.S. Patent Application No. 17/007,206, now abandoned. U.S. Patent Application No. 18/374,840 is also a reissue of U.S. Patent Application No. 12/354,158 (hereinafter, the '158 application), entitled “SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF”, now issued as U.S. Patent No. 7,746,723 (hereinafter, the '723 patent). U.S. Patent Application No. 17/007,206 was filed as a continuation of U.S. Patent Application No.14/100,793, now issued as U.S. Patent No. RE48341 (hereinafter, the '341 patent), which was filed as a continuation of U.S. Patent Application No. 13/538,130, now issued as U.S. RE44632 (hereinafter, the '632 patent). U.S. Patent Application Nos. 17/007,206, 14/100,793 and 13/538,130 were each filed as reissues of the '158 application. The '158 application a continuation of U.S. Application Ser. No. 11/647,402, now issued as U.S. Patent No. 7,489,586. The above applications claim foreign priority to KR 10-2006-0059735, filed June 29, 2006. CLAIM STATUS Original patent claims 1-10 have been canceled. Patent claim 11 has been amended. Claims 12-17 are newly presented with this reissue application. PRIOR OR CONCURRENT PROCEEDINGS Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which the patent is or was involved. These proceedings would include interferences, reissues, reexaminations, and litigation. Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application. These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04. In accordance with MPEP § 1406, the examiner has reviewed and considered the prior art made of record during the prosecution of the original patent. Such prior art need not be resubmitted in this reissue application unless applicant desires the information to be printed on a patent issuing from this reissue application. APPLICATION DATA SHEET The Application Data Sheet is objected to because on page 7, in the Applicant Information section, the “Mailing Address Information For Applicant” city name is misspelled. SPECIFICATION The disclosure is objected to because of the following informalities: (1) The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For example, there are no claims directed to a “device”. Independent claim 11 is directed to receiving a calibration command from a chipset, measuring an output AC parameter of a data strobe signal in response to the calibration command, controlling a clock delay according to a value of the output AC parameter and transferring data in accordance with the calibrated parameters and in response to a strobe signal. (2) In the first paragraph of the specification, the status of U.S. Patent Application No. 17/007,206 should be updated, i.e., “now abandoned”. Appropriate correction is required. CLAIM SUPPORT Applicant must provide an explanation of the support in the disclosure of the patent for the changes made to the claims. The explanation of support must be on page(s) separate from the page(s) containing the amendment. Note the discussion below regarding the lack of written description for some of the claim limitations. Either (1) an explanation of support for each of limitations of the amended claims or (2) removal of the unsupported claims is required in response to this Office action. Note MPEP 1411.02. Note also MPEP 1453(V)(D), which shows examples of proper support, wherein a separate citation is provided for each new limitation of each claim. OBJECTIONS BASED ON DEFECTIVE OATH/DECLARATION The statement of error in the substitute statements in lieu of a reissue oath/declaration filed September 29, 2023 is as follows: “Patentee of U.S. Patent No. 7,746,723 claimed less than Patentee had the right to claim. As one example, each of independent claims 1, 4, 9, and 11 recites "AC parameters" in the plural form, which is not required for patentability. For example, issued independent claim 11 recites limitations of "measuring AC parameters," "controlling a delay time of a clock according to measured values of the AC parameters," and "transferring a second data having calibrated AC parameters.' Amended independent claim 11 seeks to broaden issued independent claim 11, e.g., by instead reciting the term "AC parameter" in the singular form in each of those limitations. This reissue continuation application seeks to correct this error in a different way from preceding reissue Appl. No. 13/538,13 filed June 29, 2012, now issued as U.S. Reissued Patent No. RE44,632, e.g., by reciting in amended claim 11 that the second data strobe signal is transferred to the chipset in synchronization with the second data, rather than in response to the clock as recited in claim 11 of RE44,632.” The substitute statements in lieu of a reissue oath/declaration filed with this application is objected to as defective (see 37 CFR 1.175 and MPEP § 1414) for the reasons set forth below: (1) The statement of error states, “Amended independent claim 11 seeks to broaden issued independent claim 11, e.g., by instead reciting the term "AC parameter" in the singular form”. However, statement concedes that this error was already corrected by the issuance of U.S. Patent No. RE44,632. A stated desire to “correct this error in a different way” is not a basis for reissue. (2) The statement of error states, “This reissue continuation application seeks to correct this error … by reciting in amended claim 11 that the second data strobe signal is transferred to the chipset in synchronization with the second data, rather than in response to the clock”. A broadening amendment that invokes impermissible recapture is not a basis for reissue. REJECTIONS BASED ON DEFECTIVE OATH/DECLARATION The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. §251 that form the basis for the rejections under this section made in this Office action: (a) IN GENERAL.—Whenever any patent is, through error, deemed wholly or partly inoperative or invalid, by reason of a defective specification or drawing, or by reason of the patentee claiming more or less than he had a right to claim in the patent, the Director shall, on the surrender of such patent and the payment of the fee required by law, reissue the patent for the invention disclosed in the original patent, and in accordance with a new and amended application, for the unexpired part of the term of the original patent. No new matter shall be introduced into the application for reissue. Defective Reissue Declaration Claims 11-17 are rejected as being based upon a defective reissue declaration under 35 U.S.C. §251. The declaration is defective for all of the reasons set forth above with regard to the objections to the declaration. See 37 CFR 1.175. Impermissible Recapture Claims 11-17 lack subject matter surrendered during the prosecution of the '158 application. Claims 11-17 lack the following language which was added to claim 26 (issued as claim 11 in the '723 patent) to overcome rejections based on the prior art during the prosecution of the '158 application: “transferring a second data and a second data strobe signal having calibrated output AC parameters to the chipset in response to the delayed clock” (amendment of December 3, 2009, emphasis added) The limitations cited above were surrendered during the prosecution of the '158 application. On September 3, 2009, a non-final Office action was mailed in the '158 application, wherein independent claim 26, among others, was rejected based on prior art. In response to the rejection, the December 3, 2009 amendment was filed with the language shown above, in order to overcome the rejection. Pages 9-10 of the remarks submitted with the December 3, 2009 amendment cite the added claim limitations noted above in arguments describing why the amended claims overcome the prior art rejection. In response to these amendments, a notice of allowance was mailed on February 17, 2010. The three step test for recapture: Step 1 - Is There Broadening? Are the reissue claims broader than the original patent claims in at least some respects? Yes, for example, amended claim 11 lacks the above-cited language which is required of claim 11 of the '723 patent. A claim is broadened if it is broader in any one respect even though it may be narrower in other respects. Step 2 - Does Any Broadening Aspect of the Reissued Claim Relate to Surrendered Subject Matter? Substep 1 – Did applicant surrender any subject matter in the prosecution of the original application that became the patent to be reissued? Yes, the surrendered subject matter is noted above. Substep 2 - Does the broadening in the reissue claims result from eliminating limitations surrendered in the original prosecution? Yes, present claims 11-17 omit limitations that the prosecution record shows as added to claim 26 (issued as claim 11) to overcome rejections based on prior art during the original prosecution. Step 3 - Are the Reissue Claims Materially Narrowed in Other Respects, and Hence Avoid the Recapture Rule? The reissue claims are narrowed in other respects but are not materially narrowed in other respects. Thus, claims 11-17 are rejected under 35 U.S.C. §251 because they lack the subject matter added to obtain patentability during prosecution of the original patent, U.S. Patent No. 7,746,723. See Greenliant Systems, Inc. et al v. Xicor LLC, 692 F.3d 1261, 103 USPQ2d 1951 (Fed. Cir. 2012); In re Shahram Mostafazadeh and Joseph O. Smith, 643 F.3d 1353, 98 USPQ2d 1639 (Fed. Cir. 2011); North American Container, Inc. v. Plastipak Packaging, Inc., 415 F.3d 1335, 75 USPQ2d 1545 (Fed. Cir. 2005); Pannu v. Storz Instruments Inc., 258 F.3d 1366, 59 USPQ2d 1597 (Fed. Cir. 2001); Hester Industries, Inc. v. Stein, Inc., 142 F.3d 1472, 46 USPQ2d 1641 (Fed. Cir. 1998); In re Clement, 131 F.3d 1464, 45 USPQ2d 1161 (Fed. Cir. 1997); Ball Corp. v. United States, 729 F.2d 1429, 1436, 221 USPQ 289, 295 (Fed. Cir. 1984). A broadening aspect is present in the reissue which was not present in the application for patent. The record of the application for the patent shows that the broadening aspect (in the reissue) relates to claimed subject matter that applicant previously surrendered during the prosecution of the application. Accordingly, the narrow scope of the claims in the patent was not an error within the meaning of 35 U.S.C. 251, and the broader scope of claim subject matter surrendered in the application for the patent cannot be recaptured by the filing of the present reissue application. Original Patent Requirement Claims 11-17 are rejected as failing to satisfy the original patent requirement of 35 USC § 251. The reissue claims must be for the same invention as that disclosed as being the invention in the original patent, as required by 35 U.S.C. 251. The entire disclosure, not just the claim(s), is considered in determining what the patentee objectively intended as the invention. The determination of the original patent requirement is “an essentially factual inquiry confined to the objective intent manifested by the original patent.” In re Amos, 953 F.2d 613, 618, 21 USPQ2d 1271, 1274 (Fed. Cir. 1991) (quoting In re Rowand, 526 F.2d 558, 560, 187 USPQ 487, 489 (CCPA 1975)) (emphasis added); See also In re Mead, 581 F.2d 251, 256, 198 USPQ 412, 417 (CCPA 1978). The original patent disclosure does not support “transferring a second data having a calibrated output AC parameter to the chipset in response to the delayed clock and transferring a second data strobe signal to the chipset in synchronization with the second data” in claim 11. The original patent disclosure does not support that “the memory system is a synchronous DDR memory system” in claim 12. Consequently, claims 11-17 do not meet the original patent requirement of § 251. DOUBLE PATENTING The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claims 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 11 of U.S. Patent No. 7,746,723. Although the claims at issue are not identical, they are not patentably distinct from each other because each of the claims of the patent is either taught or suggested by the present claims. As an example, note the following side-by-side comparison of the following independent claims: U.S. Application No. 18/374,840 U.S. Patent No. 7,746,723 11. A method for operating a synchronous semiconductor system, comprising: 11. A method for driving a semiconductor memory device, comprising: receiving a calibration command from a chipset via at least one of command and address inputs; receiving a calibration command from a chipset; receiving a first data and a first data strobe signal from the chipset; receiving a first data and a first data strobe signal from the chipset; measuring an output AC parameter of the first data and the first data strobe signal in response to the calibration command; measuring AC parameters of the first data and the first data strobe signal in response to the calibration command; controlling a delay time of a clock according to a measured value of the output AC parameter; and controlling the delay time of a clock according to measured values of the AC parameters; and transferring a second data having a calibrated output AC parameter to the chipset in response to the delayed clock and transferring a second data strobe signal to the chipset in synchronization with the second data. transferring a second data and a second data strobe signal having calibrated output AC parameters to the chipset in response to the delayed clock. Claims 11-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6-11 of U.S. Patent No. 7,489,586. Although the claims at issue are not identical, they are not patentably distinct from each other because each of the present claims is either taught or suggested by the claims of the patent. As an example, note the following side-by-side comparison of the following independent claims (the limitations of U.S. Patent No. 7,489,586 are mapped out of order to show correspondence): U.S. Application No. 18/374,840 U.S. Patent No. 7,489,586 11. A method for operating a synchronous semiconductor system, comprising: 6. A method for driving a semiconductor memory device, comprising: receiving a calibration command from a chipset via at least one of command and address inputs; outputting data strobe signal and data having calibrated output AC parameters in response to the delayed DLL clock receiving a first data and a first data strobe signal from the chipset; feeding back the data and the data strobe signal of being transmitted to a chipset in response to the calibration test mode signal measuring an output AC parameter of the first data and the first data strobe signal in response to the calibration command; measuring output AC parameters; wherein the measuring of the output AC parameters comprises: generating a calibration test mode signal in response to a calibration command controlling a delay time of a clock according to a measured value of the output AC parameter; and setting a delay value with respect to a delay locked loop (DLL) clock in response to the measured values of the output AC parameters delaying the DLL clock by the delay value to output a delayed DLL clock transferring a second data having a calibrated output AC parameter to the chipset in response to the delayed clock and transferring a second data strobe signal to the chipset in synchronization with the second data. measuring the output AC parameters by using the fed-back data strobe signal and the fed-back data The remaining claims are taught or suggested in a similar manner. Claims 11-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 11-39 of U.S. Patent No. RE44632. Although the claims at issue are not identical, they are not patentably distinct from each other because each of the claims of the patent is either taught or suggested by the present claims. As an example, note the following side-by-side comparison of the following independent claims: U.S. Application No. 18/374,840 U.S. Patent No. RE44632 11. A method for operating a synchronous semiconductor system, comprising: 11. A method for driving a semiconductor memory device system, comprising: receiving a calibration command from a chipset via at least one of command and address inputs; receiving a calibration command from a chipset; receiving a first data and a first data strobe signal from the chipset; receiving a first data and a first data strobe signal from the chipset; measuring an output AC parameter of the first data and the first data strobe signal in response to the calibration command; measuring an AC parameters parameter of the first data and the first data strobe signal in response to the calibration command; controlling a delay time of a clock according to a measured value of the output AC parameter; and controlling the delay time of a clock according to measured values of the AC parameters parameter; and transferring a second data having a calibrated output AC parameter to the chipset in response to the delayed clock and transferring a second data strobe signal to the chipset in synchronization with the second data. transferring a second data and a second data strobe signal having a calibrated output AC parameters parameter to the chipset in response to the delayed clock and transferring a second data strobe signal to the chipset in response to the clock. The remaining claims are taught in a similar manner. Claims 11-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 9-20 of U.S. Patent No. RE48341. Although the claims at issue are not identical, they are not patentably distinct from each other because each of the claims of the patent is either taught or suggested by the present claims. As an example, note the following side-by-side comparison of the following independent claims: U.S. Application No. 18/374,840 U.S. Patent No. RE48341 11. A method for operating a synchronous semiconductor system, comprising: 11. A method for driving a semiconductor memory device, comprising: receiving a calibration command from a chipset via at least one of command and address inputs; receiving a calibration command from a chipset; receiving a first data and a first data strobe signal from the chipset; receiving a first data and a first data strobe signal from the chipset; measuring an output AC parameter of the first data and the first data strobe signal in response to the calibration command; measuring AC parameters of the first data and the first data strobe signal in response to the calibration command; controlling a delay time of a clock according to a measured value of the output AC parameter; and controlling the delay time of a clock according to measured values of the AC parameters; and transferring a second data having a calibrated output AC parameter to the chipset in response to the delayed clock and transferring a second data strobe signal to the chipset in synchronization with the second data. transferring a second data and a second data strobe signal having calibrated output AC parameters to the chipset in response to the delayed clock. The remaining claims are taught in a similar manner. CLAIM INTERPRETATION The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. None of the limitations of claims 11-17 are deemed to invoke 35 U.S.C. § 112, 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph. CLAIM REJECTIONS - 35 USC § 112, 1st PARAGRAPH The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 11-17 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. With regard to claim 11, the disclosure does not teach “transferring a second data having a calibrated output AC parameter to the chipset in response to the delayed clock and transferring a second data strobe signal to the chipset in synchronization with the second data.” With regard to claim 12, the disclosure does not teach that in the invention a “memory system is a synchronous DDR memory system”. The only mention of DDR SDRAM is in the discussion of the prior art / related art (cf. Figure 2). Double data rate (DDR) is never mentioned in the discussion of the invention itself. With regard to claim 17, the disclosure does not teach that in the invention “the measured AC parameter is a selected one of a skew between the data strobe signal and the data, a skew between the data strobe signal and a system clock. and a skew between data and the system clock”. (a) First, there is no mention of any selection step for skew options. (b) Second, while the specification does disclose that “The timing measurer 58 measures skew between the data DQ and the data strobe signal DQS and controls the delay time (τd) of the DLL clock DLL_CLK according to the measured skew”, it does not mention “a skew between the data strobe signal and the data, a skew between the data strobe signal and a system clock. and a skew between data and the system clock”. The only mention of these three skew measurements is in the discussion of the prior art / related art (cf. Figures 1 and 2). Only one type of skew measurement is ever mentioned in the discussion of the invention itself. Claims 13-16 are rejected as being ultimately dependent upon rejected claim 11. CLAIM REJECTIONS - 35 USC § 112, 2nd PARAGRAPH The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 14-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In claim 14, “receiving a first data and a first data strobe signal from the chipset comprises receiving a plurality of first data and first data strobe signals from the chipset” it is unclear and unexplained as to how receiving a first data signal and a first data strobe signal could comprise receiving a plurality of such signals. In claim 14, “measuring an AC parameter of the first data and the first data strobe signal in response to the calibration command comprises measuring a plurality of AC parameters corresponding to the plurality of first data and first data strobe signals” is unclear and unexplained as to how measuring one signal would comprise measuring many signals. Claims 15-17 are rejected as being ultimately dependent upon rejected claim 14. CLAIM REJECTIONS - 35 USC § 103(a) The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action: (a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 11-17 are is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Best, U.S. Patent No. 7,171,321 (“Best”) in view of applicant’s admitted prior art (“AAPA”). U.S. Application No. 18/374,840 Best / AAPA 11. A method for operating a synchronous semiconductor system, comprising: Best does not explicitly recite “a synchronous semiconductor system”, but does teach synchronization, note, e.g., Figure 3, Step 308, “Adjust delayed strobe signal using optimal offset.” Note AAPA, column 1, lines 22-27, “A synchronous semiconductor memory device shares a system clock output from a clock generator with a chipset and receives or transfers command, address and data in synchronization with the system clock. FIG. 1 is a block diagram of a communication scheme between a synchronous dynamic random access memory” [See below for the discussion of obviousness] receiving a calibration command from a chipset via at least one of command and address inputs; Note Best, the chipset “memory system 199” and calibration output command, “calibrate-enable signal 122” receiving a first data and a first data strobe signal from the chipset; Note Best, data signals DQ<X> and corresponding strobe signals DQS measuring an output AC parameter of the first data and the first data strobe signal in response to the calibration command; Note Best, e.g., column 5, lines 29-32, “In the calibration mode the receiver 102 generally operates as a phase detector and determines any phase difference between a delayed data signal DQ<X>' and the strobe signal DQS'” controlling a delay time of a clock according to a measured value of the output AC parameter; and Note Best, e.g., column 5, lines 34-44, “The receiver/phase detector 102 compares the phase relationship between the strobe signal DQS' and the delayed data signals DQ<X>' for each received data bit, and provides those comparison results to the calibration control circuit 120 via the adjustment control signal 114. In response to the adjustment control signal 114, and optionally in additional response to the adjustment valid signal 116, the calibration control circuit 120 will adjust the delay control signal 124 which affects the delay value applied to the strobe signal DQS via the variable delay circuit 130.” transferring a second data having a calibrated output AC parameter to the chipset in response to the delayed clock and transferring a second data strobe signal to the chipset in synchronization with the second data. Note Best, e.g., column 8, lines 39-47, “a second delayed data signal DQ<3>', the rising/falling edges of this data signal DQ<3>' during the example dummy read (calibration mode) are offset from the rising/falling edges of the strobe signal DQS by a second phase difference 512. The DLL (receiver (phase detector), calibration control circuit, variable delay element) detects the phase difference 512, adjusts a variable delay 514 to compensate for the phase difference, and applies the adjusted delay 514 to the strobe signal DQS.” As noted above, Best does not explicitly recite “a synchronous semiconductor system”. However, synchronization is taught throughout the Best disclosure. Note, e.g., Figure 3, Step 308, “Adjust delayed strobe signal using optimal offset.” In any case, AAPA explicitly teaches this feature as prior / related art, column 1, lines 22-27, “A synchronous semiconductor memory device shares a system clock output from a clock generator with a chipset and receives or transfers command, address and data in synchronization with the system clock. FIG. 1 is a block diagram of a communication scheme between a synchronous dynamic random access memory”. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to incorporate “a synchronous semiconductor system” as described in AAPA as the synchronous memory of Best, since (1) Best explicitly taught the synchronization of signals (adjusting delays, etc) and (2) one of ordinary skill in the art at the time the invention was made that in high speed memory systems, that why asynchronous operations were necessary in some respects, synchronized operation was key to fast and efficient data transfers. With regard to claims 12-17: U.S. Application No. 18/374,840 Best / AAPA 12. The method of claim 11, wherein the memory system is a synchronous DDR memory system. Note Best, DDR memory system 1099 13. (New) The method of claim 11, wherein controlling the delay time of a clock comprises controlling the delay time of a DLL. Note Best, column 7, lines 45-50, “the combination of the receiver/phase detector 102, calibration control circuit 120 and variable delay element 130 effectively form a DLL circuit. This DLL circuit, in response to phase information of the delayed data signal DQ<X>' and corresponding delayed strobe signal DQS', adjusts the phase relationship between these signals” 14. (New) The method of claim 11, wherein: receiving a first data and a first data strobe signal from the chipset comprises receiving a plurality of first data and first data strobe signals from the chipset; and measuring an AC parameter of the first data and the first data strobe signal in response to the calibration command comprises measuring a plurality of AC parameters corresponding to the plurality of first data and first data strobe signals. Note Best, e.g., column 5, lines 34-44, “The receiver/phase detector 102 compares the phase relationship between the strobe signal DQS' and the delayed data signals DQ<X>' for each received data bit, and provides those comparison results to the calibration control circuit 120 via the adjustment control signal 114. In response to the adjustment control signal 114, and optionally in additional response to the adjustment valid signal 116, the calibration control circuit 120 will adjust the delay control signal 124 which affects the delay value applied to the strobe signal DQS via the variable delay circuit 130.” 15. The method of claim 14, wherein controlling the delay time of a clock according to measured values of the AC parameter comprises controlling a plurality of delay times of a clock in response to the measured values of the AC parameters corresponding to the plurality of first data and first data strobe signals. Note Best, e.g., column 5, lines 34-44, “The receiver/phase detector 102 compares the phase relationship between the strobe signal DQS' and the delayed data signals DQ<X>' for each received data bit, and provides those comparison results to the calibration control circuit 120 via the adjustment control signal 114. In response to the adjustment control signal 114, and optionally in additional response to the adjustment valid signal 116, the calibration control circuit 120 will adjust the delay control signal 124 which affects the delay value applied to the strobe signal DQS via the variable delay circuit 130.” 16. The method of claim 14, wherein measuring an AC parameter of the first data and the first data strobe signal in response to the calibration command comprises measuring a parameter representing skew between two signals. Note Best, e.g., column 5, lines 29-32, “In the calibration mode the receiver 102 generally operates as a phase detector and determines any phase difference between a delayed data signal DQ<X>' and the strobe signal DQS'” Note also AAPA, in the discussion of the prior / related art Figure 1, “The data strobe signal DQS is used for source synchronization and is also called “echo clock”. If the data DQS is strobed in synchronization with the data strobe signal DQS, skew between the clock CLK and the data DQS can be reduced.” 17. The method of claim 16, wherein the measured AC parameter is a selected one of a skew between the data strobe signal and the data, a skew between the data strobe signal and a system clock. and a skew between data and the system clock. Note Best, e.g., column 8, lines 39-47, “a second delayed data signal DQ<3>', the rising/falling edges of this data signal DQ<3>' during the example dummy read (calibration mode) are offset from the rising/falling edges of the strobe signal DQS by a second phase difference 512. The DLL (receiver (phase detector), calibration control circuit, variable delay element) detects the phase difference 512, adjusts a variable delay 514 to compensate for the phase difference, and applies the adjusted delay 514 to the strobe signal DQS.” Note also AAPA, explicitly teaches this in the discussion of the prior / related art Figure 2, “Timing of data DQ and data strobe signal DQS is illustrated in FIG. 2. In FIG. 2, “tDQSQ” is a parameter representing skew between the data strobe signal DQS and the data DQ, “tDQSCK” is a parameter representing skew between the data strobe signal DQS and clock CLK, and “tAC” is a parameter representing skew between the data DQ and the clock CLK.” CONCLUSION Any inquiry concerning this communication or earlier communications from the examiner should be directed to B. James Peikari at telephone number 571-272-4185. The examiner can normally be reached on Mon-Fri from 8:30am to 5:30pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Kosowski, SPE Art Unit 3992, can be reached at 571-272-3744. Information regarding the status of published reissue applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Any inquiry concerning this communication or earlier communications from the examiner, or as to the status of this proceeding, should be directed to the Central Reexamination Unit at telephone number (571) 272-7705. /B. James Peikari/ Primary Examiner, Art Unit 3992 Conferees: /C. Michelle Tarae/Primary Examiner, Art Unit 3992 /ALEXANDER J KOSOWSKI/Supervisory Patent Examiner, Art Unit 3992