DETAILED ACTION
This action is in response to the Election 08/18/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Election/ Restriction
Applicant's election with traverse of Invention I and Specie I in the reply filed on 01/20/2026 is acknowledged. The traversal is on the ground(s) that “the Restriction has failed to carry the burden of showing that the there would be a serious burden on the Examiner if restriction is not required. To the contrary, the Examiner has stated that all independent claims are generic to the two Species identified by the Examiner, and further stated, "The species are independent or distinct because Specie I and Specie II comprises different and mutually exclusive features". This is not found persuasive because:
-The Examiner has proven in pages 2 – 4 of Office Action 08/18/2025 that the inventions as claimed have materially different design and mode of operation, do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants.
- Applicant’s argument above is only directed to the Species Restriction, where as shown in Fig. 7 and Fig. 8, they are directed to different Species, directed to different method steps, generic to the different Inventions I – III.
The requirement is still deemed proper and is therefore made FINAL.
Claim Objections
Claim(s) 2 is/are objected to because of the following informalities:
Claim 2 recites “the second terminal of the error amplifier coupled to the control terminal of the first transistor and the control terminal of the fourth transistor”. Claim 1 recites “error detection circuitry having a terminal”, “the control terminal of the first transistor coupled to the terminal of the error detection circuitry” and “the control terminal of the fourth transistor coupled to the terminal of the error detection circuitry”. It appears that “the second terminal of the error amplifier” of claim 2 corresponds to “the terminal” of the error detection circuitry of claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US Pub. No. 2022/0231611; (hereinafter Blanco).
Regarding claim 1, Blanco [e.g. Fig. 3] discloses an apparatus comprising:
error detection circuitry [e.g. 302] having a terminal [e.g. output of 302];
first controller circuitry including:
a first transistor [e.g. 312] having a first terminal [e.g. drain terminal (upper)] and a control terminal [e.g. gate (center)], the control terminal of the first transistor coupled to the terminal of the error detection circuitry [e.g. via 304, 306];
a second transistor [e.g. 318] having a first terminal [e.g. source terminal (lower)] and a control terminal [e.g. gate (center)];
first current source circuitry [e.g. 313] having a terminal [e.g. lower terminal]; and
a third transistor [e.g. 310] having a control terminal [e.g. gate (center)] coupled to the first terminal of the first transistor, the first terminal of the second transistor [e.g. via 312 and 319], the control terminal of the second transistor [e.g. via 312, 310 and source of 318], and the terminal of the first current source circuitry [e.g. lower terminal of 313]; and
second controller circuitry including:
a fourth transistor [e.g. 316] having a first terminal [e.g. drain (upper) terminal] and a control terminal [e.g. gate (center) terminal], the control terminal of the fourth transistor coupled to the terminal of the error detection circuitry [e.g. output of 302];
a fifth transistor [e.g. 322] having a first terminal [e.g. drain (lower) terminal] and a control terminal [e.g. gate (center) terminal];
a sixth transistor [e.g. 321] having a first terminal [e.g. source (lower) terminal] and a control terminal [e.g. gate (center) terminal], the control terminal of the sixth transistor coupled to the first terminal of the fourth transistor [e.g. upper terminal of 316], the first terminal of the fifth transistor [e.g. lower terminal of 322 via drain of 321], and the control terminal of the fifth transistor [e.g. gate terminal of 322 via drain of 321]; and
second current source circuitry [e.g. 320] having a terminal [e.g. lower terminal] coupled to the first terminal of the sixth transistor [e.g. lower terminal of 321 via 316].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claims 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Blanco in view of US Pub. No. 2017/0025950; (hereinafter Wu).
Regarding claim 2, Blanco [e.g. Fig. 3] discloses wherein the error detection circuitry comprising: an error amplifier [e.g. 302] having a first terminal [e.g. inverting input] and a second terminal [e.g. output of 302], the second terminal of the error amplifier coupled to the control terminal of the first transistor [e.g. 312] and the control terminal of the fourth transistor [e.g. 316].
Blanco fails to disclose the error detection circuitry comprising: resistor divider circuitry having a terminal; and the first terminal of the error amplifier coupled to the terminal of the resistor divider circuitry.
Wu [e.g. Fig. 1] teaches the error detection circuitry comprising: resistor divider circuitry [e.g. resistors directly connected to inverting input of 152] having a terminal [e.g. node between resistors]; and the first terminal of the error amplifier [e.g. inverting of 152] coupled to the terminal of the resistor divider circuitry.
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Blanco by the error detection circuitry comprising: resistor divider circuitry having a terminal; and the first terminal of the error amplifier coupled to the terminal of the resistor divider circuitry as taught by Wu in order of being able to reduce a voltage level of the output voltage, appropriate for a control circuitry.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
Claims 3 – 6 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 3 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further comprising first controller circuitry including: third current source circuitry having a terminal; a seventh transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the seventh transistor coupled to the terminal of the third current source circuitry, the control terminal of the seventh transistor coupled to the control terminal of the first transistor and the control terminal of the fourth transistor; and a resistor having a terminal coupled to the second terminal of the seventh transistor”.
The primary reason for the indication of the allowability of claim 4 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the second controller circuitry further including: a seventh transistor having a first terminal and a control terminal; and an eighth transistor having a control terminal coupled to the first terminal of the sixth transistor, the terminal of the second current source circuitry, the first terminal of the seventh transistor, and the control terminal of the seventh transistor”.
Claim(s) 5 – 6 are objected to as being dependent upon claim(s) 4.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Torres-Rivera whose telephone number is (571)272-5261. The examiner can normally be reached M-F 9:00-5:30 ET.
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838