DETAILED ACTION
This action is in response to the 07/10/2026 amendment.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restriction
Newly submitted claims 21 - 34 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: the inventions as claimed have materially different design, mode of operation, function and effect and do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants.
Claim 1 (Invention I)
Claim 21 (Invention II)
Claim 30 (Invention III)
An apparatus comprising:
error detection circuitry having a terminal;
first controller circuitry including:
a first transistor having a first terminal and a control terminal, the control terminal of the first transistor coupled to the terminal of the error detection circuitry;
a second transistor having a first terminal and a control terminal;
first current source circuitry having a terminal; and
a third transistor having a control terminal coupled to the first terminal of the first transistor, the first terminal of the second transistor, the control terminal of the second transistor, and the terminal of the first current source circuitry; and
second controller circuitry including:
a fourth transistor having a first terminal and a control terminal, the control terminal of the fourth transistor coupled to the terminal of the error detection circuitry;
a fifth transistor having a first terminal and a control terminal;
a sixth transistor having a first terminal and a control terminal, the control terminal of the sixth transistor coupled to the first terminal of the fourth transistor, the first terminal of the fifth transistor, and the control terminal of the fifth transistor; and
second current source circuitry having a terminal coupled to the first terminal of the sixth transistor.
A method comprising:
supplying a current and a voltage;
detecting a difference between the voltage and a reference voltage;
generating an error voltage based on the difference between the voltage and the reference voltage;
generating a control current responsive to the error voltage;
comparing the control current to a first reference current;
responsive to the control current being greater than the first reference current, generating a peak current based on the control current and the first reference current; comparing the control current to a second reference current; responsive to the control current being less than the second reference current, generating a valley current based on the control current and the second reference current; and
generating an output current and an output voltage responsive to the peak current and the valley current.
A switching power converter system comprising:
power stage circuitry having first and second supply inputs, an inductor, and an output;
a peak-valley controller circuitry comprising:
an input coupled to the output of the power stage circuitry,
a first output; and a second output;
peak comparator circuitry comprising:
an input coupled to the first output of the peak-valley controller circuitry; and
an output;
valley comparator circuitry comprising:
an input coupled to the second output of the peak-valley controller circuitry; and
an output;
logic circuitry comprising:
a first input coupled to the output of the valley comparator circuitry;
a second input coupled to the output of the peak comparator circuitry; and
an output;
driver circuitry coupled to the output of the logic circuitry and coupled to the first and second supply inputs of the power stage circuitry; and
a load coupled to receive the output of the power stage circuitry.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21 - 34 withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Response to Arguments
Applicant's arguments filed 07/10/2026 have been fully considered but they are not persuasive.
Applicant(s) argue(s) with respect to claim 1:
“Paragraph [0173] of the applicant's specification, as published, states: "In this description, the term "couple" may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A."
The Examiner's interpretation of "coupled" is overly broad and inconsistent with the definition of "coupled" as defined in paragraph [0173] of the specification. For two given elements to be "coupled," paragraph [0173] requires that:
1. A functional relationship exists between the coupled elements.
2. Any intervening components must not alter the functional relationship between the coupled elements. Blanco fails to satisfy both requirements.
Therefore, the limitation from claim 1 that the control terminal of the third transistor is coupled to the first terminal of the second transistor is not anticipated by Blanco.
Therefore, the limitation from claim 1 that the control terminal of the third transistor is coupled to the control terminal of the second transistor is not anticipated by Blanco.
The Examiner's rejection interprets "coupled" in a manner inconsistent with the definition provided in paragraph [0173] of the specification. The rejection of claim 1 is not supported by Blanco. Accordingly, Applicant respectfully requests that the § 102 rejection of claim 1 be withdrawn and claim 1 be allowed.”
In response, to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., direct connection and functional relationship between coupled elements) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Further, claims must be given the broadest reasonable interpretation during
examination, and limitations appearing in the specification but not recited in the claim are not read into the claims (See M.P.E.P. 2111 [R-I]).
Therefore, the argument is not persuasive and the rejection of claim 1 under 35 USC 102(a)(1) and 102(a)(2) is maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US Pub. No. 2022/0231611; (hereinafter Blanco).
Regarding claim 1, Blanco [e.g. Fig. 3] discloses an apparatus comprising:
error detection circuitry [e.g. 302] having a terminal [e.g. output of 302];
first controller circuitry including:
a first transistor [e.g. 312] having a first terminal [e.g. drain terminal (upper)] and a control terminal [e.g. gate (center)], the control terminal of the first transistor coupled to the terminal of the error detection circuitry [e.g. via 304, 306];
a second transistor [e.g. 318] having a first terminal [e.g. source terminal (lower)] and a control terminal [e.g. gate (center)];
first current source circuitry [e.g. 313] having a terminal [e.g. lower terminal]; and
a third transistor [e.g. 310] having a control terminal [e.g. gate (center)] coupled to the first terminal of the first transistor [e.g. drain (upper) terminal of 312], the first terminal of the second transistor [e.g. via 312 and 319], the control terminal of the second transistor [e.g. via 312, 319 and source of 318], and the terminal of the first current source circuitry [e.g. lower terminal of 313]; and
second controller circuitry including:
a fourth transistor [e.g. 316] having a first terminal [e.g. drain (upper) terminal] and a control terminal [e.g. gate (center) terminal], the control terminal of the fourth transistor coupled to the terminal of the error detection circuitry [e.g. output of 302 via 314];
a fifth transistor [e.g. 322] having a first terminal [e.g. drain (lower) terminal] and a control terminal [e.g. gate (center) terminal];
a sixth transistor [e.g. 321] having a first terminal [e.g. source (lower) terminal] and a control terminal [e.g. gate (center) terminal], the control terminal of the sixth transistor coupled to the first terminal of the fourth transistor [e.g. upper terminal of 316], the first terminal of the fifth transistor [e.g. lower terminal of 322 via drain of 321], and the control terminal of the fifth transistor [e.g. gate terminal of 322 via drain of 321]; and
second current source circuitry [e.g. 320] having a terminal [e.g. lower terminal] coupled to the first terminal of the sixth transistor [e.g. lower terminal of 321 via 316].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claims 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Blanco in view of US Pub. No. 2017/0025950; (hereinafter Wu).
Regarding claim 2, Blanco [e.g. Fig. 3] discloses wherein the error detection circuitry comprising: an error amplifier [e.g. 302] having a first terminal [e.g. inverting input] and a second terminal [e.g. output of 302], the second terminal of the error amplifier coupled to the terminal of the error detection circuitry [e.g. output of 302 having COMP_PWM].
Blanco fails to disclose the error detection circuitry comprising: resistor divider circuitry having a terminal; and the first terminal of the error amplifier coupled to the terminal of the resistor divider circuitry.
Wu [e.g. Fig. 1] teaches the error detection circuitry comprising: resistor divider circuitry [e.g. resistors directly connected to inverting input of 152] having a terminal [e.g. node between resistors]; and the first terminal of the error amplifier [e.g. inverting of 152] coupled to the terminal of the resistor divider circuitry.
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Blanco by the error detection circuitry comprising: resistor divider circuitry having a terminal; and the first terminal of the error amplifier coupled to the terminal of the resistor divider circuitry as taught by Wu in order of being able to reduce a voltage level of the output voltage, appropriate for a control circuitry.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
Claims 3 – 6 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 3 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further comprising first controller circuitry including: third current source circuitry having a terminal; a seventh transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the seventh transistor coupled to the terminal of the third current source circuitry, the control terminal of the seventh transistor coupled to the control terminal of the first transistor and the control terminal of the fourth transistor; and a resistor having a terminal coupled to the second terminal of the seventh transistor”.
The primary reason for the indication of the allowability of claim 4 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the second controller circuitry further including: a seventh transistor having a first terminal and a control terminal; and an eighth transistor having a control terminal coupled to the first terminal of the sixth transistor, the terminal of the second current source circuitry, the first terminal of the seventh transistor, and the control terminal of the seventh transistor”.
Claim(s) 5 – 6 are objected to as being dependent upon claim(s) 4.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Torres-Rivera whose telephone number is (571)272-5261. The examiner can normally be reached M-F 9:00-5:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838
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