DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/12/2026 has been entered.
Response to Amendment
The amendments filed 6/12/2026 have been accepted. Claims 1, 2, 4, 5, 7, 8, 10, 16, and 19-30 are still pending. Claims 1, 10, and 16 are amended. Claims 29 and 30 are new. Claims 11 and 15 have been canceled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 5, 7, 8, 10, 16, 19-22, and 25-29 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US PGPub 2024/0134568) in view of Ovsiannikov et al. (US PGPub 2019/0187983, hereafter referred to as Ovsiannikov) in view of Chang et al. (US PGPub 2016/0267011, hereafter referred to as Chang).
Regarding claim 1, Lee teaches a system comprising: a host that includes at least one core (Fig. 1 and Paragraph [0026], show the host which includes a controller. While not explicitly stated, as the host has a controller that will have some kind of processor, one or ordinary skill in the art would recognize that at least one core must be present), a memory device that includes a memory and a processing-in-memory component (Fig. 1 and Paragraphs [0031]-[0033], shows the FPGA in the memory that can act as an acceleratory (processing-in-memory component) and the NVM memory included in the memory device), a memory controller configured to: receive a command from the host, the command associated with at least one of a plurality of data elements (Paragraph [0034] and claim 19, states a storage controller can receive a command from a host. Paragraph [0058]-[0062] and [0110], the commands can be directed to data that is stored on the memory device), and responsive to the command including a request to perform one or more data operations, cause the processing-in-memory component of the memory device to execute one or more data operations (Paragraph [0043], states the FPGA can act as an accelerator and used to perform operations on the data based on the commands received from the host. Paragraphs [0080]-[0081], [0083] and [0087], shows this is done via a command queue after receiving a command from the host), and an interface for communicating data between the host and a memory (Fig. 1 and Paragraphs [0034] and [0036], shows the host interface 211 which is used to transfer data and commands between the memory and host). Lee does not teach a command including a request to perform one or more data casting operations causing execution of one or more data casting operations that adjust a bit size of the plurality of data elements to generate casted data elements, store the casted data elements in a register, and wherein the processing-in-memory component is configured to transmit a data response message back to the host once a threshold number of the casted data elements generated by the one or more data casting operations are stored in the register.
Ovsiannikov teaches receiving a command that causes execution of the one or more data casting operations that adjust a bit size of the plurality of data elements to generate casted data elements (Paragraph [0090], states that data casting can be performed on data elements. Paragraph [0092], states the host issue a start command to the memory controller which will begin the process), store the casted data elements generated by the one or more data casting operations in a register and transmit a data response message (Paragraph [0088], states that the processing elements include two output registers that are used to output the results of their operations meaning that after down casting input data they would be stored in the output registers and then transmitted to the next element in the system). Since both Lee and Ovsiannikov teach performing operations on data elements it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art elements according to known methods by modifying the teachings of Lee to perform the modifications to data of Ovsiannikov to obtain the predictable result of a command including a request to perform one or more data casting operations causing execution of one or more data casting operations that adjust a bit size of the plurality of data elements to generate casted data elements, store the casted data elements in a register and transmit a data response message back to the host (as all this does is specify that there is a specific command to request data casting and what operations are to be performed on the data). Lee and Ovsiannikov do not explicitly teach wherein the processing-in-memory component is configured to transmit a data response message back to the host once a threshold number of the casted data elements generated by the one or more data casting operations are stored in the register.
Chang teaches wherein the component is configured to transmit a data response message back to the host once a threshold number of data elements are stored in the register (Paragraph [0035], states a burst transfer can send data back to a host once the fullness of the buffer (register) reaches a certain threshold (threshold number of data elements is reached)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lee and Ovsiannikov to utilize the burst transfer method as taught in Chang so to reduce data access times (Chang, Paragraph [0002]).
Regarding claim 2, Lee, Ovsiannikov, and Chang teach all the limitations to claim 1. Lee further teaches wherein the interface is configured to transmit the data elements (Fig. 1 and Paragraphs [0034] and [0036], as stated in the rejection to claim 1). Ovsiannikov further teaches casted data elements (Paragraph [0090], as stated in the rejection to claim 1). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 4, Lee, Ovsiannikov, and Chang teach all the limitations to claim 1. Lee further teaches wherein the memory controller is configured to cause the processing-in-memory component of the memory to execute the data operations by transmitting a plurality of commands to the processing-in-memory component (Paragraph [0032]-[0033] and [0043], as stated in the rejection to claim 1, states the FPGA can act as an accelerator and used to perform operations on the data based on the commands received from the host). Ovsiannikov further teaches data casting operations (Paragraph [0090], as stated in the rejection to claim 1). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 5, Lee, Ovsiannikov, and Chang teach all the limitations to claim 4. Lee further teaches wherein the processing-in-memory component is configured to: receive the plurality of commands, each of the plurality of commands corresponding to at least one data element of the plurality of data elements (Paragraph [0032]-[0033] and [0043], as stated in the rejection to claim 4), perform an operation on at least one of the data elements, and transmit, over the interface, a data response including a plurality of data elements (Paragraph [0032]-[0033] and [0043], as stated in the rejection to claim 4, the FPGA can perform operations on the data elements. Fig. 5 and Paragraphs [0036], [0092], and [0102], data can be read out and sent to the host when that is requested). Ovsiannikov further teaches perform a downcast operation that reduces a bit size of the at least one data element to generate at least one downcast data element, and transmit, a data response including a plurality of downcast data elements as the casted data elements (Paragraphs [0088]-[0091], states the processing elements can perform operations and output data elements that were operated on. Those operations can be down casting). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 7, Lee, Ovsiannikov, and Chang teach all the limitations to claim 5. Lee further teaches wherein the memory controller is further configured to trigger transmission of the data response (Paragraphs [0035]-[0039], the storage controller controls the communications with the host so would ultimately by the one that triggers the data response). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 8, Lee, Ovsiannikov, and Chang teach all the limitations to claim 1. Lee further teaches wherein the memory controller is configured to cause the processing-in-memory component of the memory to execute the data operations by transmitting the command to the processing-in-memory component (Paragraph [0032]-[0033] and [0043], states the FPGA can act as an accelerator and used to perform operations on the data based on the commands received from the host. Paragraph [0083] and [0087], shows this is done via a command queue), wherein the processing-in-memory component is configured to: retrieve the plurality of data elements from the command and perform, for each of the plurality of data elements, an operation (Paragraph [0088], a buffer can be used to provide data to the accelerator so it can perform the necessary operations). Ovsiannikov further teaches data casting operations and perform, for each of the plurality of data elements, an upcast operation to generate a plurality of upcast data elements as the casted data elements (Paragraph [0090], both upcasting and downcasting of data elements can be performed when needed). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 10, claim 10 are the method claim associated with claim 1. Since Lee, Ovsiannikov, and Chang teach all the limitations of claim 1, they also teach all the limitations to claim 10; therefore the rejection to claim 1 also applies to claim 10.
Regarding claim 16, claim 16 is the method claim associated with claims 5. Since Lee, Ovsiannikov, and Chang teach all the limitations of claim 5, they also teach all the limitations to claim 16; therefore the rejection to claim 5 also applies to claim 16.
Regarding claim 19, Lee, Ovsiannikov, and Chang teach all the limitations to claim 16. Lee further teaches receiving an additional command including an additional plurality of data elements (Paragraphs [0010] and [0081], states that commands can be received for execution by the accelerator. Paragraph [0035], states write operations can be performed meaning commands can be received with data). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 20, Lee, Ovsiannikov, and Chang teach all the limitations to claim 19. Ovsiannikov further teaches performing, for each of the additional plurality of data elements, an upcast operation to generate a plurality of upcast data elements (Paragraph [0090], as stated in the rejection to claim 8, both upcasting and downcasting of data elements can be performed when needed). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 21, Lee, Ovsiannikov, and Chang teach all the limitations to claim 1. Lee further teaches wherein the memory device comprises a circuit board, and wherein the memory and the processing-in-memory component are mounted on the circuit board of the memory device (Fig. 1 and Paragraphs [0029] and [0168], states the storage device can include the cited components and that the components can be on printed circuit boards). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 22, Lee, Ovsiannikov, and Chang teach all the limitations to claim 1. Lee further teaches wherein the memory device is a dual in-line memory module (DIMM) that includes the processing-in-memory component (Fig. 18 and Paragraphs [0154]-[0155], states the storage device can be a DIMM). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 25, Lee, Ovsiannikov, and Chang teach all the limitations to claim 1. Lee further teaches wherein the processing-in-memory component comprises an accelerator (Paragraph [0032]-[0033] and [0043], as stated in the rejection to claim 1). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 26, Lee, Ovsiannikov, and Chang teach all the limitations to claim 1. Chang further teaches wherein the component is configured to transmit a single data response message back to the host once the threshold number of data elements are stored in the register (Paragraph [0032] and [0038], once a fullness threshold is filled a request is chosen to be sent back to the host). Lee further teaches the processing in-memory component (Fig. 1 and Paragraphs [0031]-[0033], as stated in the rejection to claim). Ovsiannikov further teaches cased data elements stored in the register (Paragraph [0088], as stated in the rejection to claim 1). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 27, Lee, Ovsiannikov, and Chang teach all the limitations to claim 26. Ovsiannikov further teaches wherein the single data response message includes the casted data elements stored in the register (Paragraph [0088] and [0092], as stated in the rejection to claim 1, the registers are meant to hold the casted data that is to be outputted meaning the response message would include the cased data elements). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 28, claim 28 is the method claim associated with claim 26. Since Lee, Ovsiannikov, and Chang teach all the limitations of claim 26, they also teach all the limitations to claim 28; therefore the rejection to claim 26 also applies to claim 28.
Regarding claim 29, Ovsiannikov, and Chang teach all the limitations to claim 26. Ovsiannikov further teaches a register full of the casted data elements generated by the one or more data casting operations (Paragraph [0088], as stated in the rejection to claim 1). Chang further teaches transmitting the data response message in response to the register being full of the data elements (Paragraph [0035], as stated in the rejection to claim 1). The combination of and reason for combining are the same as those given in claim 1.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, Ovsiannikov, and Chang and as applied to claim 1 above, and further in view of Lo et al. (US PGPub 2020/0264876, hereafter referred to as Lo).
Regarding claim 23, Lee, Ovsiannikov, and Chang teach all the limitations to claim 1. Lee, Ovsiannikov, and Chang do not explicitly teach wherein the memory device comprises a single integrated circuit device that incorporates the memory and the processing- in-memory component on a single chip.
Lo teaches wherein the memory device comprises a single integrated circuit device that incorporates the memory and the processing- in-memory component on a single chip (Paragraph [0212], states the bulk memory and hardware accelerator can be on the same integrated circuit). Since both Lee/Ovsiannikov/Chang and Lo teach a memory device with a memory and hardware accelerator it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the configuration of the memory and accelerator of Lee, Ovsiannikov, and Chang with that of Lo to obtain the predictable result of wherein the memory device comprises a single integrated circuit device that incorporates the memory and the processing- in-memory component on a single chip (as all this does is specify how the components are arranged and does not change their function or the operations of the system).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, Ovsiannikov, and Chang as applied to claim 1 above, and further in view of Farooq et al. (US PGPub 2022/0359482, hereafter referred to as Farooq).
Regarding claim 24, Lee, Ovsiannikov, and Chang teach all the limitations to claim 1. Lee, Ovsiannikov, and Chang do not explicitly teach wherein the memory device includes multiple chips that implement the memory and the processing-in-memory component that are vertically stacked together.
Farooq teaches wherein the memory device includes multiple chips that implement the memory and the processing-in-memory component that are vertically stacked together (Paragraph [0017] and [0021], states that there can be a vertical stack of chips that has an accelerator on one chip and memory on another chip). Since both Lee/Ovsiannikov/Chang and Farooq teach a memory device with a memory and hardware accelerator it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the configuration of the memory and accelerator of Lee, Ovsiannikov, and Chang with that of Farooq to obtain the predictable result of wherein the memory device includes multiple chips that implement the memory and the processing-in-memory component that are vertically stacked together (as all this does is specify how the components are arranged and does not change their function or the operations of the system).
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, Ovsiannikov, and Chang as applied to claim 1 above, and further in view of Mascaro et al. (US PGPub 2017/0315791, hereafter referred to as Mascaro).
Regarding claim 30, Lee, Ovsiannikov, and Chang teach all the limitations to claim 1. Lee, Ovsiannikov, and Chang do not explicitly teach wherein the processing-in-memory component performs the data casting operations to reduce bandwidth utilization by transmitting the casted data elements having a reduced bit size over the interface.
Mascaro teaches wherein the processing-in-memory component performs the data casting operations to reduce bandwidth utilization by transmitting the casted data elements having a reduced bit size over the interface (Paragraph [0014], states that one of the purposes of the application is to reduce bandwidth utilization. Paragraph [0056], states one of the transformations that can be done is casting). Since both Lee/Ovsiannikov/Chang and Mascaro teach data casting it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art references according to known methods by modifying the teachings of Lee, Ovsiannikov, and Chang to utilize the various transformations as taught in Mascaro to obtain the predictable result of wherein the processing-in-memory component performs the data casting operations to reduce bandwidth utilization by transmitting the casted data elements having a reduced bit size over the interface (as this is merely intended use).
Response to Arguments
Applicant's arguments filed 6/12/2026 have been fully considered but they are not persuasive. The applicant argues that the references do not teach the amended limitations of the independent claims. The examiner respectfully disagrees. It is the combination of references that teach the limitations. Chang specifically is relied upon to teach using a fullness of a buffer/register to determine when to send the response to the host. Ovsiannikov is relied upon to teach a register with casted data elements generated from casting operations. The combination of the two references do teach the limitations of the independent claims and the rejections still hold.
Conclusion
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/NICHOLAS A. PAPERNO/Examiner, Art Unit 2132
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