Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. DETAILED ACTION 1. The application of Rosenbluth et al. for the " CHIP-TO-CHIP BANDWIDTH OPTIMIZATION " filed 09/29/2023 has been examined. Claims 1-24 are pending in the present application. 2. The applicant should use this period for response to thoroughly and very closely proof read and review the whole of the application for correct correlation between reference numerals in the textual portion of the Specification and Drawings along with any minor spelling errors, general typographical errors, accuracy, assurance of proper use for Trademarks TM , and other legal symbols @, where required, and clarity of meaning in the Specification, Drawings, and specifically the claims (i.e., provide proper antecedent basis for “the'' and “said'' within each claim). Minor typographical errors could render a Patent unenforceable and so the applicant is strongly encouraged to aid in this endeavor. Claim Rejections - 35 USC § 103 3 . The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed Invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining ob viousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . 4 . This application currently names joint inventors. In considering patentability of the claims under 35 U.S.C. 103, the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of 35 U.S.C. 103 and potential 35 U.S.C. 102(e), (f) or (g) prior art under 35 U.S.C. 103. 5 . Claims 1-3, 5-12, 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chaudhary et al. (US#2025/0 061078 ) in view of S uthar et al. (US# 202 3/0412712 ) . Regarding claim 1 , the re ferences disclose a system and method for communicating between two or more devices in a processor , according to the essential features of the claim. Chaudhary et al. (US#2025/0061078) discloses a transceiver for sending and receiving data packets on a communication channel ( see Fig s . 1A -C for processing an eviction request using chip-to-chip communications ) , the transceiver is to perform operations comprising: receiving a first request packet comprising a plurality of information fields , the plurality of information fields comprising a first type of operation to be performed on a memory device and a first address in the memory device ( F ig. 2; para [ 0025 ] , [0032]-[0041]: The eviction request and the read request are transmitted using an ordered communication network, which ensures the communications are received and/or processed by the other chip in an order that maintains memory coherency ) ; storing the first type of operation and the first address in a memory associated with the transceiver; sending, to a target device, the first request packet with the first address ( para [0018]-[0020] ) ; receiving a second request packet comprising a second address in the memory device ( Fig. 5; p ara [0004]-[0005], [0018]-[0020]: when an interconnect bridge of a chip has received an eviction request from a client of the chip, the interconnect bridge may transmit, C2C, a read request (or snoop response) corresponding to the same portion of memory without waiting for an inter-chip completion response for the eviction request ) . However, Chaudhary reference does not disclose expressly wherein determining, based at least in part on the first type of operation, the first address, and the second address, that the second request packet is part of a sequence of request packets to the target device , and eliminating, in a header of the second request packet, a portion of the second address to form a third request packet; and sending the third request packet to the target device . In the same field of endeavor, Suthar et al. (US# 2023/0412712 ) teaches i n Figs. 1-4 the architectures of a computing network with optimized packet headers , in which packet header optimization according both option A and option B is based on recognition that, if elements in the network path are capable of routing based on IP addresses alone, then MAC addresses used in conventional packet headers are redundant and can be eliminated and only IP addresses are used to identify a source network device and a destination network device. Further in contrast to such conventional implementations, packet header optimization according both option A and option B is based on recognition that the complete IP addresses of the source and destination network devices may be shortened and that some other fields used in conventional packet headers may be either shortened or eliminated ( Fig. 4; para [0015], [0047]-[0051]: transmitter may eliminate a portion of the address or the entire address, and only transmit a portion of the address to the receiver. This way, the redundant or low-value fields may be eliminated, and the bandwidth of the I / O link can be saved for other communications ) . One skilled in the art would have recognized the need for effectively and efficiently communicating between two or more devices in a processor , and would have applied Suthar’s optimized packet headers for Ethernet IP networks into Chaudhary ’s techniques for communicate over chip-to-chip (C2C) while maintaining memory coherency . Therefore, It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to apply Suthar ’s packet header optimization in ethernet IP networks into Chaudhary ’s efficient chip-to-chip communications with the motivation being to provide a method and system for chip-to-chip bandwidth optimization. Regarding claim 2, the reference further teaches wherein comparing the first type of operation of the first request packet to a second type of operation of the second request packet, wherein the first request packet precedes the second request packet; and determining a match between the first type of operation of the first request packet and the second type of operation of the second request packet ( Chaudhary et al.: Fig. 1A-C; p ara [0004]-[0005], [00 30 ] : the routing of transactions between the agents 112A and 112B based at least on examining transaction attributes, such as the transaction type, source and destination IDs, and corresponding coherence information ). Regarding claim 3, the reference further teaches wherein comparing the first address in the first request packet to the second address in the second request packet, wherein the first request packet precedes the second request packet; and determining the first address and the second address are in a sequence of addresses ( Chaudhary et al.: para [0025]: the sequence numbers may be used to reconstruct the order in which the messages are to be processed and/or were transmitted ). Regarding claim 5, the reference further teaches wherein the communication channel comprises at least one of a bus, a switch, a network, a crossbar, a daisy chain, or an interconnect fabric ( Chaudhary et al.: Fig. 1A; para [002 7 ]: communication channel 102 using one or more C2C communications protocols, include Advanced Microcontroller Bus ). Regarding claim 6, the reference further teaches wherein receiving a response packet in response to the third request packet; and matching, based on a tag field in the response packet, the response packet with the third request packet ( Chaudhary et al.: Fig. 1A; para [00 04 ] -[ 0005]: the interconnect bridge may transmit a C2C message corresponding to the same portion of memory (e.g., a read request, a snoop response, etc. ). Regarding claim 7, the reference further teaches wherein the first type of operation comprises at least one of a read operation, a write operation, or a scan operation ( Chaudhary et al.: Fig. 1A, 3A; para [00 3 4 ] , [0056] : the inter-chip read request 128 , and for transmitting write data with a copy back request using C2C communications ). Regarding claim 8, the reference further teaches wherein the storing further comprises storing the first type of operation and the first address in a data structure in a content addressable memory (CAM) associated with the transceiver ( Suthar et al.: Fig. 4; para [ 0049]: The packet processing pipelines 430 can be configured to perform match-action on received packets to identify packet processing rules and next hops using information stored in a TCAM table 440 ). Regarding claim 9, the reference further teaches wherein indexing the first type of operation in the data structure using a unique process identification (ID )( Suthar et al.: Fig. 5 ; para [00 52 ] : using two (or more) subsets 504 for indexing in the lookup table 506 may help optimizing the size of the lookup table 506 , and generate the ID 510 ). Regarding claims 10-12, 14-17, they are method claims corresponding to the apparatus claim s 1-3, 5-9 examined above. Therefore, claims 10-12, 14-17 are analyzed and rejected as previously discussed in paragraph above with respect to claim s 1-3, 5-9. Claim Rejections - 35 USC § 102 6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless — (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sate. or otherwise available to the public before the effective filing date of the claimed invention 7. Claim(s) 18, 20-24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chaudhary et al. (US#2025/0061078) . As to claim 18, the re ferences disclose a system and method for communicating between two or more devices in a processor , according to the essential features of the claim. Chaudhary et al. (US#2025/0061078) discloses a transceiver for sending and receiving data packets on a communication channel ( see Fig s . 1A -C for processing an eviction request using chip-to-chip communications ) , the transceiver configured to : receiving a first request packet comprising a plurality of information fields, the plurality of information fields comprising a first type of operation to be performed on a memory device and a first address in the memory device (F ig. 2; para [0025] , [0032]-[0041]: The eviction request and the read request are transmitted using an ordered communication network, which ensures the communications are received and/or processed by the other chip in an order that maintains memory coherency ) ; storing the first type of operation and the first address in a memory associated with the transceiver; receiving a second request packet comprising a first portion of the second address (p ara [0004]-[0005], [0018]-[0020]: when an interconnect bridge of a chip has received an eviction request from a client of the chip, the interconnect bridge may transmit, C2C, a read request (or snoop response) corresponding to the same portion of memory without waiting for an inter-chip completion response for the eviction request ) ; determining, based on the first type of operation, and the first portion of the second address, a second portion of the address . Thus, (Fig. 5, para [0018] -[ 0020] , [0069]-[0072] : processing a request to relinquish ownership of a portion of memory using an ordered communication network . Thus, minimize the amount of overhead associated with signaling and data transfer, as well as to optimize the use of available IO bandwidth of C2C communications ). As to claim 20 , Chaudhary further teaches wherein the communication channel comprises at least one of a bus, a switch, a network, a crossbar, a daisy chain, or an interconnect fabric ( Chaudhary et al.: Fig. 1A; para [002 7 ]: communication channel 102 using one or more C2C communications protocols, include Advanced Microcontroller Bus ). As to claim 21 , Chaudhary further teaches wherein generating, in response to the second request packet and based on a tag field in the second request packet, a response packet; and sending the response packet to a source device ( Chaudhary et al.: Fig. 1A; para [00 04 ] -[ 0005]: the interconnect bridge may transmit a C2C message corresponding to the same portion of memory (e.g., a read request, a snoop response, etc ). As to claim 22 , Chaudhary further teaches wherein the first type of operation comprises at least one of a read operation, a write operation, or a scan operation ( Chaudhary et al.: Fig. 1A, 3A; para [00 34 ] , [0056]: the inter-chip read request 128 , and for transmitting write data with a copy back request using C2C communications ). As to claim 23, Chaudhary further teaches wherein the storing further comprises storing the first type of operation and the first address in a data structure in a cache memory associated with the transceiver ( Chaudhary et al.: Fig. 2; para [0018] -[ 0020], [0048]-[0049]: processing a memory access with ownership permissions update request using C2C communications ). As to claim 24, Chaudhary further teaches wherein indexing the first type of operation in the data structure using a unique process identification (ID )( Chaudhary et al. ; Fig. 3A; para [0020], [0057]: database identifier response is received from the other chip to send out the copy back write data ). Allowable Subject Matter 8 . Claim s 4, 13, 19 are objected to as being dependent upon a rejected base claims , but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 9 . The following is an examiner's statement of reasons for the indication of allowable subject matter: The closest prior art of record fails to disc lose or suggest wherein determining, based on the first address and the second address, a size of operation of the first type of operation; determining, based on the size of operation, a third address for the first type of operation and storing the third address in the memory associated with the transceiver; receiving a fourth request packet comprising the third address; eliminating, in a header of the fourth request packet, the third address to form a fifth request packet; and sending the fifth request packet to the target device , as specifically recited in the claims. Conclusion 1 0 . The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The Kushnir et al. (US# 12,489,085 ) is cited to show C2C yield and performance optimization in a die stacking platform . The Jeong et al. (US# 202 4/0242014 ) shows methods and systems for designing integrated circuits . The Khare et al. (US# 9,992,135 ) shows apparatus and method for fusion of compute and switching functions of exascale system into a single component by using configurable network-on-chip fabric with distributed dual mode I/O ports and programmable network interfaces . The Schulz et al. (US# 202 1/0109883 ) interface bridge between integrated circuits die . The Krick et al. (US# 20 02/0169935 ) shows system of and method for memory arbitration using multiple queues . The Whetsel (US# 11,333,703 ) shows interposer instrumentation method and apparatus . The Rowley et al. (US# 11,637,903 ) shows memory device with a multi-mode communication mechanism . The Roozbeh et al. (US# 2023/0421473 ) shows method and system for efficient I/O transfer in network devices . The Roozbeh et al. (US# 12,425,351 ) shows method and system for efficient I/O transfer in network devices . The Goren (US# 2017/0177476 ) shows system and method for automated data organization in a storage system . The Gray (US# 11,677,662 ) shows FPGA-efficient directional two dimensional router . 1 1 . Applicant's future amendments need to comply with the requirements of MPEP § 714.02, MPEP § 2163.04 and MPEP § 2163.06. " with respect to newly added or amended claims, applicant should show support in the original disclosure for the new or amended claims." See MPEP § 714.02 and § 2163.06 ("Applicant should * * * specifically point out the support for any amendments made to the disclosure."); and MPEP § 2163.04 ("If applicant amends the claims and points out where and/or how the originally filed disclosure supports the amendment(s), and the examiner finds that the disclosure does not reasonably convey that the inventor had possession of the subject matter of the amendment at the time of the filing of the application, the examiner has the initial burden of presenting evidence or reasoning to explain why persons skilled in the art would not recognize in the disclosure a description of the invention defined by the claims."). See In re Smith, 458 F.2d 1389, 1395, 173 USPQ 679, 683 (CCPA 1972) In re Wertheim, 541 F.2d at 262,191 USPQ at 96 (emphasis added). "The use of a confusing variety of terms for the same thing should not be permitted. New claims and amendments to the claims already in the application should be scrutinized not only for new matter but also for new terminology. While an applicant is not limited to the nomenclature used in the application as filed, he or she should make appropriate amendment of the specification whenever this nomenclature is departed from by amendment of the claims so as to have clear support or antecedent basis in the specification for the new terms appearing in the claims. This is necessary in order to insure certainty in construing the claims in the light of the specification." Ex parte Kotler, 1901 C.D. 62, 95 O.G. 2684 (Comm'r Pat. 1901). See 37 CFR 1.75, MPEP § 608.01 ( i ) and § 1302.01. Note that examiners should ensure that the terms and phrases used in claims presented late in prosecution of the application (including claims amended via an examiner's amendment) find clear support or antecedent basis in the description so that the meaning of the terms in the claims may be ascertainable by reference to the description, see 37 CFR 1,75(d )( 1 ). If the examiner determines that the claims presented late in prosecution do not comply with 37 CFR 1.75(d)(1), applicant will be required to make appropriate amendment to the description to provide clear support or antecedent basis for the terms appearing in the claims provided no new matter is introduced." "USPTO personnel are to give claims their broadest reasonable interpretation in light of the supporting disclosure." In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). MPEP § 2106. " 1 2 . Any inquiry concerning this communication or earlier communications from the examiner should be directed to M. Phan whose telephone number is (571) 272-3149. The examiner can normally be reached on Mon - Fri from 6:00 to 3:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Chirag Shah , can be reached on (571) 272-3 144 . The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571) 272-2600. 1 3 . Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov . Should you have any questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at toll free 1-866-217-9197. Mphan 12/ 10 /2025 /MAN U PHAN/ Primary Examiner, Art Unit 2477