CTNF 18/375,381 CTNF 83270 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Status of the Application This Office Action is in response to Applicant’s Application filed on 9/29/2023. Claims 1-27 are pending for this examination. Information Disclosure Statement The information disclosure statements (IDSs) submitted on 5/07/2024; and 8/19/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Claim Rejections - 35 U.S.C. § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-2, 10-11, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zimmer (US 2005/0114639), herein referred to as Zimmer ‘639, in view of Sutton, II et al. (US 2003/0229794), herein referred to as Sutton ‘794 . Referring to claim 1, Zimmer ‘639 teaches a processor (see Fig. 1, CPU 150) comprising: a plurality of cores (see Paragraph 0033, wherein the system can exist in a multiprocessor environment, i.e. an environment with a plurality of processor cores), at least a first core of the plurality of cores (see Paragraph 0034, where in a multiprocessor system environment, all processors are synchronized 206 whereby all but a selected processor (the first processor identified by the pre-boot process) are halted while the SMM Nub in the selected processor is executed) to perform operations to cause the plurality of cores to enter into a system management mode (SMM) (see Paragraph 0034, where the CPU 150 switches to an SMM mode and redirects the instruction pointer to the first instruction in SMM Nub 124), the operations comprising: allocating a memory region for a system management RAM (SMRAM) (see Fig 1, SMRAM 126 with SMM Nub 124; see Paragraph 0023, wherein conventional SMM implementations the SMM space is locked by the platform software/firmware/BIOS before handing off control; also see Paragraph 0029, where SMM Nub 124 is loaded into SMRAM 126 during the installation of the (extensible firmware interface (EFI) SMM base protocol driver, where SMM Nub 124 is responsible for coordinating all activities while control is transfer to SMM including memory allocation services 132); writing an SMRAM state save location (see Fig. 2, step 208, where a save machine state of each CPU is saved by both CPU hardware and SMM Nub 124, see Paragraph 0034); and generating a page table (see Fig. 2, setup page table to map SMRAM 216; see Paragraph 0036 and 0054) in the SMRAM (see Fig. 6, memory paging map 602 with page table 613 located in SMRAM 126), including mapping a virtual address space to a physical address space (see Paragraph 0066, where the global descriptor table (GDT) and page table are set to have a 1:1 Mapping between virtual and physical addresses). However, Zimmer ‘639 does not specifically teach the writing an SMRAM state save location to a first register . Sutton ‘794 teaches a microprocessor system implementing system management code during secure operations (see Abstract), where the each processor has its own dedicated SMRAM space (see Paragraph 0021) and the processors’ system management base (SMBASE – acronym defined in Paragraph 0018) register content PSMBASE (SMBASE register in the processor – acronym defined in Paragraph 0018) may define code-entry points and state save locations within SMRAM (see Paragraph 0021), i.e. the processor’s register defines state save locations within SMRAM. Zimmer ‘639 and Sutton ‘794 apply as analogous prior arts as both pertain to the same field of endeavor of implement SMM for processors. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zimmer ‘639 system as set forth above to have state save locations stored in a register such as a processor register, as taught by Sutton ‘794, as a person of ordinary skill in the art would be motivated to store state variables / data in a register as this would maximize performance by minimizing the cycles / time the CPU would spend waiting on state data where registers are the fastest form of storage in usually located directly within the CPU. As to claim 2, Zimmer ‘639 teaches the processor of claim 1 wherein the operations further comprise: allocating memory from the memory region for an SMM descriptor (see Fig. 2, switch GDT for 32-bit mode 210 and switch to a 64-bit mode 220; see Paragraphs 0035-0036, where the global descriptor table is switched to a 32-bit linear addressing mode and processor mode switched to 32-bit legacy mode for supporting legacy handlers, and then setting up a 64-bit support and executing 64-bit handlers for 64-bit global descriptor table; Examiner points out that global descriptors being used for instructions to be executed while the processors are in system management mode would be SMM descriptors as the operations executed in SMM would be SMM operations). Referring to claim 10, Zimmer ‘639 teaches a method (see Abstract) comprising: performing operations (see Paragraph 0020) on a first core (see Paragraph 0034, where in a multiprocessor system environment, all processors are synchronized 206 whereby all but a selected processor (the first processor identified by the pre-boot process) are halted while the SMM Nub in the selected processor is executed) of a plurality of cores (see Paragraph 0033, wherein the system can exist in a multiprocessor environment, i.e. an environment with a plurality of processor cores) to cause the plurality of cores to enter into a system management mode (SMM) (see Paragraph 0034, where the CPU 150 switches to an SMM mode and redirects the instruction pointer to the first instruction in SMM Nub 124), the operations comprising: allocating a memory region for a system management RAM (SMRAM) (see Fig 1, SMRAM 126 with SMM Nub 124; see Paragraph 0023, wherein conventional SMM implementations the SMM space is locked by the platform software/firmware/BIOS before handing off control; also see Paragraph 0029, where SMM Nub 124 is loaded into SMRAM 126 during the installation of the (extensible firmware interface (EFI) SMM base protocol driver, where SMM Nub 124 is responsible for coordinating all activities while control is transfer to SMM including memory allocation services 132); writing an SMRAM state save location (see Fig. 2, step 208, where a save machine state of each CPU is saved by both CPU hardware and SMM Nub 124, see Paragraph 0034); and generating a page table (see Fig. 2, setup page table to map SMRAM 216; see Paragraph 0036 and 0054) in the SMRAM (see Fig. 6, memory paging map 602 with page table 613 located in SMRAM 126), including mapping a virtual address space to a physical address space (see Paragraph 0066, where the global descriptor table (GDT) and page table are set to have a 1:1 Mapping between virtual and physical addresses). However, Zimmer ‘639 does not specifically teach the writing an SMRAM state save location to a first register ; and Sutton ‘794 teaches a microprocessor system implementing system management code during secure operations (see Abstract), where the each processor has its own dedicated SMRAM space (see Paragraph 0021) and the processors’ system management base (SMBASE – acronym defined in Paragraph 0018) register content PSMBASE (SMBASE register in the processor – acronym defined in Paragraph 0018) may define code-entry points and state save locations within SMRAM (see Paragraph 0021), i.e. the processor’s register defines state save locations within SMRAM. Zimmer ‘639 and Sutton ‘794 apply as analogous prior arts as both pertain to the same field of endeavor of implement SMM for processors._ Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zimmer ‘639 system as set forth above to have state save locations stored in a register such as a processor register, as taught by Sutton ‘794, as a person of ordinary skill in the art would be motivated to store state variables / data in a register as this would maximize performance by minimizing the cycles / time the CPU would spend waiting on state data where registers are the fastest form of storage in usually located directly within the CPU. As to claim 11, Zimmer ‘639 teaches the method of claim 10 further comprising: allocating memory from the memory region for an SMM descriptor (see Fig. 2, switch GDT for 32-bit mode 210 and switch to a 64-bit mode 220; see Paragraphs 0035-0036, where the global descriptor table is switched to a 32-bit linear addressing mode and processor mode switched to 32-bit legacy mode for supporting legacy handlers, and then setting up a 64-bit support and executing 64-bit handlers for 64-bit global descriptor table; Examiner points out that global descriptors being used for instructions to be executed while the processors are in system management mode would be SMM descriptors as the operations executed in SMM would be SMM operations). Referring to claim 19, Zimmer ‘639 teaches a machine-readable medium having program code stored thereon (see Paragraph 0090) which, when executed by a machine (see the system of Fig. 1), causes the machine to perform the operations of: performing operations (see Paragraph 0020) on a first core (see Paragraph 0034, where in a multiprocessor system environment, all processors are synchronized 206 whereby all but a selected processor (the first processor identified by the pre-boot process) are halted while the SMM Nub in the selected processor is executed) of a plurality of cores (see Paragraph 0033, wherein the system can exist in a multiprocessor environment, i.e. an environment with a plurality of processor cores) to cause the plurality of cores to enter into a system management mode (SMM) (see Paragraph 0034, where the CPU 150 switches to an SMM mode and redirects the instruction pointer to the first instruction in SMM Nub 124), the operations comprising: allocating a memory region for a system management RAM (SMRAM) (see Fig 1, SMRAM 126 with SMM Nub 124; see Paragraph 0023, wherein conventional SMM implementations the SMM space is locked by the platform software/firmware/BIOS before handing off control; also see Paragraph 0029, where SMM Nub 124 is loaded into SMRAM 126 during the installation of the (extensible firmware interface (EFI) SMM base protocol driver, where SMM Nub 124 is responsible for coordinating all activities while control is transfer to SMM including memory allocation services 132); writing an SMRAM state save location (see Fig. 2, step 208, where a save machine state of each CPU is saved by both CPU hardware and SMM Nub 124, see Paragraph 0034); and generating a page table (see Fig. 2, setup page table to map SMRAM 216; see Paragraph 0036 and 0054) in the SMRAM (see Fig. 6, memory paging map 602 with page table 613 located in SMRAM 126), including mapping a virtual address space to a physical address space (see Paragraph 0066, where the global descriptor table (GDT) and page table are set to have a 1:1 Mapping between virtual and physical addresses). However, Zimmer ‘639 does not specifically teach the writing an SMRAM state save location to a first register . Sutton ‘794 teaches a microprocessor system implementing system management code during secure operations (see Abstract), where the each processor has its own dedicated SMRAM space (see Paragraph 0021) and the processors’ system management base (SMBASE – acronym defined in Paragraph 0018) register content PSMBASE (SMBASE register in the processor – acronym defined in Paragraph 0018) may define code-entry points and state save locations within SMRAM (see Paragraph 0021), i.e. the processor’s register defines state save locations within SMRAM. Zimmer ‘639 and Sutton ‘794 apply as analogous prior arts as both pertain to the same field of endeavor of implement SMM for processors._ Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zimmer ‘639 system as set forth above to have state save locations stored in a register such as a processor register, as taught by Sutton ‘794, as a person of ordinary skill in the art would be motivated to store state variables / data in a register as this would maximize performance by minimizing the cycles / time the CPU would spend waiting on state data where registers are the fastest form of storage in usually located directly within the CPU. As to claim 20, Zimmer ‘639 teaches the machine-readable medium of claim 19 further comprising program code to cause the first core to perform the operations of: allocating memory from the memory region for an SMM descriptor (see Fig. 2, switch GDT for 32-bit mode 210 and switch to a 64-bit mode 220; see Paragraphs 0035-0036, where the global descriptor table is switched to a 32-bit linear addressing mode and processor mode switched to 32-bit legacy mode for supporting legacy handlers, and then setting up a 64-bit support and executing 64-bit handlers for 64-bit global descriptor table; Examiner points out that global descriptors being used for instructions to be executed while the processors are in system management mode would be SMM descriptors as the operations executed in SMM would be SMM operations) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 3-9, 12-18, and 21-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. As to claims 3, 12, and 21, Examiner finds that prior art does not specifically teach the operations further comprise: storing a pointer to the SMM descriptor in at least one of the first register and a second register . More specifically, Examiner finds prior arts teach the storing of pointers to descriptors in registers, but not specifically a singular pointer to the SMM descriptor being stored in a first and second register. As to claims 4, 13 and 22, Examiner finds that prior art does not specifically teach the operations further comprise: populating the SMM descriptor with a plurality of values to be used to initialize a corresponding plurality of control registers on each core of the plurality of cores . More specifically, Examiner points out that a descriptor by definition is a data structure providing detailed information about an operation/instruction used to identify and manage the operation/instruction and as such would including values used to indicate location and provide corresponding control registers with the information needed initialize execution of the operation/instruction. However Examiner does not specifically find the SMM descriptor initializing a plurality of control register on each cores of the plurality of cores in context of the preceding claim limitations of the claimed invention. Relevant Prior Art 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Nguyen et al. (US 2002/0099893) teaches a multiprocessor system implementing SMM where a SMI is issued to the system processors to get the processor to enter system management mode and where registers at each processor are saved to SMRAM memory. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL SUN whose telephone number is (571)270-1724. The examiner can normally be reached Monday-Friday 8am-4pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL SUN/Primary Examiner, Art Unit 2183 Application/Control Number: 18/375,381 Page 2 Art Unit: 2183 Application/Control Number: 18/375,381 Page 3 Art Unit: 2183 Application/Control Number: 18/375,381 Page 4 Art Unit: 2183 Application/Control Number: 18/375,381 Page 5 Art Unit: 2183 Application/Control Number: 18/375,381 Page 6 Art Unit: 2183 Application/Control Number: 18/375,381 Page 7 Art Unit: 2183 Application/Control Number: 18/375,381 Page 8 Art Unit: 2183 Application/Control Number: 18/375,381 Page 9 Art Unit: 2183 Application/Control Number: 18/375,381 Page 10 Art Unit: 2183
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