DETAILED ACTION
This office action is in response to Application No. 18/375,419, filed on 29 September 2023. Claims 1-21 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 15-21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claims are directed to machine-readable media, which includes non-statutory transitory media, such as signals. In re Nuijten, 84 U.S.P.Q.2d 1495.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 6-8, 11, 13-15, 18, 20, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marchya (US 2017/0338661) in view of Burnes (“GeForce GTX 1080 Now Available. Learn More In This Deep Dive”).
Regarding claim 1, Marchya discloses a processor, comprising: a plurality of intellectual property (IP) circuit blocks including a first type of IP circuit block and at least a second type of IP circuit blocks (Figs. 1 and 6, blocks 230-250, 630, 640); and power management circuitry to perform operations to determine voltages and frequencies at which to operate the plurality of IP circuit blocks (Figs. 1 and 6, blocks 210/610, 220/620), the operations including: determining a plurality of voltage/frequency combinations for the first type of IP circuit block based on stored voltage/frequency curve data (Figs. 1A/B; ¶30); determining maximum frequency values for the second type of IP circuit blocks corresponding to one or more of the plurality of voltage/frequency combinations, the maximum frequency values based on the stored voltage/frequency curve data (¶33); and causing the first type of IP circuit blocks to operate at one of the plurality of voltage/frequency combinations and responsively causing one or more of the second type of IP circuit blocks to operate at a corresponding final maximum frequency value (¶¶30, 33).
Marchya does not appear to explicitly disclose adjusting one or more of the maximum frequency values based on one or more corresponding stored scalar values to determine final maximum frequency values for each of the second type of IP circuit blocks; Burnes discloses these limitations (p. 13, ¶2; p. 14, Fig. 1). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Marchya and Burnes, because doing so would have involved merely the routine combination of known elements according to known techniques, or the routine use of a known technique to improve similar devices in the same way, to produce merely the predictable results of adjusting maximum frequency (Fmax) to actual values determined through testing. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395-1396. Marchya discloses setting frequencies based on voltage-frequency (VF) curves. Burnes teaches testing for actual operating Fmax at a given voltage, and adjusting VF curves according to the tests. The teachings of Burnes are directly applicable to Marchya in the same way, so that chips can be operated at frequencies that reflect their actual tested capability.
Regarding claim 4, Marchya discloses that causing the first type of IP circuit block to operate at one of the plurality of voltage/frequency combinations further comprises transmitting a control message to one or more local power manager circuits associated with the first type of IP circuit block, the one or more local power manager circuits to cause the first type of IP circuit block to operate at one of the plurality of voltage/frequency combinations (¶41).
Regarding claim 6, Marchya discloses one or more additional types of IP circuit blocks (Figs. 1 and 6, blocks 230-250, 630, 640), wherein the power management circuitry is to perform additional operations to determine voltages and frequencies at which to operate the one or more additional types of IP circuit blocks (Figs. 1 and 6, blocks 210/610, 220/620), the additional operations including: determining additional maximum frequency values for the one or more additional types of IP circuit blocks corresponding to the plurality of voltage/frequency combinations, the additional maximum frequency values based on the stored voltage/frequency curve data (Figs. 1A/B; ¶¶32, 33, 77); and causing the one or more additional types of IP circuit blocks to operate at one of the additional final maximum frequency values corresponding to the one of the plurality of voltage/frequency combinations at which the first type of IP circuit blocks are to operate (¶¶32, 33, 77).
Marchya does not appear to explicitly disclose adjusting one or more of the additional maximum frequency values based on one or more corresponding stored scalar values to determine additional final maximum frequency values; Burnes discloses these limitations (p. 13, ¶2; p. 14, Fig. 1). Motivation to combine remains consistent with claim 1.
In particular, the claim duplicates the limitations of claim 1 for additional IP blocks, and Marchya is explicitly applicable to arbitrary IP block types and numbers of IP blocks. Furthermore, duplication of parts is likely to be obvious. See MPEP § 2144.04(VI)(B).
Regarding claim 7, Marchya discloses that the power management circuity is to control an external voltage regulator to supply a voltage to the plurality of different types of IP circuit blocks in accordance with the one of the plurality of voltage/frequency combinations at which the first type of IP circuit blocks are to operate (Figs. 1 and 6, blocks 220/620 controlling 210/610; ¶41).
Claims 8, 11, 13, and 14 are directed to the methods performed by the processor of claims 1, 4, 6, and 7, and are rejected under the same reasoning.
Claims 15, 18, 20, and 21 are directed to machine-readable media for performing the operations of the processor of claims 1, 4, 6, and 7, and are rejected under the same reasoning. Marchya similarly discloses a machine-readable media for performing the claimed operations (¶48).
Claim(s) 2, 9, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marchya in view of Burnes and Bouvier (“Delivering a new level of visual performance in an SoC”).
Regarding claims 2, 9, and 16, Marchya discloses that the first type of IP circuit block comprises an IP block including performance cores and wherein the second type of IP circuit blocks comprise at least one of: efficiency cores, graphics processing cores, interconnect circuitry, memory controllers, and input-output controllers (Fig. 2). If Marchya is found to be unclear regarding these limitations, Bouvier discloses the same (slide 6, high-performance Zen core; slide 16, Zen cores and graphics cores). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Marchya, Burnes, and Bouvier, because doing so would have involved merely the routine combination of known elements according to known techniques, or the routine use of a known technique to improve similar devices in the same way, to produce merely the predictable results of frequency scaling SoCs with processor and graphics cores. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395-1396. Marchya teaches frequency scaling of different types of cores in a processing system. Bouvier provides an explicit example of a processing system having CPU and GPU cores. The teachings of Bouvier are directly applicable to Marchya in the same way, so that Marchya would similarly use frequency scaling in a processing system having CPU and GPU cores to operate the CPU and GPU cores at appropriate frequencies according to their voltages.
Claim(s) 3, 10, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marchya in view of Burnes and Girson (US 7,111,179).
Regarding claims 3, 10, and 17, Marchya discloses that adjusting one or more of the maximum frequency values further comprises multiplying one or more of the maximum frequency values by the corresponding stored scalar values to generate the final maximum frequency values. However, Burnes discloses that adjusting one or more of the maximum frequency values further comprises offsetting one or more of the maximum frequency values by the corresponding stored scalar values to generate the final maximum frequency values (p. 13, ¶2; p. 14, Fig. 1). Persons having ordinary skill in the art would recognize that multiplying the frequency by a scalar value is a known way of applying the offset, as taught by Girson (col. 13, lines 2-6). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Marchya, Burnes, and Girson, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of adjusting frequency to test-verified frequencies through known multiplication. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Marchya teaches frequency scaling. Burnes teaches that frequency scaling should use adjusted frequency offsets determined through testing. Persons having ordinary skill in the art would recognize that offsetting a frequency can be done through multiplication, as taught by Girson. The teachings of Burnes and Girson are directly applicable to Marchya in the same way, so that Marchya would scale frequencies using an adjusted frequency multiplier determined through testing.
Claim(s) 5, 12, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marchya in view of Burnes, Zak (“How to use MSI Afterburner”), and von Kaenel (US 2016/0072505).
Regarding claims 5, 12, and 19, Marchya does not appear to explicitly disclose that the scalar values comprise predetermined values determined by post silicon tuning and stored in a non-volatile memory; Burnes discloses these limitations (p. 13, ¶2; p. 14, Fig. 1, ‘Profiles’). If Burnes is found to be unclear regarding storage in non-volatile memory, Zak (p. 6, ¶3; p. 10, last par. to p. 11, first par., saving curve to profile) and von Kaenel (¶33) disclose the same. It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Marchya, Burnes, Zak, and von Kaenel, because doing so would have involved merely the routine combination of known elements according to known techniques, or the routine use of a known technique to improve similar devices in the same way, to produce merely the predictable results of storing tested VF curves for later use. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395-1396. Marchya discloses frequency scaling based on VF curves. Burnes teaches adjusting VF curves based on tests; anyone with any familiarity of the type of software disclosed in Burnes would recognize that Burnes’s illustrated ‘profile’ buttons are for saving test-determined VF curves in non-volatile memory so that the curves can be used in later operation. Zak and von Kaenel provide further explicit disclosure of saving post-silicon-tuned curves in non-volatile memory. The teachings of Burnes, Zak, and von Kaenel are directly applicable to Marchya in the same way, so that Marchya would perform frequency scaling based on test-determined adjusted VF curves that are stored in non-volatile memory so that they can be used in later operation.
Conclusion
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16 September 2026
/ARIC LIN/ Examiner, Art Unit 2851
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