DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/22/26 has been entered.
1. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Davis (US 20160041887) in view of Jalal (US 20170168939).
With respect to claim 1, the Davis reference teaches an apparatus comprising:
a storage node (see fig. 3, storage node 152) comprising:
a first interface (see fig. 4, where NVRAM 204 is connected to the communication interconnect 170) to communicate with a first memory medium that stores a first object corresponding to a cache copy of the data in a portion of the first memory medium; (e.g. fig. 3, NVRAM 204; and paragraph 37, where each non-volatile solid-state storage 152 has a relatively fast non-volatile solid-state memory, such as non-volatile random access memory (NVRAM) 204; and NVRAM 204 is implemented in one embodiment as high speed volatile memory, such as dynamic random access memory (DRAM) 216, backed up by energy reserve 218 [i.e. a ‘cache’]; and paragraph 27, where in UNIX-style file systems, data is handled with an index node or inode, which specifies a data structure that represents an object [analogous to ‘a first object corresponding to a cache copy of the data’ as claimed] in a file system. The object could be a file or a directory, for example.)
a second interface (see fig. 4, where flash 206 is connected to the communication interconnect 170) to communicate with a second memory medium that stores a second object corresponding to the data in a portion of the second memory medium, wherein the portion of the first memory medium has a faster access than the portion of the second memory medium. (e.g. fig. 3, flash 206; and paragraph 37, where energy reserve 218 provides sufficient electrical power to keep the DRAM 216 powered long enough for contents to be transferred to the flash memory 206 in the event of power failure; and paragraph 37, where each non-volatile solid-state storage 152 has a relatively fast non-volatile solid-state memory, such as non-volatile random access memory (NVRAM) 204; and paragraph 27, where in UNIX-style file systems, data is handled with an index node or inode, which specifies a data structure that represents an object [analogous to ‘a second object corresponding to the data’ as claimed] in a file system. The object could be a file or a directory, for example.)
However, the Davis reference does not explicitly teach:
at least one control circuit configured to: transmit, from the storage node to a user node, location information of the first object in the first memory medium; and transfer, between the user node and the storage node, using a memory access scheme and the location information, at least one of the first object or the second object; and wherein the location information comprises one or more locations at which the at least one of the first object or the second object is stored. [The Examiner notes the Davis reference teaches data corresponds to ‘objects’ as shown above]
The Jalal reference teaches it is conventional to have:
at least one control circuit (e.g. fig. 1, memory controller 110) configured to:
transmit, from the storage node to a user node, location information of the first object in the first memory medium; (paragraph 42, where if the request is a read request, as depicted by the ‘READ’ branch from decision block 506, flow continues to decision block 508. If the address is not found in the cache (a cache ‘miss’), as indicated by the negative branch from decision block 508, flow continues to decision block 510 to determine, from the snoop filter, if any other caches contain the requested data) and
transfer, between the user node and the storage node, using a memory access scheme and the location information, at least one of the first object or the second object; (paragraph 42, where if the address is not found in the snoop filter (a snoop filter ‘miss’), as depicted by the negative branch from decision block 510, a signal to read the data from memory is sent to a memory controller at block 512, and the snoop filter is updated. The data is received from the memory controller at block 514 and forwarded to the requesting RN-F at block 516) and
wherein the location information comprises one or more locations at which the at least one of the first object or the second object is stored. (paragraph 42, where if the address is not found in the snoop filter (a snoop filter ‘miss’), as depicted by the negative branch from decision block 510, a signal to read the data from memory is sent to a memory controller at block 512, and the snoop filter is updated. The data is received from the memory controller at block 514 and forwarded to the requesting RN-F at block 516)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Davis reference to have at least one control circuit configured to: transmit, from the storage node to a user node, location information of the first object in the first memory medium; and transfer, between the user node and the storage node, using a memory access scheme and the location information, at least one of the first object or the second object; and wherein the location information comprises one or more locations at which the at least one of the first object or the second object is stored, as taught by the Jalal reference.
The suggestion/motivation for doing so would have been to have a snoop filter that monitors access by the processors to the shared data resource, and includes snoop filter control logic and a snoop filter cache configured to maintain cache coherency. (Jalal, abstract)
Therefore it would have been obvious to combine the Davis and Jalal references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 2, the combination of the Davis and Jalal references teaches the apparatus of claim 1, wherein the at least one control circuit is configured to operate at least a portion of the first memory medium as a cache for at least a portion of the second memory medium. (Davis, e.g. fig. 3, NVRAM 204; and paragraph 37, where each non-volatile solid-state storage 152 has a relatively fast non-volatile solid-state memory, such as non-volatile random access memory (NVRAM) 204; and NVRAM 204 is implemented in one embodiment as high speed volatile memory, such as dynamic random access memory (DRAM) 216, backed up by energy reserve 218 [i.e. a ‘cache’])
With respect to claim 3, the combination of the Davis and Jalal references teaches the apparatus of claim 1, wherein the at least one control circuit is configured to transmit the location information using the memory access scheme. (Jalal, paragraph 42, where if the address is not found in the snoop filter (a snoop filter ‘miss’), as depicted by the negative branch from decision block 510, a signal to read the data from memory is sent to a memory controller at block 512, and the snoop filter is updated. The data is received from the memory controller at block 514 and forwarded to the requesting RN-F at block 516)
With respect to claim 4, the combination of the Davis and Jalal references teaches the apparatus of claim 1, wherein the at least one control circuit is configured to: receive a request for the location information; and transmit the location information based on the request. (Jalal, paragraph 42, where if the address is not found in the snoop filter (a snoop filter ‘miss’), as depicted by the negative branch from decision block 510, a signal to read the data from memory is sent to a memory controller at block 512, and the snoop filter is updated. The data is received from the memory controller at block 514 and forwarded to the requesting RN-F at block 516)
With respect to claim 5, the combination of the Davis and Jalal references teaches the apparatus of claim 1, wherein the at least one control circuit is configured to:
update the location information to generate updated location information; and perform a transmission, from the storage node, of the updated location information. (Jalal, paragraph 42, where if the address is not found in the snoop filter (a snoop filter ‘miss’), as depicted by the negative branch from decision block 510, a signal to read the data from memory is sent to a memory controller at block 512, and the snoop filter is updated. The data is received from the memory controller at block 514 and forwarded to the requesting RN-F at block 516)
With respect to claim 6, the combination of the Davis and Jalal references teaches the apparatus of claim 5, wherein the transmission of the updated location information is caused by the storage node. (Jalal, paragraph 42, where if the address is not found in the snoop filter (a snoop filter ‘miss’), as depicted by the negative branch from decision block 510, a signal to read the data from memory is sent to a memory controller at block 512, and the snoop filter is updated. The data is received from the memory controller at block 514 and forwarded to the requesting RN-F at block 516)
With respect to claim 7, the combination of the Davis and Jalal references teaches the apparatus of claim 1, wherein the at least one control circuit is configured to: receive a request to transfer the second object; and transfer, based on the request, from the storage node, using the memory access scheme, the second object. (Jalal, paragraph 42, where if the address is not found in the snoop filter (a snoop filter ‘miss’), as depicted by the negative branch from decision block 510, a signal to read the data from memory is sent to a memory controller at block 512, and the snoop filter is updated. The data is received from the memory controller at block 514 and forwarded to the requesting RN-F at block 516)
With respect to claim 8, the combination of the Davis and Jalal references teaches the apparatus of claim 7, wherein the request to transfer the second object comprises a command. (Davis, paragraph 26, where data is requested to be pulled, and in other embodiments, data is pushed. In reverse, when data is read, the authority 168 for the segment ID containing the data is located as described above. The host CPU 156 of the storage node 150 on which the non-volatile solid-state storage 152 and corresponding authority 168 reside requests the data from the non-volatile solid-state storage and corresponding storage nodes pointed to by the authority)
With respect to claim 9, the combination of the Davis and Jalal references teaches the apparatus of claim 1, wherein: the storage node comprises a network adapter; and the network adapter comprises at least a portion of the memory access scheme. (Davis, paragraph 40, the network interface controller 202 of each storage node 150 in the storage cluster is coupled to the communication interconnect 170, providing a communication path 234 among storage nodes 150 and non-volatile solid-state storage 152. Embodiments of storage nodes 150 have one or more non-volatile solid-state storage 152)
Claims 10-18 are another apparatus implementation of claims 1-9, wherein there is receiving of the ‘location information’ instead of transmitting as shown in the claims above, and rejected under the same rationale as shown in the rejections above.
Claims 19-20 is a similar method implementation of claims 1-9, and rejected
under the same rationale as shown in the rejections above.
2. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see pages 7-9 of the remarks) and amendments with respect to claims 1-20 have been considered, and are not persuasive.
Particularly, the Applicant argues (see page 8) Davis does not teach "a first interface to communicate with a first memory medium that stores a first object corresponding to a cache copy of data in a portion of the first memory medium," and "a second interface to communicate with a second memory medium that stores a second object corresponding to the data in a portion of the second memory medium". The Examiner respectfully disagrees. The Davis reference teaches (see fig. 3 and paragraph 37) a NVRAM 204 (i.e. “a first memory medium that stores a first object corresponding to a cache copy of the data in a portion of the first memory medium”) and a flash memory 206 (i.e. “a second memory medium that stores the data in a portion of the second memory medium, wherein the portion of the first memory medium has a faster access than the portion of the second memory medium”. Further, the Davis reference teaches (see fig. 4) that the NVRAM and flash 206 are connected to a communication interconnect 170 to create a “first interface” and “second interface” to these memories.
Secondly, the Applicant argues (see page 8) that Davis does not teach the limitations of "a first object corresponding to a cache copy of data in a portion of the first memory medium," and "a second object corresponding to the data in a portion of the second memory medium." As shown in the updated citations of the Davis reference in the rejections above, the Davis reference teaches (paragraph 27) where in UNIX-style file systems, data is handled with an index node or inode, which specifies a data structure that represents an object in a file system; and the object could be a file or a directory. Thus, in view of the citations above, the data could be represented in an ‘object’ form as argued.
Lastly, the Applicant argues (see pages 8-9) “Davis and Jalal cannot be combined because the proposed modification would render the prior art invention being modified unsatisfactory for its intended purpose”. In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, the suggestion/motivation for combining the Davis and Jalal references teaches would have been to have a snoop filter that monitors access by the processors to the shared data resource, and includes snoop filter control logic and a snoop filter cache configured to maintain cache coherency. (Jalal, abstract)
Thus, the Examiner has maintained the rejections for the reasons set forth above. Any arguments not specifically addressed can refer to the reasons set forth above.
3. RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
O'Krafka (US 20090240869), which teaches a Sharing Data Fabric (SDF) causes flash memory attached to multiple compute nodes to appear to be a single large memory space that is global yet shared by many applications running on the many compute nodes. Flash objects stored in flash memory of a home node are copied to an object cache in DRAM at an action node by SDF threads executing on the nodes. The home node has a flash object map locating flash objects in the home node's flash memory, and a global cache directory that locates copies of the object in other sharing nodes. Application programs use an applications-programming interface (API) into the SDF to transparently get and put objects without regard to the object's location on any of the many compute nodes. SDF threads and tables control coherency of objects in flash and DRAM.
4. CLOSING COMMENTS
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
Prosecution Insights