DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Examiner acknowledges the applicant's submission of the amendment dated 12/24/25, which has been entered.
1. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Davis (US 20160041887) in view of Jalal (US 20170168939).
With respect to claim 1, the Davis reference teaches an apparatus comprising:
a storage node (see fig. 3, storage node 152) comprising:
a first interface to communicate with a first memory medium that stores a cache copy of the data in a portion of the first memory medium; (e.g. fig. 3, NVRAM 204; and paragraph 37, where each non-volatile solid-state storage 152 has a relatively fast non-volatile solid-state memory, such as non-volatile random access memory (NVRAM) 204; and NVRAM 204 is implemented in one embodiment as high speed volatile memory, such as dynamic random access memory (DRAM) 216, backed up by energy reserve 218 [i.e. a ‘cache’])
a second interface to communicate with a second memory medium that stores the data in a portion of the second memory medium, wherein the portion of the first memory medium has a faster access than the portion of the second memory medium. (e.g. fig. 3, flash 206; and paragraph 37, where energy reserve 218 provides sufficient electrical power to keep the DRAM 216 powered long enough for contents to be transferred to the flash memory 206 in the event of power failure; and paragraph 37, where each non-volatile solid-state storage 152 has a relatively fast non-volatile solid-state memory, such as non-volatile random access memory (NVRAM) 204)
However, the Davis reference does not explicitly teach: at least one control circuit configured to: transmit, from the storage node to a user node, location information of the cache copy in the first memory medium; and transfer, between the user node and the storage node, using a memory access scheme and the location information, at least one of the cache copy or the data; and wherein the location information comprises one or more locations at which the at least one of the cache copy or the data is stored.
The Jalal reference teaches it is conventional to have:
at least one control circuit (e.g. fig. 1, memory controller 110) configured to:
transmit, from the storage node to a user node, location information of the cache copy in the first memory medium; (paragraph 42, where if the request is a read request, as depicted by the ‘READ’ branch from decision block 506, flow continues to decision block 508. If the address is not found in the cache (a cache ‘miss’), as indicated by the negative branch from decision block 508, flow continues to decision block 510 to determine, from the snoop filter, if any other caches contain the requested data) and
transfer, between the user node and the storage node, using a memory access scheme and the location information, at least one of the cache copy or the data; (paragraph 42, where if the address is not found in the snoop filter (a snoop filter ‘miss’), as depicted by the negative branch from decision block 510, a signal to read the data from memory is sent to a memory controller at block 512, and the snoop filter is updated. The data is received from the memory controller at block 514 and forwarded to the requesting RN-F at block 516) and
wherein the location information comprises one or more locations at which the at least one of the cache copy or data is stored. (paragraph 42, where if the address is not found in the snoop filter (a snoop filter ‘miss’), as depicted by the negative branch from decision block 510, a signal to read the data from memory is sent to a memory controller at block 512, and the snoop filter is updated. The data is received from the memory controller at block 514 and forwarded to the requesting RN-F at block 516)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Davis reference to have at least one control circuit configured to: transmit, from the storage node to a user node, location information of the cache copy in the first memory medium; and transfer, between the user node and the storage node, using a memory access scheme and the location information, at least one of the cache copy or the data; and wherein the location information comprises one or more locations at which the at least one of the cache copy or the data is stored, as taught by the Jalal reference.
The suggestion/motivation for doing so would have been to have a snoop filter that monitors access by the processors to the shared data resource, and includes snoop filter control logic and a snoop filter cache configured to maintain cache coherency. (Jalal, abstract)
Therefore it would have been obvious to combine the Davis and Jalal references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 2, the combination of the Davis and Jalal references teaches the apparatus of claim 1, wherein the at least one control circuit is configured to operate at least a portion of the first memory medium as a cache for at least a portion of the second memory medium. (Davis, e.g. fig. 3, NVRAM 204; and paragraph 37, where each non-volatile solid-state storage 152 has a relatively fast non-volatile solid-state memory, such as non-volatile random access memory (NVRAM) 204; and NVRAM 204 is implemented in one embodiment as high speed volatile memory, such as dynamic random access memory (DRAM) 216, backed up by energy reserve 218 [i.e. a ‘cache’])
With respect to claim 3, the combination of the Davis and Jalal references teaches the apparatus of claim 1, wherein the at least one control circuit is configured to transmit the location information using the memory access scheme. (Jalal, paragraph 42, where if the address is not found in the snoop filter (a snoop filter ‘miss’), as depicted by the negative branch from decision block 510, a signal to read the data from memory is sent to a memory controller at block 512, and the snoop filter is updated. The data is received from the memory controller at block 514 and forwarded to the requesting RN-F at block 516)
With respect to claim 4, the combination of the Davis and Jalal references teaches the apparatus of claim 1, wherein the at least one control circuit is configured to: receive a request for the location information; and transmit the location information based on the request. (Jalal, paragraph 42, where if the address is not found in the snoop filter (a snoop filter ‘miss’), as depicted by the negative branch from decision block 510, a signal to read the data from memory is sent to a memory controller at block 512, and the snoop filter is updated. The data is received from the memory controller at block 514 and forwarded to the requesting RN-F at block 516)
With respect to claim 5, the combination of the Davis and Jalal references teaches the apparatus of claim 1, wherein the at least one control circuit is configured to:
update the location information to generate updated location information; and perform a transmission, from the storage node, of the updated location information. (Jalal, paragraph 42, where if the address is not found in the snoop filter (a snoop filter ‘miss’), as depicted by the negative branch from decision block 510, a signal to read the data from memory is sent to a memory controller at block 512, and the snoop filter is updated. The data is received from the memory controller at block 514 and forwarded to the requesting RN-F at block 516)
With respect to claim 6, the combination of the Davis and Jalal references teaches the apparatus of claim 5, wherein the transmission of the updated location information is caused by the storage node. (Jalal, paragraph 42, where if the address is not found in the snoop filter (a snoop filter ‘miss’), as depicted by the negative branch from decision block 510, a signal to read the data from memory is sent to a memory controller at block 512, and the snoop filter is updated. The data is received from the memory controller at block 514 and forwarded to the requesting RN-F at block 516)
With respect to claim 7, the combination of the Davis and Jalal references teaches the apparatus of claim 1, wherein the at least one control circuit is configured to: receive a request to transfer the data; and transfer, based on the request, from the storage node, using the memory access scheme, the data. (Jalal, paragraph 42, where if the address is not found in the snoop filter (a snoop filter ‘miss’), as depicted by the negative branch from decision block 510, a signal to read the data from memory is sent to a memory controller at block 512, and the snoop filter is updated. The data is received from the memory controller at block 514 and forwarded to the requesting RN-F at block 516)
With respect to claim 8, the combination of the Davis and Jalal references teaches the apparatus of claim 7, wherein the request to transfer the data comprises a command. (Davis, paragraph 26, where data is requested to be pulled, and in other embodiments, data is pushed. In reverse, when data is read, the authority 168 for the segment ID containing the data is located as described above. The host CPU 156 of the storage node 150 on which the non-volatile solid-state storage 152 and corresponding authority 168 reside requests the data from the non-volatile solid-state storage and corresponding storage nodes pointed to by the authority)
With respect to claim 9, the combination of the Davis and Jalal references teaches the apparatus of claim 1, wherein: the storage node comprises a network adapter; and the network adapter comprises at least a portion of the memory access scheme. (Davis, paragraph 40, the network interface controller 202 of each storage node 150 in the storage cluster is coupled to the communication interconnect 170, providing a communication path 234 among storage nodes 150 and non-volatile solid-state storage 152. Embodiments of storage nodes 150 have one or more non-volatile solid-state storage 152)
Claims 10-18 are another apparatus implementation of claims 1-9, wherein there is receiving of the ‘location information’ instead of transmitting as shown in the claims above, and rejected under the same rationale as shown in the rejections above.
Claims 19-20 is a similar method implementation of claims 1-9, and rejected
under the same rationale as shown in the rejections above.
2. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see pages 7-9 of the remarks) and amendments with respect to claims 1-20 have been considered, and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of updated citations of the Davis reference, and the addition of the Jalal reference to teach the newly added limitations as shown in the updated rejections above.
3. CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
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