Prosecution Insights
Last updated: October 27, 2026
Application No. 18/375,487

THROTTLING FOR POWER AND THERMAL MANAGEMENT

Non-Final OA §103
Filed
Sep 30, 2023
Priority
Aug 18, 2023 — IN 202341055579
Examiner
JOHNSON, TERRELL S
Art Unit
Tech Center
Assignee
Intel Corporation
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
436 granted / 502 resolved
+26.9% vs TC avg
Moderate +10% lift
Without
With
+10.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
16 currently pending
Career history
516
Total Applications
across all art units

Statute-Specific Performance

§101
8.3%
-31.7% vs TC avg
§103
43.2%
+3.2% vs TC avg
§102
29.9%
-10.1% vs TC avg
§112
9.3%
-30.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 502 resolved cases

Office Action

§103
DETAILED ACTION Status of Claims Claims 1 – 20 are pending. Claims 1, 16, and 20 are independent. This office action is Non-Final. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-6, 9, 11, 12, 14 – 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zou et al. (US Patent Application Publication No. 2011/0161683, hereinafter “Zou”), in view of Park et al. (US Patent Application Publication No. 2015/0181117, hereinafter “Park”). As per claim 1, Zou teaches an apparatus comprising: a processor core [core 103, Fig. 1B, 0029 - 0030]; and a power management unit coupled to the processor core [PMU 104/ PMU 304, coupled to cores Fig. 1A and 1B, 0021, 0024, 0029] to: determine when one or more of power and thermal operating characteristics of a system, of which the apparatus is a part of [0044 – 0045: The P-Code 105 functions as the low-level program for the PMU when implemented as a controller. .. It includes a low-level power management engine 264, a DPMI-enable device policy look-up table 265, a DPMI not-enable device policy look-up table 266, a low-level OS PM event handler 267, an average power usage monitor module 268, a timer management module 269, a thermal management module 270, and a sensor monitoring module 271.] … and place one or more of devices coupled to the power management unit into a lower power state… [0023 – 0024: A benefit of the PMU and DPMI, … is that it can work within the framework of the OS power management 102 scheme or independent of it. so, for example, working within it, the OS may implement conventional power state schemes such as ACPI, etc. and at the same time, the PMU and DPMI logic can work to manage power on a lower level (higher granularity, faster response), in many cases, without having to go through the OS framework… The OS may be in a given power state (e.g., G state or s state) and the PMU 104/DPMI 106 may manage power for the devices accordingly… the PMU/DPMI might change device power states more slowly, more quickly, and/or differently, e.g., instruct something to stay on or off or in a reduced power mode for a longer or shorter time.]. However, Zou does not explicitly teach “…determine when one or more of power and thermal operating characteristics of a system, of which the apparatus is a part of, are outside of a system constraint, and place one or more of devices coupled to the power management unit into a lower power state to meet the system constraint.”. Park is cited to teach adjusting at least one operating parameter of the device to produce an operating characteristic target, wherein the adjustment is based on an estimated change to the determined user experience metric due to the adjustment. In particularly, Park teaches a trigger based on a system power or thermal constraint. Both Park and Zou are directed to power management. As per claim 1, Park further teaches …determine when one or more of power and thermal operating characteristics of a system, of which the apparatus is a part of, are outside of a system constraint [Fig. 7, 142, 144, 0109 – 0110: Device 40 may then determine power consumption (P) of one or more components of device 40 …and/or a system temperature (T) of device 40 (142)… Device 40 may determine whether the power consumption (P) exceeds a predetermined power budget and/or whether the temperature exceeds a predetermined temperature limit (T) (144). If the power consumption (P) exceeds the power budget and/or the temperature (T) exceeds the temperature limit (the yes branch of step 144), device 40, e.g., thermal/power manager 80 of device 40, may determine one or more operating parameters in vector S that, when adjusted, produce a minimum user experience ratio (delta UX/delta P (or delta T)) (146)., 0069-0070 ], and place one or more of devices coupled to the power management unit into a lower power state to meet the system constraint [Fig. 7, steps 146 – 150, 0068, 0072-0074: thermal/power manager 116 may adjust the operating parameters by selecting one or more operating parameters to maximize or at least increase a change in the operating parameters, thereby increasing or potentially maximizing a change in power usage (as determined using power model 114) relative to selecting other operating parameters.] It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Park and Zou, as Park teaches a policy (when power or temperature exceeds a target), to place components into lower-power operating points. As per claim 2, Zou teaches the apparatus of claim 1, wherein the power management unit comprises firmware [power management unit PMU 104 and P-code 105, 0021; 0024: Policies for processing these, and other, factors to control the amount of power to be supplied by the VRs may be implemented by a combination of executable software or firmware (referred to as "P-code" 105) executing in the PMU and the DPMI logic 106 , 0044: The P-Code 105 functions as the low-level program for the PMU when implemented as a controller. (equivalent appropriate code/logic may be used for alternative PMU implementations.)]. As per claim 3, Zou teaches the apparatus of claim 1, wherein the power management unit is to maintain status of the one or more devices coupled to the apparatus [0028: The DPMI logic can function to more quickly administer such device traffic and forward it to the PMU in a desired fashion; 0037: The device communicates activity status and power state change request to the PMU 104 in real-time, and the PMU can then quickly adjust the given supply rail (and possibly sub-systems such as a clock tree, for example) to low power states; 0044-0045: The P-Code 105 functions as the low-level program for the PMU when implemented as a controller.. It includes a low-level power management engine 264, a DPMI-enable device policy look-up table 265, a DPMI not-enable device policy look-up table 266, a low-level OS PM event handler 267, an average power usage monitor module 268, a timer management module 269, a thermal management module 270, and a sensor monitoring module 271… The P-Code also enables the PMU to track average power usage, e.g., for interested devices, using the average power usage monitor 268 and sensor monitoring modules 271.]. As per claim 4, Zou, in view of Park teaches the apparatus of claim 1, wherein the one or more devices comprise one or more of a display [Park: displays 26A and 26B, local display 56, fig.2, 0022], a peripheral component interface, and a universal serial bus [Zou: 0003: USB devices , 0041: hardware layer integrates the PMU 104, VRs 108 and USB devices]. As per claim 5, Park teaches the apparatus of claim 4, wherein the lower power state is a reduction to a display frame rate [0053: In the example of FIG. 3, camera system 106 also includes frame rate scaling unit 108 and resolution scaling unit 110. …In some examples, as described in greater detail below, frame scaling unit 108 and resolution scaling unit 110 may receive commands from thermal/power manager 116. For example, frame scaling unit 108 may receive control commands from thermal/power manager 116 that indicate a particular frame rate.]. As per claim 6, Park teaches the apparatus of claim 4, wherein the lower power state is a reduction to a display resolution [0053: In the example of FIG. 3, camera system 106 also includes frame rate scaling unit 108 and resolution scaling unit 110. … Resolution scaling unit 110 may be operable to change the resolution of images captured by camera system 106. In some examples, as described in greater detail below, frame scaling unit 108 and resolution scaling unit 110 may receive commands from thermal/power manager 116…. In addition, resolution scaling unit110 may receive control commands from thermal/power manager 116 that indicate a particular resolution.]. As per claim 11, Park teaches the apparatus of claim 1, wherein the system constraint is a thermal constraint [0047: Thermal/power manager 80 may manage one or more components of device 40 to keep the one or more components operating at or below one or more operating characteristic targets. In an example, the operating characteristic target may be a thermal target (which also may be referred to as a thermal limit or thermal threshold) indicative of an operating temperature of device 40, such that adjusting the at least one operating parameter of the device to produce the operating characteristic target comprises adjusting the at least one operating parameter of the device to maintain a temperature of one or more components of device 40 equal to or less than the thermal target.]. As per claim 12, Park teaches the apparatus of claim 1, wherein the system constraint is a power constraint [0047: Thermal/power manager 80 may manage one or more components of device 40 to keep the one or more components operating at or below one or more operating characteristic targets. …the operating characteristic target comprises a power target (which also may be referred to as a power budget or power threshold) indicative of an amount of power consumed by operating the device, such that adjusting the at least one operating parameter of device 40 to produce the operating characteristic target comprises adjusting the at least one operating parameter of device40 to maintain a power consumption of one or more components of device 40 equal to or less than the power target.]. As per claim 14, Zou teaches the apparatus of claim 1, wherein after placing one or more of the devices coupled to the power management unit via the at least one interconnect into a lower power state, the power management unit is further to: determine when one or more of power and thermal operating characteristics of a system, of which the apparatus is a part of, are within of a system constraint, and place one or more of the devices coupled to the power management unit into a higher power state [0037: The device communicates activity status and power state change request to the PMU 104 in real-time, and the PMU can then quickly adjust the given supply rail … to low power states, and "recover" to a higher power state as needed, thereby enabling the platform to achieve increased power usage efficiency.]. As per claim 15, Zou teaches the apparatus of claim 1, wherein the processor core is to be placed into a lower power state by power management unit when the system constraint is met [0029: a PMU 104 and DPMI 106 for managing VRs (not shown) for powering the devices including the one or more cores.]. As per claims 16 - 18, it is directed to a method of steps to implement on the apparatus set forth in claims 1, 4, 11, and 12. Zou, in view of Park, teaches the claimed apparatus. Therefore, Zou, in view of Park, teaches the method to implement the claims steps. As per claim 20, it is directed to a system to implement with the apparatus set forth in claims 1, 4, 11, and 12. Zou, in view of Park teaches the claimed apparatus. Therefore, Zou, in view of Park, teaches the system to implement with the claimed device. Claims 7, 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Zou et al. (US Patent Application Publication No. 2011/0161683, hereinafter “Zou”), in view of Park et al. (US Patent Application Publication No. 2015/0181117, hereinafter “Park”), in even further view of Hassan et al (US Patent Application Publication No. 2008/0141049, hereinafter “Hassan”) As per claim 7, Zou, in view of Park, teaches the apparatus of claim 4. However, Zou, in view of Park, does not teach “… wherein the lower power state is a reduction to a number of displays…”. Hassan is cited to teach a system and method to increase battery life for portable computing devices through intelligent display management. Zou, in view of Park, teaches a method to keep a platform within a power or thermal budget. Hassan teaches that the display can be placed in a lower power display state: reduced area and resolution, saving power. Hassan, Zou and Park are directed to power management. As per claim 7, Hassan teaches the apparatus of claim 4, wherein the lower power state is a reduction to a number of displays [0009-0011: determining that the remaining power falls below a first threshold, and in response to the amount of remaining power falling below the first threshold level, partitioning the display into a first and a second portion and causing power to be substantially reduced to the first portion; 0037: a number of partitions on the display may be turned off ]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention Hassan with Zou and Park as Hassan teaches power management of the display device. As per claim 131, Hassan teaches the apparatus of claim 1, wherein the system constraint is a user configurable [0007-0008: A user interface is provided where a user can input threshold values and parameters such that power management actions, 0010, 0037: The threshold value may be preset or may be user-configured]. As per claim 19, Hassan teaches the method of claim 16, wherein the system constraint is a user configurable [0007-0008: A user interface is provided where a user can input threshold values and parameters such that power management actions, 0010, 0037: The threshold value may be preset or may be user-configured]. 20030088799 Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Zou et al. (US Patent Application Publication No. 2011/0161683, hereinafter “Zou”), in view of Park et al. (US Patent Application Publication No. 2015/0181117, hereinafter “Park”), in even further view of Bodas (US Patent Application Publication No. 2003/0088799). As per claim 8, Zou, in view of Park, teaches the apparatus of claim 4. However, Zou, in view of Park, does not teach “… wherein the lower power state is a peripheral component interface lane adjustment…”. Bodas is cited to teach a system for the regulation of electrical component temperature and power consumption rate through the reconfiguration between different interconnect bus widths. Bodas, Zou and Park are directed to power management. As per claim 8, Bodas further teaches …wherein the lower power state is a peripheral component interface lane adjustment [0010 – 0017: thermal/power trigger]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention Bodas with Zou and Park as Bodas’s link -width reduction as another parameter to adjust to achieve additional power savings. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Zou et al. (US Patent Application Publication No. 2011/0161683, hereinafter “Zou”), in view of Park et al. (US Patent Application Publication No. 2015/0181117, hereinafter “Park”), in even further view of Ghosh et al.(US Patent Application Publication No. 2020/00393885, hereinafter “Ghosh”). As per claim 10, Zou and Park teaches the apparatus of claim 4. However, Zou, in view of Park, does not teach “… wherein the lower power state is a universal serial bus port adjustment…”. Ghosh is cited to teach power management of USB ports based on power budget and temperature. Ghosh, Zou and Park are directed to power management. As per claim 10, Ghosh teaches the apparatus of claim 4, wherein the lower power state is a universal serial bus port adjustment [throttles or shuts off an individual USB port when it gets hot, fig. 3 and 4, 0076]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention Ghosh with Zou and Park as Ghosh’s USB port power adjustment is another parameter to adjust to achieve additional power savings. Allowable Subject Matter Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Selvam; Thiyagarajan et al. (US Patent Application Publication No. 2020/0371579 “Bandwidth Based Power Management For Peripheral Component Interconnect Express Devices” is cited to teach a system that includes an interface circuit configured to provide an interface with a link, and a controller. The controller is configured to receive one or more bandwidth requests from one or more clients, and determine at least one of a link speed and a link width for the link based on the one or more bandwidth requests. Venkideswaran; Ajay et al. (US Patent Application Publication No. 2021/0208648 “Dynamic Power Throttling Based On System Conditions In USB Type-C Power Delivery (USB-C/PD) Ecosystem” is cited to teach technology to dynamically throttle power in a power delivery system. In one embodiment, a power delivery system includes a controller associated with a port to supply power. The controller manages a power budget available to the port based on a current state of one or more system parameters. The power budget available to the port can be throttled when the power delivery system operates under stress conditions and adjusted when the power delivery system is no longer operating under stress conditions. Branover; Alexander J. et al. (US Patent Application Publication No. 2016/0378168) “Dynamic Power Management Optimization” is cited to teach systems, apparatuses, and methods for managing power usage of integrated circuits. One or more processor cores may be powered down when the system is idle. Even if there is no user activity, the processor core(s) may be woken up periodically for background downloads to retrieve the latest status for social media and other applications. Additionally, a power management unit may track the average number of active cores and the average core utilization. If the average number of active cores is less than a first threshold and the average core utilization is less than a second threshold, the power management unit may generate a request to offline one or more cores. Still further, when the processor's skin temperature is above a threshold and all of the cores are operating at the lowest acceptable operating point, one or more cores may be powered down. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERRELL S JOHNSON whose telephone number is (571)270-3485. The examiner can normally be reached 10AM-7PM EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TERRELL S JOHNSON/Primary Examiner, Art Unit 2176 1 The same rationale as set forth in the detailed discussion of claim 7 hereinabove is applied to claims 13 and 19, to the extent that is applicable.
Read full office action

Prosecution Timeline

Sep 30, 2023
Application Filed
Nov 15, 2023
Response after Non-Final Action
Oct 05, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
97%
With Interview (+10.4%)
2y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 502 resolved cases by this examiner. Grant probability derived from career allowance rate.

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