CTNF 18/375,492 CTNF 83106 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Lee et al. (US 2016/0239074, hereinafter Lee) . As per claim 1, Lee teaches an apparatus comprising: a first plurality of physical processing devices of a first type (i.e., heterogeneous multiprocessor may include two different types of cores, see at least [0030]); a second plurality of physical processing devices of a second type (i.e., heterogeneous multiprocessor may include two different types of cores, see at least [0030]); a power management unit to monitor telemetry data on the first plurality of processing devices and second plurality of processing devices and to update hardware feedback telemetry data based at least in part on the hardware telemetry data and thread runtime telemetry data to provide a hint to consolidate a task on at least one core of the second type (i.e., a PCU or other power management logic to perform processor-based power management, including workload classification and dynamic thread migration, collect input statistics periodically by reading performance/energy counters, and then using an intelligent model to evaluate the current status and predict the next optimal power configuration, the control logic applies this power control decision via thread migration, see at least [0117], [0120]-[0122], [0126], [0153]-[0157]); and thread runtime telemetry circuitry to maintain the hardware feedback telemetry data (i.e., history logic may implement a history table to record prior power configuration decisions and system states, see at least [0150], [0157]). As per claim 2, Lee teaches wherein hardware telemetry data of the first plurality of cores includes a number of cores of each type that are concurrently active and an operating frequency of the active cores and hardware telemetry data of the second plurality of cores is a maximum frequency, average frequency, and average concurrency (i.e., a number of actively powered cores in a current operational level and the power state thereof, performance state for a core may be a guaranteed operating frequency (which is a maximum operating frequency at which a processor is guaranteed to operate), a collection of average statistical values for all attributes during a sampling time period, see at least [0128]-[0133], [0153]). As per claim 3, Lee teaches wherein the hint is to consolidate all energy efficiency oriented tasks on the cores for which an energy efficiency capability is a set value (i.e., memory bound workloads execute on memory optimized cores, compute bound workloads execute on compute optimized core, see at least [0025]-[0032], [0141], [0173], [0174]). As per claim 4, Lee teaches wherein the hint is to consolidate all performance oriented tasks on the cores for which a performance capability is a set value (i.e., memory bound workloads execute on memory optimized cores, compute bound workloads execute on compute optimized core, see at least [0025]-[0032], [0141], [0173], [0174]). As per claim 5, Lee teaches wherein the thread runtime telemetry data includes a compute type capability per class (i.e., classify workload being executed based on some or all workload characteristics information, see at least Fig. 18, [0126], [0128], [0154]). As per claim 6, Lee teaches wherein the thread runtime telemetry data includes a per class latency (i.e., classify workload being executed based on some or all workload characteristics information, the determination of workload memory boundedness may be based on an aggregate of latency information, see at least Fig. 18, [0126], [0128], [0154]). As per claim 7, Lee teaches wherein the thread runtime telemetry data includes a per class power value (i.e., classify workload being executed based on some or all workload characteristics information, such information may be received from performance/energy counters of various cores, see at least Fig. 18, [0025]-[0028], [0126], [0128], [0153], [0154]). As per claim 8, Lee teaches wherein the hardware telemetry data includes system operating characteristics (i.e., runtime statistics (e.g., various performance/energy counters) at a current time sample, see at least [0121], [0122]). As per claim 9, Lee teaches a system comprising: a first plurality of physical processing devices of a first type (i.e., heterogeneous multiprocessor may include two different types of cores, see at least [0030]); a second plurality of physical processing devices of a second type (i.e., heterogeneous multiprocessor may include two different types of cores, see at least [0030]); a power management unit to monitor telemetry data on the first plurality of processing devices and second plurality of processing devices and to update hardware feedback telemetry data based at least in part on the hardware telemetry data and thread runtime telemetry data to provide a hint to consolidate a task on at least one core of the second type (i.e., a PCU or other power management logic to perform processor-based power management, including workload classification and dynamic thread migration, collect input statistics periodically by reading performance/energy counters, and then using an intelligent model to evaluate the current status and predict the next optimal power configuration, the control logic applies this power control decision via thread migration, see at least [0117], [0120]-[0122], [0126], [0153]-[0157]); and thread runtime telemetry circuitry to maintain the hardware feedback telemetry data (i.e., history logic may implement a history table to record prior power configuration decisions and system states, see at least [0150], [0157]); and memory to store system software to receive the hardware feedback telemetry data (see at least Fig. 17., [0125]-[0130]). As per claims 10-15, these are the system claims of claims 2-7. Therefore, claims 10-15 are rejected using the same reasons as claims 2-7. As per claims 16-20, these are the method claims of claims 1 and 3-6. Therefore, claims 16-20 are rejected using the same reasons as claims 1 and 3-6 . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Busaba et al. (US 8,930,950) Naveh et al. (US 10,185,566) Bieswanger et al. (US 2010/0037038) Wolfe et al. (US 2011/0066828) Park et al. (US 2017/0024316) Bassin et al. (US 2023/0018828) Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jue Louie whose telephone number is (571)270-1655. The examiner can normally be reached M-F, 9:30am-5:00pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Brooks can be reached at (571)272-8112. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Jue Louie/ Primary Examiner Art Unit 6221 Application/Control Number: 18/375,492 Page 2 Art Unit: 6221 Application/Control Number: 18/375,492 Page 3 Art Unit: 6221 Application/Control Number: 18/375,492 Page 4 Art Unit: 6221
