DETAILED ACTION
Summary
This Office Action is in response to the Amendments to the Claims and Remarks filed December 10, 2025.
In view of the Amendments to the Claims filed December 10, 2025, the rejections of claims 13-17, 20, and 22 under 35 U.S.C. 112(b) previously presented in the Office Action sent September 17, 2025 have been withdrawn.
In view of the Amendments to the Claims filed December 10, 2025, the rejections of claims 1-17 and 20-22 under 35 U.S.C. 103 previously presented in the Office Action sent September 17, 2025 have been substantially maintained and modified only in response to the Amendments to the Claims.
Claims 1-17 and 20-22 are currently pending.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21 and 22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 21 recites, “further comprising an antireflection film, wherein the antireflection film is located on a surface of the first insulating film opposite the first conductive region”.
However, claim 1, from which claim 21 depends, already recites, “the first insulating film is a first passivation film and a first antireflection film”.
The specification, as originally filed, does not evidence Applicant had in possession an invention including a first insulating film is a first passivation film and a first antireflection film and also further comprising an antireflection film, wherein the antireflection film is located on a surface of the first insulating film opposite the first conductive region.
The specification only teaches a first passivation film 24 and a first antireflection film 26 which collectively are used as the first insulating film (see, for example, instant [0062]) but does not teach a first passivation film and a first antireflection film and further comprising an antireflection film. Dependent claims are rejected for dependency.
Claim 22 recites, “further comprising forming an antireflection film covering the first insulating film”.
However, claim 1, from which claim 13 depends, already recites, “the first insulating film is a first passivation film and a first antireflection film”.
The specification, as originally filed, does not evidence Applicant had in possession an invention including a first insulating film is a first passivation film and a first antireflection film and also further comprising forming an antireflection film covering the first insulating film.
The specification only teaches a first passivation film 24 and a first antireflection film 26 which collectively are used as the first insulating film (see, for example, instant [0062]) but does not teach a first passivation film and a first antireflection film and further comprising an antireflection film. Dependent claims are rejected for dependency.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 9, 10, 13, and 20-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 210897294 U included in Applicant submitted IDS filed October 17, 2024) in view of Shin et al. (U.S. Pub. No. 2014/0311562 A1).
With regard to claim 1, Chen et al. discloses a solar cell, comprising:
a semiconductor substrate having a first major surface and a second major surface (10 depicted in Fig. 3 as having a first major bottom surface and a second major top surface);
a tunneling layer (20’, Fig. 3), wherein
the tunneling layer is located on the first major surface of the semiconductor substrate (as depicted in Fig. 3, the cited tunneling layer 20’ is located on the cited first major bottom surface of the semiconductor substrate 10);
a first conductive region (30’, Fig. 3), wherein
the first conductive region is located on the tunneling layer on a surface of the first tunneling layer opposite the semiconductor substrate (as depicted in Fig. 3, the cited first conductive region 30’ is located on the cited tunneling layer 20’ opposite the semiconductor substrate 10);
a first insulating film (80, Fig. 3), wherein
the first insulating film is located on a surface of the first conductive region opposite the tunneling layer and the first insulating film and passivates the first conductive region; (as depicted in Fig. 3, the cited first insulating film 80 is located on a surface of the first conductive region 30’ opposite the tunneling layer 20’ and passivates the cited first conductive region 30’; see [0031] and [0033] teaching “a silicon nitride film layer”);
a second conductive region (30, Fig. 3), wherein
the second conductive region is located at the second major surface of the semiconductor substrate and composed of a doping region (as depicted in Fig. 3, the cited second conductive region 30 is located at the cited second major top surface of the cited semiconductor substrate 10 and composed of a doping region; see [0024]);
a first electrode (70, Fig. 3), wherein
the first electrode is connected to the first conductive region (as depicted in Fig. 3, the cited first electrode 70 is connected to the cited first conductive region 30’) and
is formed through the first insulating film by firing of metal material (the cited first electrode 70 is cited to read on the claimed product-by-process limitation “is formed through the first insulating film by firing of metal material” because the cited first electrode 70 is formed through the cited first insulating film 80 and includes metal material; see [0012]); and
a second electrode (50, Fig. 3), wherein
the second electrode is connected to the second conductive region (as depicted in Fig. 3, the cited second electrode 50 is connected to the cited second conductive region 30), wherein
the first conductive region comprises a first part connected to the first electrode (as depicted in Fig. 3, the cited first conductive region 30’ comprises a first part 33 connected to the cited first electrode 70) and
a second part other than the first part (as depicted in Fig. 3, a second part 34 other than the first part 33), and
a thickness of the first part is different from that of the second part (as depicted in Fig. 3, a vertical thickness of the first part 33 is different from that of the second part 34); wherein
a thickness of the first part of the first conductive region is configured so that the tunneling layer is protected from penetration of the fired metal material (the cited thickness of the cited first part 33 is cited to read on the claimed “is configured so that the tunneling layer is protected from penetration of the fired metal material” because it forms a thickness of material at 33 which is a physical barrier between the cited first electrode 70 and the cited tunnel laying 20’ and is a thickness that is greater than the thickness of the cited second part 34); wherein
the first insulating film is a first passivation film and a first antireflection film (see Fig. 3 depicting cited first insulating film 80 adjacent cited first conductive region 30’ of doped polysilicon material and see [0033] teaching a “silicon nitride film layer”; the top half of the cited first insulating film 80 adjacent cited first conductive region 30’ of doped polysilicon material is cited to read on the claimed “first passivation film” because it is a film of silicon nitride material adjacent the cited first conductive region 30’ of doped polysilicon material; the bottom half of the cited first insulating film 80 is cited to read on the claimed “first antireflection film” because it is a film of silicon nitride material) and
a second passivation film is located on a surface of the second conductive region opposite the semiconductor substrate (40 depicted in Fig. 3 as located on a top surface of the second conductive region 30 opposite the semiconductor substrate 10).
Chen et al. teaches the first conductive region being n-type and the second conductive region being p-type (see [0015] and [0035]) and teaches the first passivation film is silicon nitride (see [0031] and [0033]) but does not teach wherein the second passivation film is aluminum oxide.
However, Shin et al. discloses a solar cell (see Title and Abstract) and teaches a passivation film 22 can be formed of aluminum oxide (see Fig. 1 and see [0035]).
Thus, at the time of the invention, it would have been obvious to a person having ordinary skill in the art to have selected the aluminum oxide material exemplified by Shin et al. for the material of the second passivation film of Chen et al. because the selection of a material based on its suitability for its intended use supports a prima facie obviousness determination (see MPEP 2144.07).
Chen et al., as modified above, teaches the claimed “wherein the first and second passivation films have fixed positive charges for the first and second conductive regions being n-type regions and fixed negative charges for the first and second conductive regions being p-type regions” because Chen et al., as modified above, teaches the first conductive region being n-type and the second conductive region being p-type (see [0015] and [0035]), teaches the first passivation film is silicon nitride (see [0031] and [0033]), and teaches the second passivation film is aluminum oxide (recall selection of aluminum oxide material of Shin et al.).
With regard to claim 2, independent claim 1 is obvious over Chen et al. in view of Shin et al. under 35 U.S.C. 103 as discussed above. Chen et al. discloses wherein
a width of the first part is greater than that of the first electrode (as depicted in Fig. 3, a horizontal width of the cited first part 33 is greater than that of the cited first electrode 70).
With regard to claim 3, independent claim 1 is obvious over Chen et al. in view of Shin et al. under 35 U.S.C. 103 as discussed above. Chen et al. discloses wherein
the thickness of the first part is greater than that of the second part (as depicted in Fig. 3, the cited vertical thickness of the first part 33 is greater than that of the second part 34).
With regard to claim 4, dependent claim 3 is obvious over Chen et al. in view of Shin et al. under 35 U.S.C. 103 as discussed above. Chen et al. discloses wherein
the thickness of the first part ranges from 100 nm to 200 nm (see [0030] exemplifying 80-300 nm and specifically 80, 120, 170, and 200 nm).
With regard to claim 5, independent claim 1 is obvious over Chen et al. in view of Shin et al. under 35 U.S.C. 103 as discussed above. Chen et al. discloses wherein
the thickness of the second part is less than 50 nm (see [0030] exemplifying 10-80 nm and specifically 10, 20, and 30 nm).
With regard to claim 6, independent claim 1 is obvious over Chen et al. in view of Shin et al. under 35 U.S.C. 103 as discussed above. Chen et al. discloses wherein
the first major surface is a back surface of the semiconductor substrate and the first conductive region is doped with a dopant of a same conductivity type as the semiconductor substrate (as depicted in Fig. 3, the cited first major bottom surface is a back surface of the semiconductor substrate 10 and the first conductive region 30’ is doped with a dopant of a same conductivity type as the semiconductor substrate 10; see [0035]).
With regard to claim 9, independent claim 1 is obvious over Chen et al. in view of Shin et al. under 35 U.S.C. 103 as discussed above. Chen et al. discloses wherein
the second major surface of the semiconductor substrate is a front surface of the semiconductor substrate and the first major surface of the semiconductor substrate is a back surface of the semiconductor substrate (see Fig. 3 depicting the cited second major top surface of the semiconductor substrate 10 is a front surface of the semiconductor substrate and the cited first major bottom surface of the semiconductor substrate 10 is a back surface of the semiconductor substrate), and
unevenness is not formed on the back surface of the semiconductor substrate (see Fig. 3)
With regard to claim 10, independent claim 1 is obvious over Chen et al. in view of Shin et al. under 35 U.S.C. 103 as discussed above.
Chen et al. does not disclose wherein a width of the first part is greater than that of the first electrode by 10 µm to 200 µm.
However, the width of the first part and first electrode is a result effective variable directly affecting the recombination loss and contact resistance in the electrode and absorption of light and passivating effects (see [0037]).
Thus, at the time of the invention, it would have been obvious to a person having ordinary skill in the art to have optimized the width of the first part and first electrode in the solar cell of Chen et al. and arrive at the claimed range of 10 µm to 200 µm through routine experimentation (see MPEP 2144.05); especially since it would have led to optimizing the recombination loss and contact resistance in the electrode and absorption of light and passivating effects.
With regard to claim 21, independent claim 1 is obvious over Chen et al. in view of Shin et al. under 35 U.S.C. 103 as discussed above. Chen et al. discloses a solar cell, comprising:
a semiconductor substrate having a first major surface and a second major surface (10 depicted in Fig. 3 as having a first major bottom surface and a second major top surface);
a tunneling layer (20’, Fig. 3), wherein
the tunneling layer is located on the first major surface of the semiconductor substrate (as depicted in Fig. 3, the cited tunneling layer 20’ is located on the cited first major bottom surface of the semiconductor substrate 10);
a first conductive region (30’, Fig. 3), wherein
the first conductive region is located on the tunneling layer on a surface of the first tunneling layer opposite the semiconductor substrate (as depicted in Fig. 3, the cited first conductive region 30’ is located on the cited tunneling layer 20’ opposite the semiconductor substrate 10);
a first insulating film (bottom half of 80, Fig. 3), wherein
the first insulating film is located on a surface of the first conductive region opposite the tunneling layer and the first insulating film and passivates the first conductive region; (as depicted in Fig. 3, the cited first insulating film, recall bottom half of 80, is located on a surface of the first conductive region 30’ opposite the tunneling layer 20’ and passivates the cited first conductive region 30’; see [0031] and [0033] teaching “a silicon nitride film layer”);
a second conductive region (30, Fig. 3), wherein
the second conductive region is located at the second major surface of the semiconductor substrate and composed of a doping region (as depicted in Fig. 3, the cited second conductive region 30 is located at the cited second major top surface of the cited semiconductor substrate 10 and composed of a doping region; see [0024]);
a first electrode (70, Fig. 3), wherein
the first electrode is connected to the first conductive region (as depicted in Fig. 3, the cited first electrode 70 is connected to the cited first conductive region 30’) and
is formed through the first insulating film by firing of metal material (the cited first electrode 70 is cited to read on the claimed product-by-process limitation “is formed through the first insulating film by firing of metal material” because the cited first electrode 70 is formed through the cited first insulating film, recall bottom half of 80, and includes metal material; see [0012]); and
a second electrode (50, Fig. 3), wherein
the second electrode is connected to the second conductive region (as depicted in Fig. 3, the cited second electrode 50 is connected to the cited second conductive region 30), wherein
the first conductive region comprises a first part connected to the first electrode (as depicted in Fig. 3, the cited first conductive region 30’ comprises a first part 33 connected to the cited first electrode 70) and
a second part other than the first part (as depicted in Fig. 3, a second part 34 other than the first part 33), and
a thickness of the first part is different from that of the second part (as depicted in Fig. 3, a vertical thickness of the first part 33 is different from that of the second part 34); and wherein
a thickness of the first part of the first conductive region is configured so that the tunneling layer is protected from penetration of the first metal material (the cited thickness of the cited first part 33 is cited to read on the claimed “is configured so that the tunneling layer is protected from penetration of the first metal material” because it forms a thickness of material at 33 which is a physical barrier between the cited first electrode 70 and the cited tunnel laying 20’ and is a thickness that is greater than the thickness of the cited second part 34), further comprising
an antireflection film, wherein the antireflection film is located on a surface of the first insulating film opposite the first conductive region (such as the top half of 80 depicted in Fig. 3 as located on a top surface of the cited first insulating film, bottom top half of 80, opposite the cited first conductive region 30’; see [0031] and [0033] teaching “a silicon nitride film layer”); wherein
the first insulating film is a first passivation film and a first antireflection film (see Fig. 3 depicting cited first insulating film adjacent cited first conductive region 30’ of doped polysilicon material and see [0033] teaching a “silicon nitride film layer”; the top half of the cited first insulating film adjacent cited first conductive region 30’ of doped polysilicon material is cited to read on the claimed “first passivation film” because it is a film of silicon nitride material adjacent the cited first conductive region 30’ of doped polysilicon material; the bottom half of the cited first insulating film is cited to read on the claimed “first antireflection film” because it is a film of silicon nitride material) and
a second passivation film is located on a surface of the second conductive region opposite the semiconductor substrate (40 depicted in Fig. 3 as located on a top surface of the second conductive region 30 opposite the semiconductor substrate 10).
Chen et al. teaches the first conductive region being n-type and the second conductive region being p-type (see [0015] and [0035]) and teaches the first passivation film is silicon nitride (see [0031] and [0033]) but does not teach wherein the second passivation film is aluminum oxide.
However, Shin et al. discloses a solar cell (see Title and Abstract) and teaches a passivation film 22 can be formed of aluminum oxide (see Fig. 1 and see [0035]).
Thus, at the time of the invention, it would have been obvious to a person having ordinary skill in the art to have selected the aluminum oxide material exemplified by Shin et al. for the material of the second passivation film of Chen et al. because the selection of a material based on its suitability for its intended use supports a prima facie obviousness determination (see MPEP 2144.07).
Chen et al., as modified above, teaches the claimed “wherein the first and second passivation films have fixed positive charges for the first and second conductive regions being n-type regions and fixed negative charges for the first and second conductive regions being p-type regions” because Chen et al., as modified above, teaches the first conductive region being n-type and the second conductive region being p-type (see [0015] and [0035]), teaches the first passivation film is silicon nitride (see [0031] and [0033]), and teaches the second passivation film is aluminum oxide (recall selection of aluminum oxide material of Shin et al.).
With regard to claims 13 and 20, Chen et al. discloses a method for manufacturing a solar cell, comprising:
providing a semiconductor substrate having a first major surface and a second major surface (10 depicted in Fig. 3 as having a first major bottom surface and a second major top surface);
forming a tunneling layer on the first surface of the semiconductor substrate (as depicted in Fig. 3, forming a tunneling layer 20’ on the first major surface of the semiconductor substrate 10);
forming an intrinsic semiconductor layer on the first tunneling layer and doping the intrinsic semiconductor layer with a first-conductivity- type dopant to form a first conductive region (see Fig. 3 depicting forming a first conductive region 30’ on the cited tunneling layer 20’; while Chen et al. does not teach the cited first conductive region 30’ is formed by forming an intrinsic layer and doping the intrinsic layer, it would have been obvious to a person having ordinary skill in the art to have tried forming the first conductive region by forming an intrinsic layer and doping the intrinsic layer because it is one in a finite number of immediately recognizable options, finite options being forming the first conductive region by forming a doped semiconductor layer or forming the first conductive region by forming an intrinsic semiconductor layer and doping the intrinsic semiconductor layer, within the technical grasp of a skilled artesian, see MPEP 2143 E);
partially etching a second part of the first conductive region other than a first part of the first conductive region to form a step (see Fig. 3 depicting a second part 34 of the first conductive region 30’ other than a first part 33 which forms a step; see [0030] teaching local etching);
doping the second major surface of the semiconductor substrate with a second-conductivity-type dopant to form a second conductive region composed of a doping region (such as depicted in Fig. 3, a second conductive region 30 on the cited second major surface of the semiconductor substrate 10 cited to read on the claimed “doping the other side of the semiconductor substrate with a second-conductivity-type dopant to form a second conductive region composed of a doping region” as the other top side of the semiconductor substrate includes doped second conductive region 30);
forming a first insulating film covering the first conductive region (as depicted in Fig. 3, forming a first insulating film 80 covering the cited first conductive region 30’); and
forming a first electrode connected to the first part of the first conductive region (as depicted in Fig. 3, a first electrode 70 connected to the first part 33 of the first conductive region 30’), wherein
the first electrode is formed through the first insulating film and is of metal material (as depicted in Fig. 3, the cited first electrode 70 is formed though the cited first insulating film 80 and is of metal material; see [0012]); and
forming a second electrode connected to the second conductive region (as depicted in Fig. 3, a second electrode 50 connected to the second conductive region 30); wherein
the first insulating film is a first passivation film and a first antireflection film (see Fig. 3 depicting cited first insulating film 80 adjacent cited first conductive region 30’ and see [0033] teaching a “silicon nitride film layer” see Fig. 3 depicting cited first insulating film 80 adjacent cited first conductive region 30’ of doped polysilicon material and see [0033] teaching a “silicon nitride film layer”; the top half of the cited first insulating film 80 adjacent cited first conductive region 30’ of doped polysilicon material is cited to read on the claimed “first passivation film” because it is a film of silicon nitride material adjacent the cited first conductive region 30’ of doped polysilicon material; the bottom half of the cited first insulating film 80 is cited to read on the claimed “first antireflection film” because it is a film of silicon nitride material) and
a second passivation film is located on a surface of the second conductive region opposite the semiconductor substrate (40 depicted in Fig. 3 as located on a top surface of the second conductive region 30 opposite the semiconductor substrate 10).
Chen et al. teaches the first conductive region being n-type and the second conductive region being p-type (see [0015] and [0035]) and teaches the first passivation film is silicon nitride (see [0031] and [0033]) but does not teach wherein the second passivation film is aluminum oxide.
However, Shin et al. discloses a solar cell (see Title and Abstract) and teaches a passivation film 22 can be formed of aluminum oxide (see Fig. 1 and see [0035]).
Thus, at the time of the invention, it would have been obvious to a person having ordinary skill in the art to have selected the aluminum oxide material exemplified by Shin et al. for the material of the second passivation film of Chen et al. because the selection of a material based on its suitability for its intended use supports a prima facie obviousness determination (see MPEP 2144.07).
Chen et al., as modified above, teaches the claimed “wherein the first and second passivation films have fixed positive charges for the first and second conductive regions being n-type regions and fixed negative charges for the first and second conductive regions being p-type regions” because Chen et al., as modified above, teaches the first conductive region being n-type and the second conductive region being p-type (see [0015] and [0035]), teaches the first passivation film is silicon nitride (see [0031] and [0033]), and teaches the second passivation film is aluminum oxide (recall selection of aluminum oxide material of Shin et al.).
Chen et al. does not disclose wherein forming the first electrode comprises coating the first insulating film on the first part with a metal paste and firing through the metal paste such that the metal paste penetrates through the first insulating film and is in contact with the first part.
However, Shin et al. discloses a method of manufacturing a solar cell (see Title and Abstract) and teaches a first electrode can be formed by coating a first insulating film on a first part with a metal paste and firing through the metal paste such that the metal paste penetrates through the first insulating film and is in contact with the first part (see [0045]). Shin et al. teaches the fire through method avoids additional steps of forming an opening (see [0045]).
Thus, at the time of the invention, it would have been obvious to a person having ordinary skill in the art to have modified the step of forming the first electrode in the method of Chen et al., as modified above, to include the fire through technique of Shin et al. because it would have avoided additional steps of forming openings.
Chen et al., as modified above, discloses a thickness of the first part of the first conductive region is configured so that the tunneling layer is protected from penetration of the fired metal material (the cited thickness of the cited first part 33 is cited to read on the claimed “is configured so that the tunneling layer is protected from penetration of the fired metal material” because it forms a thickness of material at 33 which is a physical barrier between the cited first electrode 70 and the cited tunnel laying 20’ and is a thickness that is greater than the thickness of the cited second part 34).
With regard to claim 22, Chen et al. discloses a method for manufacturing a solar cell, comprising:
providing a semiconductor substrate having a first major surface and a second major surface (10 depicted in Fig. 3 as having a first major bottom surface and a second major top surface);
forming a tunneling layer on the first surface of the semiconductor substrate (as depicted in Fig. 3, forming a tunneling layer 20’ on the first major surface of the semiconductor substrate 10);
forming an intrinsic semiconductor layer on the first tunneling layer and doping the intrinsic semiconductor layer with a first-conductivity- type dopant to form a first conductive region (see Fig. 3 depicting forming a first conductive region 30’ on the cited tunneling layer 20’; while Chen et al. does not teach the cited first conductive region 30’ is formed by forming an intrinsic layer and doping the intrinsic layer, it would have been obvious to a person having ordinary skill in the art to have tried forming the first conductive region by forming an intrinsic layer and doping the intrinsic layer because it is one in a finite number of immediately recognizable options, finite options being forming the first conductive region by forming a doped semiconductor layer or forming the first conductive region by forming an intrinsic semiconductor layer and doping the intrinsic semiconductor layer, within the technical grasp of a skilled artesian, see MPEP 2143 E);
partially etching a second part of the first conductive region other than a first part of the first conductive region to form a step (see Fig. 3 depicting a second part 34 of the first conductive region 30’ other than a first part 33 which forms a step; see [0030] teaching local etching);
doping the second major surface of the semiconductor substrate with a second-conductivity-type dopant to form a second conductive region composed of a doping region (such as depicted in Fig. 3, a second conductive region 30 on the cited second major surface of the semiconductor substrate 10 cited to read on the claimed “doping the other side of the semiconductor substrate with a second-conductivity-type dopant to form a second conductive region composed of a doping region” as the other top side of the semiconductor substrate includes doped second conductive region 30);
forming a first insulating film covering the first conductive region (as depicted in Fig. 3, forming a first insulating film, the top half of 80, covering the cited first conductive region 30’); and
forming a first electrode connected to the first part of the first conductive region (as depicted in Fig. 3, a first electrode 70 connected to the first part 33 of the first conductive region 30’), wherein
the first electrode is formed through the first insulating layer and is of metal material (as depicted in Fig. 3, the cited first electrode 70 is formed though the cited first insulating layer, recall the top half of 80, and is of metal material; see [0012]); and
forming a second electrode connected to the second conductive region (as depicted in Fig. 3, a second electrode 50 connected to the second conductive region 30), further comprising
forming an antireflection film covering the first insulating film (such as the bottom half of 80 depicted in Fig. 3 as covering the cited first insulating film, recall top half of 80; see [0031] and [0033] teaching “a silicon nitride film layer”); wherein
the first insulating film is a first passivation film and a first antireflection film (see Fig. 3 depicting cited first insulating film adjacent cited first conductive region 30’ of doped polysilicon material and see [0033] teaching a “silicon nitride film layer”; the top half of the cited first insulating film adjacent cited first conductive region 30’ of doped polysilicon material is cited to read on the claimed “first passivation film” because it is a film of silicon nitride material adjacent the cited first conductive region 30’ of doped polysilicon material; the bottom half of the cited first insulating film is cited to read on the claimed “first antireflection film” because it is a film of silicon nitride material) and
a second passivation film is located on a surface of the second conductive region opposite the semiconductor substrate (40 depicted in Fig. 3 as located on a top surface of the second conductive region 30 opposite the semiconductor substrate 10).
Chen et al. teaches the first conductive region being n-type and the second conductive region being p-type (see [0015] and [0035]) and teaches the first passivation film is silicon nitride (see [0031] and [0033]) but does not teach wherein the second passivation film is aluminum oxide.
However, Shin et al. discloses a solar cell (see Title and Abstract) and teaches a passivation film 22 can be formed of aluminum oxide (see Fig. 1 and see [0035]).
Thus, at the time of the invention, it would have been obvious to a person having ordinary skill in the art to have selected the aluminum oxide material exemplified by Shin et al. for the material of the second passivation film of Chen et al. because the selection of a material based on its suitability for its intended use supports a prima facie obviousness determination (see MPEP 2144.07).
Chen et al., as modified above, teaches the claimed “wherein the first and second passivation films have fixed positive charges for the first and second conductive regions being n-type regions and fixed negative charges for the first and second conductive regions being p-type regions” because Chen et al., as modified above, teaches the first conductive region being n-type and the second conductive region being p-type (see [0015] and [0035]), teaches the first passivation film is silicon nitride (see [0031] and [0033]), and teaches the second passivation film is aluminum oxide (recall selection of aluminum oxide material of Shin et al.).
Chen et al. does not disclose wherein forming the first electrode comprises coating the first insulating film on the first part with a metal paste and firing through the metal paste such that the metal paste penetrates through the first insulating film and is in contact with the first part.
However, Shin et al. discloses a method of manufacturing a solar cell (see Title and Abstract) and teaches a first electrode can be formed by coating a first insulating film on a first part with a metal paste and firing through the metal paste such that the metal paste penetrates through the first insulating film and is in contact with the first part (see [0045]). Shin et al. teaches the fire through method avoids additional steps of forming an opening (see [0045]).
Thus, at the time of the invention, it would have been obvious to a person having ordinary skill in the art to have modified the step of forming the first electrode in the method of Chen et al., as modified above, to include the fire through technique of Shin et al. because it would have avoided additional steps of forming openings.
Chen et al., as modified above, discloses a thickness of the first part of the first conductive region is configured so that the tunneling layer is protected from penetration of the fired metal material (the cited thickness of the cited first part 33 is cited to read on the claimed “is configured so that the tunneling layer is protected from penetration of the fired metal material” because it forms a thickness of material at 33 which is a physical barrier between the cited first electrode 70 and the cited tunnel laying 20’ and is a thickness that is greater than the thickness of the cited second part 34).
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 210897294 U included in Applicant submitted IDS filed October 17, 2024) in view of Shin et al. (U.S. Pub. No. 2014/0311562 A1), and in further view of Korevaar et al. (U.S. Pub. No. 2008/0173347 A1).
With regard to claim 7, independent claim 1 is obvious over Chen et al. in view of Shin et al. under 35 U.S.C. 103 as discussed above.
Chen et al. does not disclose wherein unevenness is formed on the first and second major surfaces of the semiconductor substrate.
However, Korevaar et al. disclose a solar cell (see Title and Abstract) and teaches texturing a planar surface can reduce undesirable light reflection and elongate the optical path length (see [0078]).
Thus, at the time of the invention, it would have been obvious to a person having ordinary skill in the art to have modified the first and second major surfaces of the semiconductor substrate of Chen et al. to include texturing, as suggested by Korevaar et al., because it would have provided for reducing undesirable light reflection and elongating the optical path length.
With regard to claim 8, dependent claim 7 is obvious over Chen et al. in view of Shin et al. and Korevaar et al. under 35 U.S.C. 103 as discussed above. Chen et al. discloses further comprising:
a second insulating film (40, Fig. 3), wherein
the second insulating film is located on a surface of the second conductive region opposite the semiconductor substrate (as depicted in Fig. 3, the cited second insulating film 40 is located on a surface of the second conductive region 30 opposite the semiconductor substrate 10).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 210897294 U included in Applicant submitted IDS filed October 17, 2024) in view of Shin et al. (U.S. Pub. No. 2014/0311562 A1), and in further view of Li et al (CN 214043679 U).
With regard to claim 11, independent claim 1 is obvious over Chen et al. in view of Shin et al. under 35 U.S.C. 103 as discussed above.
Chen et al. does not disclose wherein the first passivation film extends onto a side surface of the semiconductor substrate.
However, Li et al. discloses a solar cell (see Title and Abstract) and teaches an antireflection layer can extend onto side surfaces of a semiconductor substrate in order to improve passivation performance on the side surfaces (see Fig. 2 and [0030]).
Thus, at the time of the invention, it would have been obvious to a person having ordinary skill in the art to have modified the anti-reflection layer 80 of Chen et al. to include extension on the side surfaces of the semiconductor substrate, as suggested by Li et al. because it would have provided for improving passivation performance on the side surfaces.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 210897294 U included in Applicant submitted IDS filed October 17, 2024) in view of Shin et al. (U.S. Pub. No. 2014/0311562 A1), and in further view of Lee et al. (U.S. Pub. No. 2018/0212082 A1).
With regard to claim 12, independent claim 1 is obvious over Chen et al. in view of Shin et al. under 35 U.S.C. 103 as discussed above.
Chen et al. discloses wherein the first electrode penetrates through the first insulating film and the first part of the first conductive region is formed corresponding to the first electrode (see Fig. 3 depicting the first electrode 70 penetrates through the first passivation film at 80 and the first part 33 of the first conductive region 30’ is formed corresponding to the first electrode 70).
Chen et al. does not disclose wherein the first electrode comprises finger electrodes and busbar electrodes.
However, Lee et al. discloses a solar cell (see Title and Abstract) and teaches a first electrode can conventionally include finger electrodes and busbar electrodes (see Fig. 1-2 and [0043]).
Thus, at the time of the invention, it would have been obvious to a person having ordinary skill in the art to have substituted the first electrode of Chen et al. for the first electrode of Lee et al., which includes the cited finger and busbar electrodes, because the simple substitution of a known element known in the art to perform the same function, in the instant case a first electrode, supports a prima facie obviousness determination (see MPEP 2143 B).
Claim(s) 14 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 210897294 U included in Applicant submitted IDS filed October 17, 2024) in view of Shin et al. (U.S. Pub. No. 2014/0311562 A1), and in further view of Fujimoto et al. (WO 2020/149128 A1).
With regard to claim 14 and 16, independent claim 13 is obvious over Chen et al. in view of Shin et al. under 35 U.S.C. 103 as discussed above.
Chen et al. teaches selective etching (recall [0030]) but does not disclose wherein forming the step in the first conductive region comprises forming a mask layer, using an etching solution, and removing the mask layer.
However, Fujimoto et al. discloses a method of manufacturing a solar cell (see Title and Abstract) and teaches selective etching conventionally includes forming a mask layer on the part not etched, removing, using an alkaline etching solution, the exposed part to a predetermined thickness, and removing the mask (see [0030-0031]).
Thus, at the time of the invention, it would have been obvious to a person having ordinary skill in the art to have substituted the selective etching technique of Chen et al. for the selective etching technique of Fujimoto et al. because the simple substitution of a known element known in the art to perform the same function, in the instant case a selective etching technique, supports a prima facie obviousness determination (see MPEP 2143 B).
Claim(s) 15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 210897294 U included in Applicant submitted IDS filed October 17, 2024) in view of Shin et al. (U.S. Pub. No. 2014/0311562 A1), and in further view of Buchholz et al. (EP 3982421 A1).
With regard to claim 15 and 17, independent claim 13 is obvious over Chen et al. in view of Shin et al. under 35 U.S.C. 103 as discussed above.
Chen et al. teaches selective etching (recall [0030]) but does not disclose wherein forming the step in the first conductive region comprises irradiating the first part of the first conductive region with a laser to change a crystalline structure of the first part and etching the second part to a predetermined thickness.
However, Buchholz et al. discloses a method of manufacturing a solar cell (see Title and Abstract) and teaches selective etching conventionally includes irradiating a first part not meant to be etched with a laser to change a crystalline structure of the first part and etching a second part to a predetermined thickness in an alkaline solution (see Fig. 1 and see [0041]).
Thus, at the time of the invention, it would have been obvious to a person having ordinary skill in the art to have substituted the selective etching technique of Chen et al. for the selective etching technique of Buchholz et al. because the simple substitution of a known element known in the art to perform the same function, in the instant case a selective etching technique, supports a prima facie obviousness determination (see MPEP 2143 B).
Response to Arguments
Applicant's arguments filed December 10, 2025 have been fully considered but they are not persuasive.
Applicant notes the newly added claimed limitations are not found within the previously cited prior art references. However, this argument is addressed in the rejections of the claims above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DUSTIN Q DAM/Primary Examiner, Art Unit 1721 January 8, 2026
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