DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/22/2025 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Dentoni Litta et al., hereinafter Dentoni (US 2021/0193821 A1) in view of Wu et al., hereinafter Wu (US 2020/0168715 A1) and Lan (US 11,257,903 B2)
Re claim 1: Dentoni teaches (fig.8a) an integrated circuit structure, comprising: a backbone (104 is a dielectric, p.54); a first transistor device (10a is a FET device region, p.61) comprising a first vertical stack of semiconductor channels (102a are a stack of nanosheets, p.52) adjacent to a first edge (right edge of 104;hereinafter “1E”) of the backbone (104); and a second transistor device (30a is another FET device region) comprising a second vertical stack (102c) of semiconductor channels adjacent to a second edge (left edge of 104; hereinafter “2E”) of the backbone (104) opposite the first edge (1E) ;
a first gate structure (gate structure mentioned in par.95 partially wrapping around 102a hereinafter GS1) around the first vertical stack of semiconductor channels (102a);
and a second gate structure (gate structure mentioned in par.95 partially wrapping around 102c hereinafter GS2) around the second vertical stack of semiconductor channels (102c), wherein the backbone (104) separates the second gate structure (GS2) from the first gate structure (GS1).
Dentoni is silent to explicitly teach a second gate structure (gate structure mentioned in par.95 partially wrapping around 102c hereinafter GS2) around the second vertical stack of semiconductor channels (102c), wherein the backbone (104) completely separates the second gate structure (GS2) from the first gate structure (GS1).
Lan teaches (fig.2G-2) a second gate structure (160-2 on left side) around the second vertical stack of semiconductor channels (stack of 108-1 and 108-2), wherein the backbone (126 124 and 122, hereinafter BK) completely separates the second gate structure (160-2 on left side) from the first gate structure (160-2 on right side).
It would have been obvious to one of ordinary skill in the art before the effective filing date to include the backbone Bk as taught in Lan that extends to completely separate a first and second gate structure in the device of Dentoni in order to have the predictable result of improved isolation between two vertical stacks of semiconductor channels to reduce bulk leakage and improve efficiency of the device.
Dentoni in view of Lan is silent to teach the second vertical stack of semiconductor channels comprising a greater number of semiconductor channels than the first vertical stack of semiconductor channels.
Wu teaches (fig.28B) a second vertical stack of semiconductor channels (407a) comprising a greater number (there are 4 channels in 407a vs 3 channels in 407c or 407b) of semiconductor channels than the first vertical stack of semiconductor channels (407c or 407b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the modulation of nanosheet channels of Wu in the device of Dentoni in view of Lan order to have the predictable result of providing flexibility in the design of the device to optimize and improve circuit performance and power usage of the device based on design requirements. (p.56 of Wu)
Re claim 2: Dentoni in view of Wu and Lan teaches the integrated circuit structure of claim 1, wherein a topmost semiconductor channel (407b of Wu would be in 10a of Dentoni) of the first transistor (10a of Dentoni) is co-planar with a topmost semiconductor channel (407a of Wu would be in 30a of Dentoni) of the second transistor (30a of Dentoni).
Re claim 3: Dentoni in view of Wu and Lan teaches the integrated circuit structure of claim 1, wherein a bottommost semiconductor channel (407b or 407c of Wu) of the first transistor (10a of Dentoni) is co-planar with a bottommost semiconductor channel (407a of Wu) of the second transistor (30a of Dentoni).
Re claim 4: Dentoni in view of Wu and Lan teaches the integrated circuit structure of claim 1, wherein the first transistor device (10a) is a P-type device (p.16).
Re claim 5: Dentoni in view of Wu and Lan teaches the integrated circuit structure of claim 4, wherein the second transistor device (30a) is an N-type device (30a can be different dopant from the first dopant, p.66).
Re claim 6: Dentoni in view of Wu and Lan teaches the integrated circuit structure of claim 1, wherein the first vertical stack of semiconductor channels (407c or 407b of Wu) and the second vertical stack of semiconductor channels (407a of Wu) are nanowires. (Wu teaches the width of the channels can span from 4-100 nm, p.25, and nanowires are commonly known to be 1-200 nm in width.)
Re claim 7: Dentoni in view of Wu and Lan teaches the integrated circuit structure of claim 1, wherein the first vertical stack of semiconductor channels (407c or 407b of Wu) and the second vertical stack of semiconductor channels (407a) are nanoribbons (Wu teaches the width of the channels can span from 4-100 nm, p.25, and nanoribbons are commonly known to be less than 50nm in width.).
Claim(s) 8-20 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw et al. hereinafter Liaw (US 2020/0135740) in view of Wu et al; hereinafter Wu (US 2020/0168715 A1) , Dentoni et al., hereinafter Dentoni (US 2021/0193821 A1) and Lan (US 11,257,903 B2) .
Re claim 8: Liaw teaches (fig.2-2C) A static random-access memory (SRAM) cell (200), comprising: a pair of pass-gate (PG) transistors (pass-gate nodes 202/204,p.23), wherein individual ones of the PG transistors (202) comprise a first stack of semiconductor channels (stack of channels in PG node 202 hereinafter 202C); a pair of pull-up (PU) transistors (pull up nodes 206,208,p.23), wherein individual ones of the PU transistors (206,208) comprise a second stack of semiconductor channels (stack of channels in PG node 206 (not labeled but mentioned in p.23) ; hereinafter 206C ; and a pair of pull-down (PD) transistors (pull-down nodes 210 and 212,p.23), wherein individual ones of the PD transistors (210 and 212) comprise a third stack of semiconductor channels (stack of channels in PD node 212 ; hereinafter 212C),
Liaw is silent to teach wherein a number of semiconductor channels in the second stack is smaller than a number of semiconductor channels in the first stack or the third stack, wherein a first of the PU transistors and a first of the PD transistors are adjacent first and second edges of a first backbone, and wherein a second of the PU transistors and a second of the PD transistors are adjacent first and second edges of a second backbone;
wherein the first backbone separates a gate structure of the first of the PU transistors from a gate structure of the first of the PD transistors, and wherein the second backbone completely separates a gate structure of the second of the PU transistors from a gate structure of the second of the PD transistors.
Wu in view of Liaw teaches (fig.28A) a number (3) of semiconductor channels (407b of Wu would be in stack 206C of Liaw) in the second stack (206C of Liaw) is smaller than a number (4) of semiconductor channels (407a of Wu would be in stack 202C of Liaw) in the first stack (202C) or the third stack (407c of Wu would be in third stack 212C of Liaw)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the modulation of nanosheet channels of Wu in the device of Liaw in order to have the predictable result of providing flexibility in the design of the device to optimize and improve circuit performance and power usage of the device based on design requirements. (p.56 of Wu)
Liaw in view of Dentoni teaches (fig.8a of Dentoni) wherein a first of the PU transistors (206 of Liaw) and a first of the PD transistors (210 of Liaw) are adjacent first (right edge of 104; hereinafter “1E” of Dentoni) and second (left edge of 104; hereinafter “2E” of Dentoni) edges of a first backbone (104 of Dentoni in between 206 and 210 of Liaw; hereinafter 1B),
and wherein a second of the PU transistors (208 of Liaw) and a second of the PD transistors (212 of Liaw) are adjacent first (right edge of 104; hereinafter “1E” of Dentoni) and second (left edge of 104; hereinafter “2E” of Dentoni) edges of a second backbone (104 of Dentoni in between 208 and 212 of Liaw; hereinafter 2B);
wherein the first backbone (1B of Dentoni) separates a gate structure (gate around 206 ,p.23 mentions 206 is a gate all around (GAA) transistor , hereinafter GS1 of Liaw) of the first of the PU transistors (206 of Liaw) from a gate structure (gate structure of 210, p.23 mentions 210 is GAA transistor, hereinafter GS2 of Liaw) of the first of the PD transistors (210 of Liaw), and wherein the second backbone (2B of Dentoni) separates a gate structure (gate structure around 208, p.23 mentions 208 is a GAA transistor, hereinafter GS3 of Liaw) of the second of the PU transistors (208 of Liaw) from a gate structure (gate structure around 208, p.23 mentions 208 is a GAA transistor, hereinafter GS4 of Liaw) of the second of the PD transistors (212 of Liaw).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the backbone of Dentoni in between the PD and PU transistors of the device of Liaw in order to have the predictable result of increasing the electrical isolation and improving the electrical separation of the devices while forming the devices closer together to save on space. (p.31 of Dentoni)
Liaw in view of Dentoni are silent to teach wherein the first backbone (1B of Dentoni) separates a gate structure (gate around 206 ,p.23 mentions 206 is a gate all around (GAA) transistor , hereinafter GS1 of Liaw) of the first of the PU transistors (206 of Liaw) from a gate structure (gate structure of 210, p.23 mentions 210 is GAA transistor, hereinafter GS2 of Liaw) of the first of the PD transistors (210 of Liaw), and wherein the second backbone (2B of Dentoni) completely separates a gate structure (gate structure around 208, p.23 mentions 208 is a GAA transistor, hereinafter GS3 of Liaw) of the second of the PU transistors (208 of Liaw) from a gate structure (gate structure around 208, p.23 mentions 208 is a GAA transistor, hereinafter GS4 of Liaw) of the second of the PD transistors (212 of Liaw).
Lan teaches (fig.2G-2) a second gate structure (160-2 on left side) around the second vertical stack of semiconductor channels (stack of 108-1 and 108-2), wherein the backbone (126 124 and 122, hereinafter BK) completely separates the second gate structure (160-2 on left side) from the first gate structure (160-2 on right side).
It would have been obvious to one of ordinary skill in the art before the effective filing date to include the backbone Bk as taught in Lan that extends to completely separate a first and second gate structure in the device of Dentoni in order to have the predictable result of improved isolation between two vertical stacks of semiconductor channels to reduce bulk leakage and improve efficiency of the device.
Re claim 9: Liaw in view of Wu, Dentoni and Lan teach the SRAM cell of claim 8, wherein a topmost semiconductor channel (407b of Wu) in the second stack (206C of Liaw) is aligned with topmost semiconductor channels (407a/407c of Wu) in the first stack (202C of Liaw) and the third stack (212C of Liaw), and wherein bottommost semiconductor channels (407a/407c of Wu) in the first stack (202C of Liaw) and the third stack (212C of Liaw) are aligned with a depopulated region (206C of Liaw would have channels 407b of Wu where there is a depopulated amount of channels compared to 407a and 407c of Wu; therefore the entire stack will be known as a depopulated region DR) in the second stack. (206C of Liaw)
Re claim 10: : Liaw in view of Wu and Dentoni teaches the SRAM cell of claim 8, wherein a bottommost semiconductor channel (407b of Wu) in the second stack (206C of Liaw) is aligned with bottommost semiconductor channels (407a/407c of Wu) in the first stack (202C of Liaw) and the third stack (212C of Liaw), and wherein topmost semiconductor channels (407a/407c of Wu) in the first stack (202C of Liaw) and the third stack (212C of Liaw) are aligned with a depopulated region (206C of Liaw would have channels 407b of Wu where there is a depopulated amount of channels compared to 407a and 407c of Wu; therefore the entire stack will be known as a depopulated region DR) in the second stack (206C of Liaw).
Re claim 11: Liaw in view of Wu and Dentoni teaches the SRAM cell of claim 8, wherein semiconductor channels (407a-c of Wu) are nanowires. (Wu teaches the width of the channels can span from 4-100 nm, p.25, and nanowires are commonly known to be 1-200 nm in width.)
Re claim 12: Liaw in view of Wu and Dentoni teaches the SRAM cell of claim 8, wherein semiconductor channels (407a-c of Wu) are nanoribbons. (Wu teaches the width of the channels can span from 4-100 nm, p.25, and nanoribbons are commonly known to be less than 50nm in width.)
Re claim 13: Liaw teaches (fig.2A and 6) a computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure. (The device of Liaw is within a SOC, commonly known to be used in computing devices such as phones and PCs that contain a board and multiple components such as an IC structure);
a first transistor device (pull up node 208, p.23) comprising a first vertical stack of semiconductor channels (stack of channels 253 in PG node 208; hereinafter 253c)
and a second transistor device (pull-down node 212, p.23) comprising a second vertical stack of semiconductor channels (stack of channels 255; hereinafter 255C)
Liaw is silent to teach an integrated circuit structure, comprising: a backbone; a first transistor device comprising a first vertical stack of semiconductor channels adjacent to a first edge of the backbone; and a second transistor device comprising a second vertical stack of semiconductor channels adjacent to a second edge of the backbone opposite the first edge, the second vertical stack of semiconductor channels comprising a greater number of semiconductor channels than the first vertical stack of semiconductor channels;
a first gate structure around the first vertical stack of semiconductor channels; and a second gate structure around the second vertical stack of semiconductor channels, wherein the backbone completely separates the second gate structure from the first gate structure.
Dentoni teaches (fig.8a) an integrated circuit structure, comprising: a backbone (104 is a dielectric, p.80); a first transistor device (10a is a FET region, p.61) comprising a first vertical stack of semiconductor channels (102a are a stack of nanosheets, p.52) adjacent to a first edge (right edge of 104;hereinafter “1E”) of the backbone (104); and a second transistor device (30a is another FET device region) comprising a second vertical stack (102c) of semiconductor channels adjacent to a second edge (left edge of 104; hereinafter “2E”) of the backbone (104) opposite the first edge (1E)
a first gate structure (gate structure mentioned in par.95 partially wrapping around 102a hereinafter GS1) around the first vertical stack of semiconductor channels (102a); and a second gate structure (gate structure mentioned in par.95 partially wrapping around 102c hereinafter GS2) around the second vertical stack of semiconductor channels (102c), wherein the backbone (104) separates the second gate structure (GS2) from the first gate structure (GS1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the first and second stack of channels and backbone of Dentoni in between the PD and PU transistors of the device of Liaw in order to have the predictable result of increasing the electrical isolation and improving the electrical separation of the devices while forming the devices closer together to save on space. (p.31)
Liaw in view of Dentoni is silent to explicitly teach a first gate structure (gate structure mentioned in par.95 partially wrapping around 102a hereinafter GS1 of Dentoni) around the first vertical stack of semiconductor channels (102a of Dentoni); and a second gate structure (gate structure mentioned in par.95 partially wrapping around 102c hereinafter GS2 of Dentoni) around the second vertical stack of semiconductor channels (102c of Dentoni), wherein the backbone (104 of Dentoni) completely separates the second gate structure (GS2 of Dentoni) from the first gate structure (GS1 of Dentoni).
Lan teaches (fig.2G-2) a second gate structure (160-2 on left side) around the second vertical stack of semiconductor channels (stack of 108-1 and 108-2), wherein the backbone (126 124 and 122, hereinafter BK) completely separates the second gate structure (160-2 on left side) from the first gate structure (160-2 on right side).
It would have been obvious to one of ordinary skill in the art before the effective filing date to include the backbone Bk as taught in Lan that extends to completely separate a first and second gate structure in the device of Dentoni in order to have the predictable result of improved isolation between two vertical stacks of semiconductor channels to reduce bulk leakage and improve efficiency of the device.
Wu teaches (fig.28B) a second vertical stack of semiconductor channels (407a) comprising a greater number (there are 4 channels in 407a vs 3 channels in 407c or 407b) of semiconductor channels than the first vertical stack of semiconductor channels (407c or 407b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the modulation of nanosheet channels of Wu in the device of Liaw in view of Dentoni and Lan in order to have the predictable result of providing flexibility in the design of the device to optimize and improve circuit performance and power usage of the device based on design requirements. (p.56 of Wu)
Re claim 14: Liaw in view of Wu, Dentoni and Lan teaches the computing device of claim 13, wherein semiconductor channels (407a-c of Wu) are nanowires. (Wu teaches the width of the channels can span from 4-100 nm, p.25, and nanowires are commonly known to be 1-200 nm in width.)
Re claim 15: Liaw in view of Wu, Dentoni and Lan teaches the computing device of claim 13, wherein semiconductor channels (407a-c of Wu) are nanoribbons. (Wu teaches the width of the channels can span from 4-100 nm, p.25, and nanoribbons are commonly known to be less than 50nm in width.)
Re claim 16: Liaw in view of Wu, Dentoni and Lan teaches the computing device of claim 13, further comprising: a memory coupled to the board. (Liaw contains SRAM cells 200 which is commonly known to be on a board in PCs and phones as discussed in claim 13)
Re claim 17: Liaw in view of Wu, Dentoni and Lan teaches the computing device of claim 13, further comprising: a communication chip coupled to the board (communication chips are commonly found in PCs and phones as discussed in claim 13).
Re claim 18: Liaw in view of Wu, Dentoni and Lan teaches the computing device of claim 13, further comprising: a battery coupled to the board. (Phones and PCs are known to have batteries as discussed in claim 13)
Re claim 19: Liaw in view of Wu, Dentoni and Lan teaches the computing device of claim 13, wherein the component is a packaged integrated circuit die. (SRAM devices are known to be in the form of dies and are known to be packaged)
Re claim 20: Liaw in view of Wu, Dentoni and Lan teaches the computing device of claim 13, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor. (Processors, communication chips, and DSP are commonly found in PCs and phones as discussed in claim 13)
Response to Arguments
Applicant’s arguments with respect to claims 1,8 and 13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/RICKY VERDES/
Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898