Prosecution Insights
Last updated: October 01, 2026
Application No. 18/376,002

MANUFACTURING METHOD OF ELECTRONIC DEVICE

Non-Final OA §103
Filed
Oct 03, 2023
Priority
Nov 04, 2022 — provisional 63/422,443 +1 more
Examiner
ABRAHAM, JOSE K
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Innolux Corporation
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
312 granted / 375 resolved
+15.2% vs TC avg
Strong +33% interview lift
Without
With
+32.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
41 currently pending
Career history
405
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
48.5%
+8.5% vs TC avg
§102
16.2%
-23.8% vs TC avg
§112
31.5%
-8.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 375 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 03 October 2023, 05 August 2025 and 13 April 2023 were filed prior to the mailing date of this office correspondence. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Election/Restrictions Applicant’s election with traverse of Invention I, claims 1-10 in the reply filed on 12 August 2026 is acknowledged. The traversal is on the ground(s) that, “the present application provides a method of transferring electronic elements onto a substrate having recesses through a fluid transfer process, and invention I and invention II merely describe two process embodiments falling within this common inventive concept. Therefore, Applicant believes that it would not require serious burden to examine invention I-II on the merits, all claims 1-20 could be examined simultaneously without serious burden, and the restriction of the claims is not needed.” Examiner respectfully submits that, firstly, as outlined in the Election/Restriction requirement office action, Invention II does not have “identifying a defective working area from the plurality of working areas, wherein at least one of the plurality of first recesses of the defective working area has no electronic unit or a defective first electronic unit disposed therein; and disposing at least one repairing electronic unit in at least one of the plurality of second recesses of the defective working area through laser transfer.” as recited in claim 1; and/or Invention I does not have “providing a second substrate, wherein the second substrate includes a plurality of recesses, and the plurality of recesses have a first pitch… providing a third substrate, wherein the third substrate includes a plurality of working areas, the plurality of working areas have a second pitch, and the second pitch is greater than the first pitch” as recited in claim 11. This results in a divergent search, because a search for one group would require searching for limitations not required by any of the other groups. Thus, different search queries or thought processes must be employed in locating prior art, and a reference applicable against one group is not likely to be directly applicable against another group, and therefore additional searching for any missing limitations would be required. Secondly, if, during prosecution, a linking claim becomes allowable, the withdrawn claims depending therefrom would be rejoined and examined for patentability from a 35 U.S.C. 112 perspective. The requirement is still deemed proper and is therefore made FINAL. Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Xu (US 20230036183) in view of Lin (CN 115472725). PNG media_image1.png 318 433 media_image1.png Greyscale Annotated Figs. 1 and 2, Xu. Regarding claim 1, Xu teaches, a manufacturing method of an electronic device (Figs. 11 and 12, para. [0094-0100]), comprising following steps: providing a substrate (substrate 1, Fig. 11, step 301, providing a substrate 1, para. [0094]), wherein the substrate includes a plurality of working areas (sub-pixel areas 10, Figs. 1 and 11),and each of the plurality of working areas includes a plurality of first recesses (main recess 110) and a plurality of second recesses (backup recess 120); disposing a plurality of first electronic units (micro-LED chips, para. [0096]) in the plurality of first recesses of the plurality of working areas through fluid transfer (step 302, transferring a huge number of main micro-LED chips to the substrate 1 by a fluid mass transfer method, so that the main recess 110 in each of the sub-pixel areas 10 is loaded with one of the main micro-LED chips, para. [0096]); identifying a defective working area from the plurality of working areas, wherein at least one of the plurality of first recesses of the defective working area has no electronic unit or a defective first electronic unit disposed therein (step 303: detecting all of the main micro-LED chips to find the sub-pixel area 10 where the defective pixel is detected, para. [0098]); and disposing at least one repairing electronic unit in at least one of the plurality of second recesses of the defective working area (step 304: transferring a plurality of backup micro-LED chips to the substrate 1 by a fluid mass transfer method, so that the backup recess 120 in each of the sub-pixel areas 10 where the defective pixel is detected is loaded with one of the backup micro-LED chips, para. [0099]). Xu does not teach, disposing the repairing electronic unit through laser transfer. However, Lin teaches, a manufacturing method of an electronic device, including providing a providing a substrate (substrate 100, see annotated Fig. 4 below), wherein the substrate includes a plurality of working areas (see Fig. 2a); disposing a plurality of first electronic units in the plurality of first recesses of the plurality of working areas (see Fig. 2a); identifying a defective working area from the plurality of working areas, wherein at least one of the plurality of first recesses of the defective working area has no electronic unit or a defective first electronic unit disposed therein; and disposing at least one repairing electronic unit in at least one of the plurality of second recesses of the defective working area through laser transfer (step S10 above, determining the coordinates of the defect location that creates the micro-LED void…when the chip used for display on the display substrate is a Micro LED, after mass transfer of the display substrate, multiple unsuccessfully transferred Micro LEDs may be generated on the display substrate... by irradiating the repair substrate 400 with a laser at the coordinates of each defect location, the photolytic material at the corresponding location can be decomposed under the light, and the chip 20 at the corresponding location can be detached from the repair substrate 400 and transferred to the blank substrate, ultimately forming the transfer substrate 500, para. [0056-0068]). [AltContent: textbox (laser)][AltContent: arrow][AltContent: textbox (second electronic units)][AltContent: ] PNG media_image2.png 329 541 media_image2.png Greyscale Annotated Fig. 4, Lin. Therefore, in view of the teachings of Lin, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the manufacturing method of an electronic device of Xu and to replace the disposing or transferring the repairing electronic unit of Xu with a laser transfer method as Lin disclosed in Fig. 4 so that it enables to repairing a display device comprising large scale repair electronic units as Lin disclosed in para. [0082]. Moreover, there is no indication in the instant invention that any surprising results were derived, or that any special steps were devised in laser transfer. Such a combination would have been done by one of ordinary skill in the art without any need for experimentation and with reasonable expectations of success. Regarding claim 2, Xu in view of Lin teaches the recited limitations with respect to claim 1. Lin further teaches, the manufacturing method of claim 1, wherein the step of disposing the at least one repairing electronic unit in the at least one of the plurality of second recesses of the defective working area through laser transfer includes: [AltContent: textbox (first carrier)][AltContent: ][AltContent: textbox (second carrier)][AltContent: ] PNG media_image3.png 223 482 media_image3.png Greyscale Annotated Fig. 7a, Lin. providing a first carrier (red repairing substrate 400r, green repairing substrate 400g, blue repairing substrate 400b, see annotated Fig. 7a and Figs. 7b, 7c and Fig. 8), wherein the first carrier includes a plurality of second electronic units (see annotated Fig. 7a); irradiating at least one of the plurality of second electronic units with a laser light, such that the at least one of the plurality of second electronic units is transferred from the first carrier to a second carrier (transfer substrate 500, see Figs. Fig. 7a to Fig. 8 ); and transferring the at least one of the plurality of second electronic units from the second carrier to the at least one of the plurality of second recesses of the defective working area, so as to enable the at least one of the plurality of second electronic units to serve as the at least one repairing electronic unit (see Figs. 7a to 7c and Fig. 8, para. [089-0092]). Therefore, in view of the teachings of Lin, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the manufacturing method of an electronic device of Xu and to replace the disposing or transferring the repairing electronic unit of Xu with a laser transfer method as Lin disclosed in Fig. 2 so that it enables to simultaneously repairing a display device having multiple defective units. Regarding claim 3, Xu in view of Lin teaches the recited limitations with respect to claim 2. Lin further teaches, the manufacturing method of claim 2, wherein the first carrier includes a base (repairing substrate 400r, 400g, 400b, Figs. 7a to 7c) and a material layer (photolysis material 501, Figs. 7a to 7c) disposed on the base, and the plurality of second electronic units are adhered to the base through the material layer (repairing substrate 400 and each chip 20 are bonded by photolysis material 401, para. [0068]). Regarding claim 4, Xu in view of Lin teaches the recited limitations with respect to claim 1. Lin further teaches, the manufacturing method of claim 1, wherein the step of disposing the at least one repairing electronic unit in the at least one of the plurality of second recesses of the defective working area through laser transfer includes: providing a carrier (red repairing substrate 400r, green repairing substrate 400g, blue repairing substrate 400b, see annotated Fig. 7a and Figs. 7b, 7c and Fig. 8), wherein the carrier includes a plurality of second electronic units (see Fig. 8); and irradiating at least one of the plurality of second electronic units with a laser light, such that the at least one of the plurality of second electronic units is transferred from the carrier to the at least one of the plurality of second recesses of the defective working area to enable the at least one of the plurality of second electronic units to serve as the at least one repairing electronic unit (para. [0089-0092]). Therefore, in view of the teachings of Lin, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the manufacturing method of an electronic device of Xu and to replace the disposing or transferring the repairing electronic unit of Xu with a laser transfer method as Lin disclosed in Fig. 2 so that it enables to simultaneously repairing a display device having multiple defective units. Regarding claim 5, Xu in view of Lin teaches the recited limitations with respect to claim 1. Xu further teaches, the manufacturing method of claim l, wherein the at least one of the plurality of second recesses of the defective working area is adjacent to the at least one of the plurality of first recesses of the defective working area (see Figs. 1, 2 and 11). Regarding claim 6, Xu in view of Lin teaches the recited limitations with respect to claim 1. Xu further teaches, the manufacturing method of claim 1, wherein the substrate includes: a base (see annotated Fig. 2 below); a circuit layer disposed on the base (a bottom of each of the main recesses and a bottom of each of the backup recesses are provided with two electrodes, respectively, the two electrodes in the main recess are electrically connected to a first welding circuit, and the two electrodes in the backup recess are electrically connected to a second welding circuit, para. [0015]); and a bank structure (see annotated Fig. 2) disposed on the circuit layer, wherein the plurality of first recesses and the plurality of second recesses are defined through the bank structure (see Figs. 2 and 11). [AltContent: arrow][AltContent: textbox (base)][AltContent: textbox (bank structure)][AltContent: arrow] PNG media_image4.png 276 418 media_image4.png Greyscale Annotated Fig. 2, Xu. Regarding claim 7, Xu in view of Lin teaches the recited limitations with respect to claim 6. Xu further teaches, the manufacturing method of claim 6, wherein the circuit layer includes a plurality of bonding pads being exposed by the plurality of first recesses (a bottom of each of the main recesses and a bottom of each of the backup recesses are provided with two electrodes, para. [0015]). Regarding claim 8, Xu in view of Lin teaches the recited limitations with respect to claim 1. Xu further teaches, the manufacturing method of claim 1, wherein a number of the plurality of first recesses included in each of the plurality of working areas is three, and a number of the plurality of second recesses included in each of the plurality of working areas is three (plurality of the sub-pixel areas are divided into three areas, para. [0124]). Regarding claim 9, Xu in view of Lin teaches the recited limitations with respect to claim 1. Xu further teaches, the manufacturing method of claim 1, wherein a shape of the plurality of first recesses is different from a shape of the plurality of second recesses (see the main recess 110 and backup recess 120 in first area 100, second area 200 and third area 300 in Fig. 4). [AltContent: textbox (first recess)][AltContent: arrow][AltContent: textbox (second recess)][AltContent: ] PNG media_image5.png 307 456 media_image5.png Greyscale Annotated Fig. 4, Xu Regarding claim 10, Xu in view of Lin teaches the recited limitations with respect to claim 1. Xu further teaches, the manufacturing method of claim 1, wherein a size of one of the plurality of first recesses is greater than a size of one of the plurality of second recesses (see annotated Fig. 4). Conclusion Prior art Lin (US 20210057607 ) teaches, a manufacturing method of an electronic device, including providing a substrate having a plurality of working areas, and each of the plurality of working areas includes a plurality of first recesses and a plurality of second recesses; disposing a plurality of first electronic units in the plurality of first recesses of the plurality of working areas through fluid transfer; identifying a defective working area; and disposing at least one repairing electronic unit. Prior art Park (US 20200357951) teaches, a manufacturing method of an electronic device, including providing a substrate having a plurality of working areas, and each of the plurality of working areas includes a plurality of first recesses and a plurality of second recesses; disposing a plurality of first electronic units in the plurality of first recesses of the plurality of working areas; identifying a defective working area; and disposing at least one repairing electronic unit through laser transfer. Prior art Liu (Liu et.al., Micro-light-emitting diodes with quantum dots in display technology, Light: Science & Applications, 9, 83, 2020, page 1-23) teaches, a manufacturing method of an electronic device, including providing a substrate having a plurality of working areas; disposing a plurality of first electronic units through fluid transfer; identifying a defective working area; and disposing at least one repairing electronic unit through laser transfer. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE K. ABRAHAM whose telephone number is (571)270-1087. The examiner can normally be reached Monday-Friday 8:30-4:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, THOMAS J. HONG can be reached at (571) 272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOSE K ABRAHAM/Examiner, Art Unit 3729
Read full office action

Prosecution Timeline

Oct 03, 2023
Application Filed
Sep 03, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
99%
With Interview (+32.9%)
2y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 375 resolved cases by this examiner. Grant probability derived from career allowance rate.

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