Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The amendment filed 09/05/2025 has been entered. Claims 1, 5, 7-11, 15-16 and 18-19 are pending. Claims 1 and 11 have been amended. Claims 2, 6, 12 and 17 are canceled. No new claim is added.
Response to Arguments
Applicant's arguments filed 09/05/2025 have been fully considered but they are not persuasive.
In that remark, the applicant argued in substance:
That: Regarding claim 1, the cited references fail to disclose “wherein the broadcasting circuit comprises: a broadcasting memory configured to store the target data; and a state controller configured to control a state of the broadcasting circuit; wherein the first computing core checks the state before storing the target data into the broadcasting memory, and the second computing core checks the state before reading the target data from the broadcasting memory”.
In response to the applicant’s argument Park teaches wherein the broadcasting circuit comprises: a broadcasting memory configured to store the target data (i.e. the internal memory 200 may include a weight storage unit 210 and a feature map storage unit 220. The weight storage unit 210 may store at least a portion of the weights of the ANN model, [0176]); and a state controller configured to control a state of the broadcasting circuit (i.e. the controller 300 may be configured to control the PE array 100 and the internal memory 200 in consideration of the size of the weight values of the ANN model, the size of the feature map, and the calculation sequence of the weight values and the feature map, [0179]); wherein the first computing core checks the state before storing the target data into the broadcasting memory (i.e. when the size of the internal memory 200 is determined and when the size of the input feature map and the output feature map of a specific layer or a tile of a specific layer are smaller than the internal memory 200 capacity, [0149]).
Therefore, Park clearly teaches internal memory that includes plurality of storages units to store data (which corresponds to broadcasting memory to store target data), a controller controls a PE array and the internal memory (which corresponds to a state controller) and determining the size of the internal memory to check the memory capacity (which corresponds to checking the state before storing the target data).
That: the cited references fail to disclose “wherein the second computing core further comprises: a pipeline controller coupled to the broadcasting circuit and the external memory; and a broadcast control circuit configured to control, according to a convolution instruction received by the second computing core, the pipeline controller to obtain data from the external memory or read data from the broadcasting memory”.
In response to the applicant’s argument Yoda teaches a pipeline controller coupled to the broadcasting circuit and the external memory (i.e. a control core C_CORE for controlling the processor cores CORE0 to CORE3, and in addition, similarly to the configuration illustrated in FIG. 3, a direct memory access control circuit DMA, a memory controller MC, an internal high-speed memory (SRAM) I_MEM, and an internal bus I_BUS, [0057]); and a broadcast control circuit configured to control, according to a convolution instruction received by the second computing core, the pipeline controller to obtain data from the external memory or read data from the broadcasting memory (i.e. The control core C_CORE sets in a configuration register CFG of the transfer control circuit TRN_CN a specific address from which read data is read and another specific address of a shared memory to which the read data is transferred. The control core C_CORE sets in the selectors SL0 and SL1 the transfer selection information in accordance with transfer destinations, [0085] and the control core C_CORE sets the read selection information in the multiple selectors (SL0 and SL1), the read data in the multiple shared memories (SMEM0 and SMEM1) are read via the selectors (SL0 and SL1), in which the read selection information is set, by either the processor core (CORE0) to which the shared memory belongs or the first adjacent processor core (CORE3), [0100]).
Yoda clearly teaches on Fig. 3, a control core C_CORE connected and controls the processor cores and memories (a pipeline controller coupled to the broadcasting circuit and the external memory), the control core sets a specific address from which read data is read and another specific address of a shared memory to which the read data is transferred (which corresponds to obtain data from the external memory or read data from the broadcasting memory).
Therefore, the combination of PARK in view of Yoda makes the claimed limitations obvious.
That: the cited references fail to disclose “wherein the first computing core comprises a data reordering circuit, the first computing core further comprises a multiply accumulate performing a multiply-accumulate operation based on an output of the data reordering circuit, and the first computing core further provides the target data to the data reordering circuit after reading the target data; wherein the data reordering circuit reorders the target data to make the target data conform to the multiply accumulate; wherein the first computing core further comprises: a first buffer circuit for storing the target data; and a second buffer circuit for storing the output of the data reordering circuit; wherein the data reordering circuit is coupled between the first buffer circuit and the second buffer circuit”
In response to the applicant’s argument Kreeger teaches wherein the first computing core comprises a data reordering circuit (i.e. reorder module, [0089]), the first computing core further comprises a multiply accumulate performing a multiply-accumulate operation based on an output of the data reordering circuit (i.e. Given a SegNet Reorder/Convolution of width 7, height 7 and channels 64 an approach with compression will send 3136 (7×7×64) values from the reorder module, 801, to each convolver, 802 where 3136 MuItiply Accumulations will be performed. With a 50% chance of zero values the described circuitry will send 98 BitMasks and only 1568 data values, [0090] and The highest bandwidth and computation load in terms of multiply accumulates occurs in the DataStreams exiting the “Reorder” module, [0089]), and the first computing core further provides the target data to the data reordering circuit after reading the target data (i.e. data streams from the main memory and other secondary cores to stream into the corresponding core that contains the reorder module, [0061]); wherein the data reordering circuit reorders the target data to make the target data conform to the multiply accumulate (i.e. The reorder stages convert the row-based video stream into a window-based stream, [0084] and automatically compressing the data leaving the reorder module, 801, reduces the bandwidth required to feed the convolve modules as well as reducing the maximum MAC (multiply accumulates) that each convolve performs. The circuitry which resides in the reorder module which performs the compression, [0089]).
Kreeger clearly teaches reorder module (corresponds to data reordering circuit), based on values from the reorder module MuItiply Accumulations is performed (corresponds to performing a multiply-accumulate operation based on an output of the data reordering circuit), data sent from memory or secondary core to the reorder module (corresponds to provides the target data to the data reordering circuit) and the reorder module converts data to match the MAC (multiply accumulates) that each convolve performs (corresponds to reorders the target data to make the target data conform to the multiply accumulate).
Cheung teaches wherein the first computing core further comprises: a first buffer circuit for storing the target data (i.e. serial data stream DATA may be stored in a first direction on first buffer circuit 402, Col. 8, lines 4-10); and a second buffer circuit for storing the output of the data reordering circuit (i.e. data elements of left buffer 402 may be fed to re-ordering buffer 406 for reordering, col. col. 13, lines 39-40, data elements may be read out from re-ordering buffer 406 such that the data elements are provided to second buffer 404, col. 13, lines 41-43, and data elements are loaded onto second buffer 404, col. 13, lines 50-51); wherein the data reordering circuit is coupled between the first buffer circuit and the second buffer circuit (i.e. re-ordering buffer circuit 406 interposed between the first and second data buffer circuits, Col. 7, lines 28-29).
Cheung clearly teaches a re-ordering buffer circuit located between the first and second data buffer circuits, a data stream in the first buffer and sent to the reordering buffer, the output from the reordering buffer to provide to the second buffer.
Therefore, the combination of the cited refences makes the claimed limitations obvious.
That: Regarding claim 11, the cited references fail to disclose “wherein the broadcasting circuit comprises: a broadcasting memory configured to store the target data; and a state controller configured to control a state of the broadcasting circuit; wherein the convolution core checks the state before storing the target data in the broadcasting memory.”
In response to the applicant’s argument Park teaches wherein the broadcasting circuit comprises: a broadcasting memory configured to store the target data (i.e. The internal memory 200 may include a weight storage unit 210 and a feature map storage unit 220. The weight storage unit 210 may store at least a portion of the weights of the ANN model, [0176]); and a state controller configured to control a state of the broadcasting circuit (i.e. the controller 300 may be configured to control the PE array 100 and the internal memory 200 in consideration of the size of the weight values of the ANN model, the size of the feature map, and the calculation sequence of the weight values and the feature map, [0179]); wherein the convolution core checks the state before storing the target data into the broadcasting memory (i.e. when the size of the internal memory 200 is determined and when the size of the input feature map and the output feature map of a specific layer or a tile of a specific layer are smaller than the internal memory 200 capacity, [0149]); the state controller changes the state in response to a read operation the convolution core reads the target data from the memory (i.e. the controller 300 may be configured to control the PE array 100 and the internal memory 200 in consideration of the size of the weight values of the ANN model, the size of the feature map, and the calculation sequence of the weight values and the feature map, [0179] and the controller 300 of the NPU 1000 may inactivate the F_out signal line outputting the MAC operation value of the exemplary PE_10 performing step (2). That is, various stride values can be easily adjusted by not taking the MAC operation value of a specific processing element. According to the above configuration, there is an effect that the stride value can be easily applied by selectively controlling only the output of the F_out signal line of Pes, [0374]).
Therefore, Park clearly teaches internal memory that includes plurality of storages units to store data (which corresponds to broadcasting memory to store target data), a controller controls a PE array and the internal memory (which corresponds to a state controller) and determining the size of the internal memory to check the memory capacity (which corresponds to checking the state before storing the target data).
That: the cited references fail to disclose “a convolution core comprising a broadcasting circuit and a multiply accumulate, wherein the convolution core reads the target data from the memory, stores the target data in the broadcasting circuit, and provides the target data to the multiply accumulate; wherein the convolution core comprises a data reordering circuit configured to reorder the target data, and the multiply accumulate performs a multiply-accumulate operation according to an output of the data reordering circuit; wherein the data reordering circuit reorders the target data to make the target data conform to the multiply accumulate; wherein the convolution core further comprises: a first buffer circuit configured to store the target data; and a second buffer circuit configured to store the output of the data reordering circuit; wherein the data reordering circuit is coupled between the first buffer circuit and the second buffer circuit.”
In response to the applicant’s argument Park teaches a convolution core comprising a broadcasting circuit and a multiply accumulate (i.e. The PE array 100 may be configured to include a plurality of processing elements (PE1, PE2, ) 110 configured to calculate node data of an ANN and weight data of a connection network. Each processing element may include a multiply and accumulate (MAC) operator and/or an arithmetic logic unit (ALU) operator, [0132]), and provides the target data to the multiply accumulate (i.e. each PE receives the weight data and the feature map data and performs MAC operations on the weight data and the feature map data, [0297]).
Therefore, park also clearly teaches The PE array 100 may be configured to include a plurality of processing elements include a multiply and accumulate (MAC) operator and/or an arithmetic logic unit (ALU) operator (corresponds to convolution core comprising a broadcasting circuit and a multiply accumulate) and each PE receives the weight data and the feature map data and performs MAC operations (corresponds to provides the target data to the multiply accumulate).
Yoda teaches wherein the convolution core reads the target data from the memory (i.e. the processor cores CORE0 to CORE3 read the respective images X0 to X3 and the respective coefficient filters F00 to F03, F10 to F13, F20 to F23, and F30 to F33 from the respective individual memories IMEM0 to IMEM3, which belong respectively to the processor cores CORE0 to CORE3, [0067]), stores the target data in the broadcasting circuit (i.e. the image X3 is stored in the shared memory SMEM0, the image X0 is stored in the shared memory SMEM1, the image X1 is stored in the shared memory SMEM2, and the image X2 is stored in the shared memory SMEM3, [0067]).
Therefore, Yoda clearly teaches the processor cores CORE0 to CORE3 read the respective images from memory and store it.
Kreeger teaches wherein the convolution core comprises a data reordering circuit configured to reorder the target data (i.e. reorder module, [0089]), and the multiply accumulate performs a multiply-accumulate operation according to an output of the data reordering circuit (i.e. Given a SegNet Reorder/Convolution of width 7, height 7 and channels 64 an approach with compression will send 3136 (7×7×64) values from the reorder module, 801, to each convolver, 802 where 3136 MuItiply Accumulations will be performed. With a 50% chance of zero values the described circuitry will send 98 BitMasks and only 1568 data values, [0090] and The highest bandwidth and computation load in terms of multiply accumulates occurs in the DataStreams exiting the “Reorder” module, [0089]); wherein the data reordering circuit reorders the target data to make the target data conform to the multiply accumulate (i.e. The reorder stages convert the row-based video stream into a window-based stream, [0084] and automatically compressing the data leaving the reorder module, 801, reduces the bandwidth required to feed the convolve modules as well as reducing the maximum MAC (multiply accumulates) that each convolve performs. The circuitry which resides in the reorder module which performs the compression, [0089]).
Therefore, Kreeger clearly teaches reorder module (corresponds to data reordering circuit), based on values from the reorder module MuItiply Accumulations is performed (corresponds to performing a multiply-accumulate operation based on an output of the data reordering circuit), data sent from memory or secondary core to the reorder module (corresponds to provides the target data to the data reordering circuit) and the reorder module converts data to match the MAC (multiply accumulates) that each convolve performs (corresponds to reorders the target data to make the target data conform to the multiply accumulate).
Cheung teaches wherein the first computing core further comprises: a first buffer circuit for storing the target data (i.e. serial data stream DATA may be stored in a first direction on first buffer circuit 402, Col. 8, lines 4-10); and a second buffer circuit for storing the output of the data reordering circuit (i.e. data elements of left buffer 402 may be fed to re-ordering buffer 406 for reordering, col. col. 13, lines 39-40, data elements may be read out from re-ordering buffer 406 such that the data elements are provided to second buffer 404, col. 13, lines 41-43, and data elements are loaded onto second buffer 404, col. 13, lines 50-51); wherein the data reordering circuit is coupled between the first buffer circuit and the second buffer circuit (i.e. re-ordering buffer circuit 406 interposed between the first and second data buffer circuits, Col. 7, lines 28-29).
Therefore, Cheung clearly teaches a re-ordering buffer circuit located between the first and second data buffer circuits, a data stream in the first buffer and sent to the reordering buffer, the output from the reordering buffer to provide to the second buffer.
Therefore, the combination of the cited refences makes the claimed limitations obvious.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8-11, and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over PARK et al. (US 20220335282) hereinafter PARK in view of Yoda et al. (US 20190196887) hereinafter Yoda and Kreeger et al. (US 20200213079) hereinafter Kreeger and further in view of Cheung (US 9837988 B1) hereinafter Cheung.
Regarding claim 1, PARK teaches a computing device coupled to an external memory (i.e. Fig. 1 and The device B including the NPU 1000 may include at least one of the internal memory 200, the on-chip memory 3000, and the main memory 4000 of the aforementioned NPU 1000, [0098]), comprising: a first computing core (neural processing unit) comprising a broadcasting circuit (i.e. a neural processing unit (NPU) 1000 includes a processing element array (PE array) 100, an internal memory 200, and a controller 300, [0131]), wherein the first computing core is configured to obtain a target data from the external memory (i.e. the neural processing unit (NPU) frequently reads the feature map or weight kernel of a specific layer of the ANN model from the main memory, [0018], store the target data in the broadcasting circuit (i.e. the scheduler 320 loads weight data corresponding to the first input data into the weight storage unit 210 of the internal memory 200, [0186]), and use the target data to perform a first convolution operation (i.e. the controller 300 may control the PE array 100 to perform a first convolution operation such as a point-wise convolution operation in the first mode, [0193]; wherein the broadcasting circuit comprises: a broadcasting memory configured to store the target data (i.e. The internal memory 200 may include a weight storage unit 210 and a feature map storage unit 220. The weight storage unit 210 may store at least a portion of the weights of the ANN model, [0176]); and a state controller configured to control a state of the broadcasting circuit (i.e. the controller 300 may be configured to control the PE array 100 and the internal memory 200 in consideration of the size of the weight values of the ANN model, the size of the feature map, and the calculation sequence of the weight values and the feature map, [0179]); wherein the first computing core checks the state before storing the target data into the broadcasting memory (i.e. when the size of the internal memory 200 is determined and when the size of the input feature map and the output feature map of a specific layer or a tile of a specific layer are smaller than the internal memory 200 capacity, [0149]).
However, Park does not explicitly disclose a second computing core configured to read the target data from the broadcasting circuit and use the target data to perform a second convolution operation; the second computing core checks the state before reading the target data from the broadcasting memory; a pipeline controller coupled to the broadcasting circuit and the external memory; and a broadcast control circuit configured to control, according to a convolution instruction received by the second computing core, the pipeline controller to obtain data from the external memory or read data from the broadcasting memory.
However, Yoda teaches a second computing core configured to read the target data from the broadcasting circuit (i.e. the processor cores CORE0 to CORE3 read the respective images X0 to X3 and the respective coefficient filters F00 to F03, F10 to F13, F20 to F23, and F30 to F33 from the respective individual memories IMEM0 to IMEM3, which belong respectively to the processor cores CORE0 to CORE3, [0067]) and use the target data to perform a second convolution operation (i.e. perform respective convolution operations ΣW0*X0, ΣW1*X1, ΣW2*X2, and ΣW3*X3, [0067]); the second computing core checks the state before reading the target data from the broadcasting memory (i.e. detect that the transfer range in the configuration register CFG is identical to the read address and that the transfer flag denotes that transfer is desired, calculate the transfer destination address TADD, and control each of the images X0 to X3 as read data to be output together with the write signal WT to the shared memory (the memory bank B#b) that belongs to the second adjacent processor core and that is at the transfer destination address TADD, [0108]); a pipeline controller coupled to the broadcasting circuit and the external memory (i.e. a control core C_CORE for controlling the processor cores CORE0 to CORE3, and in addition, similarly to the configuration illustrated in FIG. 3, a direct memory access control circuit DMA, a memory controller MC, an internal high-speed memory (SRAM) I_MEM, and an internal bus I_BUS, [0057]); and a broadcast control circuit configured to control, according to a convolution instruction received by the second computing core, the pipeline controller to obtain data from the external memory or read data from the broadcasting memory (i.e. The control core C_CORE sets in a configuration register CFG of the transfer control circuit TRN_CN a specific address from which read data is read and another specific address of a shared memory to which the read data is transferred. The control core C_CORE sets in the selectors SL0 and SL1 the transfer selection information in accordance with transfer destinations, [0085] and the control core C_CORE sets the read selection information in the multiple selectors (SL0 and SL1), the read data in the multiple shared memories (SMEM0 and SMEM1) are read via the selectors (SL0 and SL1), in which the read selection information is set, by either the processor core (CORE0) to which the shared memory belongs or the first adjacent processor core (CORE3), [0100]).
Based on PARK in view of Yoda, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teaching of Yoda to the system of PARK in order to increase data convolution capability of PARK system.
However, PARK in view of Yoda do not explicitly disclose wherein the first computing core comprises a data reordering circuit, the first computing core further comprises a multiply accumulate performing a multiply-accumulate operation based on an output of the data reordering circuit, and the first computing core further provides the target data to the data reordering circuit after reading the target data; wherein the data reordering circuit reorders the target data to make the target data conform to the multiply accumulate.
However, Kreeger teaches wherein the first computing core comprises a data reordering circuit (i.e. reorder module, [0089]), the first computing core further comprises a multiply accumulate performing a multiply-accumulate operation based on an output of the data reordering circuit (i.e. Given a SegNet Reorder/Convolution of width 7, height 7 and channels 64 an approach with compression will send 3136 (7×7×64) values from the reorder module, 801, to each convolver, 802 where 3136 MuItiply Accumulations will be performed. With a 50% chance of zero values the described circuitry will send 98 BitMasks and only 1568 data values, [0090] and The highest bandwidth and computation load in terms of multiply accumulates occurs in the DataStreams exiting the “Reorder” module, [0089]), and the first computing core further provides the target data to the data reordering circuit after reading the target data (i.e. data streams from the main memory and other secondary cores to stream into the corresponding core that contains the reorder module, [0061]); wherein the data reordering circuit reorders the target data to make the target data conform to the multiply accumulate (i.e. The reorder stages convert the row-based video stream into a window-based stream, [0084] and automatically compressing the data leaving the reorder module, 801, reduces the bandwidth required to feed the convolve modules as well as reducing the maximum MAC (multiply accumulates) that each convolve performs. The circuitry which resides in the reorder module which performs the compression, [0089]).
Based on PARK in view of Yoda and further in view of Kreeger, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teaching of Kreeger to the system of PARK and Yoda in order to reduce consumption of computing resources, (Kreeger, [0010]).
However, PARK in view of Yoda and further in view of Kreeger do not explicitly disclose wherein the first computing core further comprises: a first buffer circuit for storing the target data; and a second buffer circuit for storing the output of the data reordering circuit; wherein the data reordering circuit is coupled between the first buffer circuit and the second buffer circuit.
However, Cheung teaches wherein the first computing core further comprises: a first buffer circuit for storing the target data (i.e. serial data stream DATA may be stored in a first direction on first buffer circuit 402, Col. 8, lines 4-10); and a second buffer circuit for storing the output of the data reordering circuit (i.e. data elements of left buffer 402 may be fed to re-ordering buffer 406 for reordering, col. col. 13, lines 39-40, data elements may be read out from re-ordering buffer 406 such that the data elements are provided to second buffer 404, col. 13, lines 41-43, and data elements are loaded onto second buffer 404, col. 13, lines 50-51); wherein the data reordering circuit is coupled between the first buffer circuit and the second buffer circuit (i.e. re-ordering buffer circuit 406 interposed between the first and second data buffer circuits, Col. 7, lines 28-29).
Based on PARK in view of Yoda and Kreeger and further in view of Cheung, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teaching of Cheung to the system of PARK, Yoda, and Kreeger in order to reduce consuming excessive system resources, (Cheung, Col. 1, lines 34).
Regarding claim 8, PARK teaches the broadcasting circuit is a first broadcasting circuit, the target data is a first target data (i.e. weight data corresponding to the first input data into the weight storage unit 210 of the internal memory 200, [0186]), the second computing core comprises a second broadcasting circuit, and the second computing core further uses a second target data to perform the second convolution operation (i.e. The NPU may further include a delay buffer disposed in at least some of the PE rows of the PE array, the delay buffer configured in the second mode to receive an input of the weight data that is used for the second convolution operation, [0043]), the second computing core obtains the second target data from the external memory (i.e. When the mode selector 310 selects the second mode, the scheduler 320 may load the weight data into the weight storage unit 210 and load the feature map data into the feature map storage unit 220, [0187]) and stores the second target data in the second broadcasting circuit (i.e. transmit the weight data to a second processing element; and a broadcast signal line configured to provide feature map data simultaneously to the second processing element, [0046] and the feature map data corresponding to the second input data may be loaded into the feature map storage unit 220 of the internal memory 200, [0186]), the first computing core obtains the second target data from the second broadcasting circuit (i.e. Each of the PEs of the PE array 100 may be configured to receive a weight through W_in signal lines connected to the weight storage unit 210, and may be connected to F_in signal lines connected to the feature map storage unit 220, [0232]), and the first computing core further uses the second target data to perform the first convolution operation (i.e. When a selection signal for operating in the second mode is received from the mode selector 310, the PE array 100 transmits an enable signal to each PE of the first group 150 to activate the PEs of the first group 150 operating in the second mode. Accordingly, the PEs of the first group 150 may be activated to perform the operation of the second mode, [0310]), the first target data being different from the second target data (i.e. the data size of the weight are different for each layer, [0189]).
Regarding claim 9, PARK teaches the target data is an input feature data of at least one of the first convolution operation and the second convolution operation (i.e. an input of the weight data that is used for the first convolution operation, [0042] and an input of the weight data that is used for the second convolution operation, [0043]).
Regarding claim 10, PARK teaches the target data is a weight data of at least one of the first convolution operation and the second convolution operation an input of the weight data that is used for the first convolution operation, [0042] and an input of the weight data that is used for the second convolution operation, [0043]).
Regarding claim 11, PARK teaches a computing core coupled to an external memory (i.e. the NPU 1000 may include at least one of the internal memory 200, the on-chip memory 3000, and the main memory 4000 of the aforementioned NPU 1000, [0098], wherein the external memory stores a target data (i.e. weight and feature map of the ANN are stored in the main memory 4000, [0190]), the computing core comprising: a memory configured to store the target data (i.e. weight and feature map of the ANN are stored in the on-chip memory 3000, [0190]); and a convolution core comprising a broadcasting circuit and a multiply accumulate (i.e. The PE array 100 may be configured to include a plurality of processing elements (PE1, PE2, ) 110 configured to calculate node data of an ANN and weight data of a connection network. Each processing element may include a multiply and accumulate (MAC) operator and/or an arithmetic logic unit (ALU) operator, [0132]), and provides the target data to the multiply accumulate (i.e. each PE receives the weight data and the feature map data and performs MAC operations on the weight data and the feature map data, [0297]); wherein the broadcasting circuit comprises: a broadcasting memory configured to store the target data (i.e. The internal memory 200 may include a weight storage unit 210 and a feature map storage unit 220. The weight storage unit 210 may store at least a portion of the weights of the ANN model, [0176]); and a state controller configured to control a state of the broadcasting circuit (i.e. the controller 300 may be configured to control the PE array 100 and the internal memory 200 in consideration of the size of the weight values of the ANN model, the size of the feature map, and the calculation sequence of the weight values and the feature map, [0179]); wherein the convolution core checks the state before storing the target data into the broadcasting memory (i.e. when the size of the internal memory 200 is determined and when the size of the input feature map and the output feature map of a specific layer or a tile of a specific layer are smaller than the internal memory 200 capacity, [0149]); the state controller changes the state in response to a read operation the convolution core reads the target data from the memory (i.e. the controller 300 may be configured to control the PE array 100 and the internal memory 200 in consideration of the size of the weight values of the ANN model, the size of the feature map, and the calculation sequence of the weight values and the feature map, [0179] and the controller 300 of the NPU 1000 may inactivate the F_out signal line outputting the MAC operation value of the exemplary PE_10 performing step (2). That is, various stride values can be easily adjusted by not taking the MAC operation value of a specific processing element. According to the above configuration, there is an effect that the stride value can be easily applied by selectively controlling only the output of the F_out signal line of Pes, [0374]).
However, Park does not explicitly disclose wherein the convolution core reads the target data from the memory, stores the target data in the broadcasting circuit; wherein the broadcasting circuit comprises: a broadcasting memory configured to store the target data.
However, Yoda teaches wherein the convolution core reads the target data from the memory (i.e. the processor cores CORE0 to CORE3 read the respective images X0 to X3 and the respective coefficient filters F00 to F03, F10 to F13, F20 to F23, and F30 to F33 from the respective individual memories IMEM0 to IMEM3, which belong respectively to the processor cores CORE0 to CORE3, [0067]), stores the target data in the broadcasting circuit (i.e. the image X3 is stored in the shared memory SMEM0, the image X0 is stored in the shared memory SMEM1, the image X1 is stored in the shared memory SMEM2, and the image X2 is stored in the shared memory SMEM3, [0067]).
Based on PARK in view of Yoda, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teaching of Yoda to the system of PARK in order to increase data convolution capability of PARK system.
However, PARK in view of Yoda do not explicitly disclose wherein the convolution core comprises a data reordering circuit configured to reorder the target data, and the multiply accumulate performs a multiply-accumulate operation according to an output of the data reordering circuit; wherein the data reordering circuit reorders the target data to make the target data conform to the multiply accumulate.
However, Kreeger teaches wherein the convolution core comprises a data reordering circuit configured to reorder the target data (i.e. reorder module, [0089]), and the multiply accumulate performs a multiply-accumulate operation according to an output of the data reordering circuit (i.e. Given a SegNet Reorder/Convolution of width 7, height 7 and channels 64 an approach with compression will send 3136 (7×7×64) values from the reorder module, 801, to each convolver, 802 where 3136 MuItiply Accumulations will be performed. With a 50% chance of zero values the described circuitry will send 98 BitMasks and only 1568 data values, [0090] and The highest bandwidth and computation load in terms of multiply accumulates occurs in the DataStreams exiting the “Reorder” module, [0089]); wherein the data reordering circuit reorders the target data to make the target data conform to the multiply accumulate (i.e. The reorder stages convert the row-based video stream into a window-based stream, [0084] and automatically compressing the data leaving the reorder module, 801, reduces the bandwidth required to feed the convolve modules as well as reducing the maximum MAC (multiply accumulates) that each convolve performs. The circuitry which resides in the reorder module which performs the compression, [0089]).
Based on PARK in view of Yoda and further in view of Kreeger, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teaching of Kreeger to the system of PARK and Yoda in order to reduce consumption of computing resources, (Kreeger, [0010]).
However, PARK in view of Yoda and further in view of Kreeger do not explicitly disclose wherein the first computing core further comprises: a first buffer circuit for storing the target data; and a second buffer circuit for storing the output of the data reordering circuit; wherein the data reordering circuit is coupled between the first buffer circuit and the second buffer circuit.
However, Cheung teaches wherein the first computing core further comprises: a first buffer circuit for storing the target data (i.e. serial data stream DATA may be stored in a first direction on first buffer circuit 402, Col. 8, lines 4-10); and a second buffer circuit for storing the output of the data reordering circuit (i.e. data elements of left buffer 402 may be fed to re-ordering buffer 406 for reordering, col. col. 13, lines 39-40, data elements may be read out from re-ordering buffer 406 such that the data elements are provided to second buffer 404, col. 13, lines 41-43, and data elements are loaded onto second buffer 404, col. 13, lines 50-51); wherein the data reordering circuit is coupled between the first buffer circuit and the second buffer circuit (i.e. re-ordering buffer circuit 406 interposed between the first and second data buffer circuits, Col. 7, lines 28-29).
Based on PARK in view of Yoda and Kreeger and further in view of Cheung, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teaching of Cheung to the system of PARK, Yoda, and Kreeger in order to reduce consuming excessive system resources, (Cheung, Col. 1, lines 34).
Regarding claims 18-19, the limitations of claims 18-19 are similar to the limitations of claims 9-10. Therefore, the limitations of claims 18-19 are rejected in the analysis of claims 9-10 above, and the claims are rejected on that basis.
Claim(s) 5, 7 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over PARK et al. (US 20220335282) hereinafter PARK in view of Yoda et al. (US 20190196887) hereinafter Yoda and Kreeger et al. (US 20200213079) hereinafter Kreeger and Cheung (US 9837988 B1) hereinafter Cheung and further in view of KREININ et al. (WO 2016199154) hereinafter KREININ.
Regarding claim 5, PARK in view of Yoda and Kreeger and further in view of Cheung teaches the limitations of claim 1 above.
However, Park in view of Yoda and Kreeger and further in view of Cheung do not explicitly disclose the first computing core further comprises a weight loading circuit, and the weight loading circuit stores two consecutive read requests.
However, KREININ teaches the first computing core further comprises a weight loading circuit, and the weight loading circuit stores two consecutive read requests (i.e. a buffer may be used to store consecutive gather read commands, [00399]).
Based on PARK in view of Yoda and Kreeger and Cheung and further in view of KREININ, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teaching of KREININ to the system of PARK, Yoda, Kreeger, and Cheung in order to have increased computation speed and more efficient use of memory and power, ([004]).
Regarding claim 7, PARK in view of Yoda and Kreeger and further in view of Cheung teach the limitations of claims 1 and 2 above.
However, Park in view of Yoda and Kreeger and further in view of Cheung do not explicitly disclose the broadcasting memory is a first-in first-out memory.
However, KREININ teaches the broadcasting memory is a first-in first-out memory (i.e. the cores 604a-d and the serial processor 616 may both share a local memory (6004 in FIG. 6B). In another example, the cores 604a-d can write data into a first in first out (FIFO) queue, [00141]).
Based on PARK in view of Yoda and Kreeger and Cheung and further in view of KREININ, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teaching of KREININ to the system of PARK, Yoda, Kreeger, and Cheung in order to have increased computation speed and more efficient use of memory and power, ([004]).
Regarding claims 15-16, the limitations of claims 15-16 are similar to the limitations of claims 5 and 7. Therefore, the limitations of claims 15-16 are rejected in the analysis of claims 5 and 7 above, and the claims are rejected on that basis.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A W/
AYELE F. WOLDEMARIAM
Examiner
Art Unit 2447
9/17/2025
/SURAJ M JOSHI/Primary Examiner, Art Unit 2447