DETAILED ACTION
This office action is in response to the application filed on 10/03/2023. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged.
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Drawing
The drawing submitted on 10/03/2023 is acknowledged and accepted by the examiner.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/03/2023, 06/24/2025, and 10/13/2025 have been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 14-15, 17-20 are rejected under 35 U.S.C. 102(a)(1) and/or (a)(2) as being anticipated by SHINTAKU et al. (WO 2015008456 A1, hereinafter SHINTAKU).
Claim 1, SHINTAKU teaches a switch control circuit (e.g., see Fig. 1-20), comprising: a voltage conversion module (e.g., 11), comprising a first switch (e.g., 30), a second switch (e.g., 33), a third switch (e.g., 31), and a fourth switch (e.g., 35), wherein the first switch and the third switch constitute a first bridge arm, the second switch and the fourth switch constitute a second bridge arm, and the voltage conversion module is configured to receive an input voltage (e.g., 28), and operate, based on the input voltage, in at least one of a boost mode, a buck mode and a buck-boost mode (e.g., see Fig. 1, 3); a control module (e.g., 27), wherein the control module is configured to control the first switch and the third switch to switch, at a first switching frequency (e.g., f0), between an on-state and an off-state, and control the second switch and the fourth switch to switch, at a second switching frequency (e.g., f2), between the on- state and the off-state, so as to control the voltage conversion module to operate in the boost mode and perform a boost conversion on the input voltage (e.g., within Rs2, see Fig. 3); and the control module is further configured to control the first switch and the third switch to switch, at the second switching frequency, between the on-state and the off-state, and control the second switch and the fourth switch to switch, at the first switching frequency, between the on-state and the off-state, so as to control the voltage conversion module to operate in the buck mode and perform a buck conversion on the input voltage (e.g., within Rs3), the first switching frequency being less than the second switching frequency (e.g., see Fig. 3).
Claim 2, SHINTAKU teaches the limitations of claim 1 as discussed above. It further teaches that wherein the first switch is connected with an input terminal (e.g., 15) of the voltage conversion module, and the second switch is connected with an output terminal (e.g., 19) of the voltage conversion module; when the first switch is in the on-state, the third switch is in the off-state (e.g., see Fig. 4, 7); when the first switch is in the off-state, the third switch is in the on-state (e.g., see Fig. 4, 7); and in the boost mode, an on-time during which the first switch is in the on-state is longer than an off-time during which the first switch is in the off- state (e.g., during in the boost mode, see Fig. 9); when the second switch is in the on-state, the fourth switch is in the off-state (e.g., see Fig. 4-8); when the second switch is in the off-state, the fourth switch is in the on-state (e.g., see Fig. 4-8); and in the buck mode, an on-time during which the second switch is in the on-state is longer than an off-time during which the second switch is in the off-state (e.g., ., during in the buck mode, see Fig. 4-5).
Claim 3, SHINTAKU teaches the limitations of claim 2 as discussed above. It further teaches that wherein the switch control circuit further comprises a first driving circuit and a second driving circuit (e.g., the corresponding drive circuit for 30 of 27), the first driving circuit is connected with the first switch, and the second driving circuit is connected with the second switch (e.g., the corresponding drive circuit for 33 of 27); the control module is further configured to: send, according to the first switching frequency, a first pulse signal to the first driving circuit, when the voltage conversion module operates in the boost mode (e.g., during Rs2, see Fig. 1, 3); and send, according to the first switching frequency, the first pulse signal to the second driving circuit, when the voltage conversion module operates in the buck mode (e.g., during Rs3, see Fig. 1, 3), wherein a pulse frequency of the first pulse signal is equal to the first switching frequency (e.g., see Fig. 3); the first driving circuit is configured to, when the received first pulse signal is a first level signal (e.g., High), provide a driving voltage to the first switch so as to drive the first switch to keep being in the on-state (e.g., see Fig. 4-9); and the second driving circuit is configured to, when the received first pulse signal is the first level signal, provide a driving voltage to the second switch so as to drive the second switch to keep being in the on-state (e.g., see Fig. 4-8).
Claim 14, SHINTAKU teaches an electronic device, comprising a control switch circuit (e.g., see Fig. 1-20), wherein the control switch circuit comprises: a voltage conversion module (e.g., 11), comprising a first switch (e.g., 30), a second switch (e.g., 33), a third switch (e.g., 31), and a fourth switch (e.g., 35), wherein the first switch and the third switch constitute a first bridge arm, the second switch and the fourth switch constitute a second bridge arm, and the voltage conversion module is configured to receive an input voltage (e.g., 28), and operate, based on the input voltage, in at least one of a boost mode, a buck mode and a buck-boost mode (e.g., see Fig. 1, 3); a control module (e.g., 27), wherein the control module is configured to control the first switch and the third switch to switch, at a first switching frequency (e.g., f0), between an on-state and an off-state, and control the second switch and the fourth switch to switch, at a second switching frequency (e.g., f2), between the on- state and the off-state, so as to control the voltage conversion module to operate in the boost mode and perform a boost conversion on the input voltage (e.g., within Rs2, see Fig. 3); and the control module is further configured to control the first switch and the third switch to switch, at the second switching frequency, between the on-state and the off-state, and control the second switch and the fourth switch to switch, at the first switching frequency, between the on-state and the off-state, so as to control the voltage conversion module to operate in the buck mode and perform a buck conversion on the input voltage (e.g., within Rs3), the first switching frequency being less than the second switching frequency (e.g., see Fig. 3).
Claim 15, SHINTAKU teaches the limitations of claim 14 as discussed above. It further teaches that wherein the first switch is connected with an input terminal (e.g., 15) of the voltage conversion module, and the second switch is connected with an output terminal (e.g., 19) of the voltage conversion module; when the first switch is in the on-state, the third switch is in the off-state (e.g., see Fig. 4, 7); when the first switch is in the off-state, the third switch is in the on-state (e.g., see Fig. 4, 7); and in the boost mode, an on-time during which the first switch is in the on-state is longer than an off-time during which the first switch is in the off- state (e.g., ., during in the boost mode, see Fig. 9); when the second switch is in the on-state, the fourth switch is in the off-state (e.g., see Fig. 4-8); when the second switch is in the off-state, the fourth switch is in the on-state (e.g., see Fig. 4-8); and in the buck mode, an on-time during which the second switch is in the on-state is longer than an off-time during which the second switch is in the off-state (e.g., during in the buck mode, see Fig. 4-5); wherein the switch control circuit further comprises a first driving circuit and a second driving circuit (e.g., the corresponding drive circuit for 30 of 27), the first driving circuit is connected with the first switch, and the second driving circuit is connected with the second switch (e.g., the corresponding drive circuit for 33 of 27); the control module is further configured to: send, according to the first switching frequency, a first pulse signal to the first driving circuit, when the voltage conversion module operates in the boost mode (e.g., during Rs2, see Fig. 1, 3); and send, according to the first switching frequency, the first pulse signal to the second driving circuit, when the voltage conversion module operates in the buck mode (e.g., during Rs3, see Fig. 1, 3), wherein a pulse frequency of the first pulse signal is equal to the first switching frequency (e.g., see Fig. 3); the first driving circuit is configured to, when the received first pulse signal is a first level signal (e.g., High), provide a driving voltage to the first switch so as to drive the first switch to keep being in the on-state (e.g., see Fig. 4-9); and the second driving circuit is configured to, when the received first pulse signal is the first level signal, provide a driving voltage to the second switch so as to drive the second switch to keep being in the on-state (e.g., see Fig. 4-8).
For method claims 17-20, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated.
Claims 1, 11-13 are rejected under 35 U.S.C. 102(a)(1) and/or (a)(2) as being anticipated by Xie et al. (US Patent or PG Pub. No. 20200373841, hereinafter ‘841).
Claim 1, ‘841 teaches a switch control circuit (e.g., see Fig. 1-11), comprising:
a voltage conversion module (e.g., 104/200), comprising a first switch (e.g., 205), a second switch (e.g., 220), a third switch (e.g., 210), and a fourth switch (e.g., 215), wherein the first switch and the third switch constitute a first bridge arm, the second switch and the fourth switch constitute a second bridge arm, and the voltage conversion module is configured to receive an input voltage (e.g., Vin), and operate, based on the input voltage, in at least one of a boost mode, a buck mode and a buck-boost mode (e.g., see Fig. 4, 5); a control module (e.g., 102), wherein the control module is configured to control the first switch and the third switch to switch, at a first switching frequency (e.g., a first switching frequency, see Fig. 5), between an on-state and an off-state, and control the second switch and the fourth switch to switch, at a second switching frequency (e.g., a second switching frequency higher than first switching frequency, see Fig. 5), between the on- state and the off-state, so as to control the voltage conversion module to operate in the boost mode and perform a boost conversion on the input voltage (e.g., within the range of Vout/Vin>1, see Fig. 5); and the control module is further configured to control the first switch and the third switch to switch, at the second switching frequency, between the on-state and the off-state, and control the second switch and the fourth switch to switch, at the first switching frequency, between the on-state and the off-state, so as to control the voltage conversion module to operate in the buck mode and perform a buck conversion on the input voltage (e.g., within the range of Vout/Vin<1, see Fig. 5), the first switching frequency being less than the second switching frequency (e.g., see Fig. 5).
Claim 11, ‘841 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the control module is further configured to: obtain a voltage comparison result (e.g., the outputs of 304 and/or 306, see Fig. 3) between the input voltage and an output voltage of the voltage conversion module; and control, according to the voltage comparison result, the voltage conversion module to operate in the at least one of the boost mode, the buck mode, and the boost-buck mode (e.g., see Fig. 3-5).
Claim 12, ‘841 teaches the limitations of claim 11 as discussed above. It further teaches that wherein the control module is further configured to: control the voltage conversion module to operate in the boost mode (e.g., state 406), when the voltage comparison result shows that the input voltage is less than the output voltage and an absolute difference between the output voltage and the input voltage is greater than a first threshold (e.g., see Fig. 4); and control the voltage conversion module to operate in the buck mode (e.g., state 402), when the voltage comparison result shows that the input voltage is greater than the output voltage and the absolute difference between the input voltage and the output voltage is greater than a second threshold (e.g., see Fig. 4).
Claim 13, ‘841 teaches the limitations of claim 11 as discussed above. It further teaches that wherein the control module is further configured to, when the voltage comparison result shows that an absolute difference between the input voltage and the output voltage is less than a third threshold, control each of the first switch, the second switch, the third switch, and the fourth switch to switch, at the first switching frequency (e.g., the switching frequency within Buck-Boost reign, see Fig. 5), between the on-state and the off-state, so as to control the voltage conversion module to operate in the buck-boost mode (e.g., state 404, see Fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1,148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating
obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims under 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of 35 U.S.C. 103(c) and potential 35 U.S.C. 102(e), (f) or (g) prior art under 35 U.S.C. 103(a).
Claim 16 is rejected under 35 U.S.C. 103(a) as being unpatentable over SHINTAKU et al. (WO 2015008456 A1, hereinafter SHINTAKU), in view of Xie et al. (US Patent or PG Pub. No. 20200373841, hereinafter ‘841).
Claim 16, SHINTAKU teaches a teaches the limitations of claim 1 as discussed above. SHINTAKU does not explicitly disclose that wherein the control module is further configured to: obtain a voltage comparison result between the input voltage and an output voltage of the voltage conversion module; and control, according to the voltage comparison result, the voltage conversion module to operate in the at least one of the boost mode, the buck mode, and the boost-buck mode.
‘841 discloses a buck-boost converter (e.g., 100) with a state machine control module to control the operation of the converter (e.g., 102, see Fig. 1-11). ‘841 further discloses that wherein the control module is further configured to: obtain a voltage comparison result (e.g., the outputs of 304 and/or 306, see Fig. 3) between the input voltage and an output voltage of the voltage conversion module; and control, according to the voltage comparison result, the voltage conversion module to operate in the at least one of the boost mode, the buck mode, and the boost-buck mode (e.g., see Fig. 3-5).
Therefore, It would have been obvious to one having ordinary skill in the art before the effective filing date to modify SHINTAKU by including the obtain a voltage comparison result between the input voltage and an output voltage of the voltage conversion module; and control, according to the voltage comparison result, the voltage conversion module to operate in the at least one of the boost mode, the buck mode, and the boost-buck mode as taught by Kawano in order of being able to operate the converter in a wide range of the switching frequency (e.g., see claim 21, Fig. 5).
Allowable Subject Matter
Claims 4-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matters:
For claims 4-7, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily,… wherein the first driving circuit having a fifth switch, a sixth switch and a first capacitor, …; …; the fifth switch … in the on-state when the first pulse signal sent by the control module is the first level signal, … in the off-state when the first pulse signal sent by the control module is a second level signal; …; … the first capacitor … to, when the fifth switch is in the on-state, provide the driving voltage to the first switch …; wherein in the first pulse signal, a time ratio of the first level signal in each pulse period is greater than a time ratio of the second level signal in the pulse period.
For claims 8-9, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily,… wherein the second driving circuit having a seventh switch, an eighth switch and a second capacitor, …; …, … a second terminal of the second capacitor is connected with the eighth switch; the seventh switch is configured to be in the on-state when the first pulse signal sent by the control module is the first level signal, …; the eighth switch is … in the on-state when the first pulse signal sent by the control module is the second level signal, …; … the second capacitor …, provide a driving voltage to the second switch …; wherein in the first pulse signal, a time ratio of the first level signal in each pulse period is greater than a time ratio of the second level signal in the pulse period.
For claims 10, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily,… wherein the switch control circuit further having a reverse module, a third driving circuit and a fourth driving circuit, the third driving circuit …; …; the reverse module … to: reverse the first pulse signal output by the control module, … to obtain a second pulse signal; send the second pulse signal to the third driving circuit, when a determined operating mode is the boost mode; …, when the determined operating mode is the buck mode; the third driving circuit … to, … keep being in the on-state; … the fourth driving circuit … to, when the received second pulse signal is the first level signal, drive the fourth switch to keep being in the on-state.
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUE ZHANG whose telephone number is (571)270-1263. The examiner can normally be reached on M-F: 8:30AM-5:00PM
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-2838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUE ZHANG/
Primary Examiner, Art Unit 2838