Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 19 November 2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 1 (and dependent claims 2-10) recite “An outlier integrated circuit (IC) detection method comprising: acquiring first measured data of a first IC set; training the first measured data for establishing a training model; acquiring second measured data of a second IC set; generating predicted data of the second IC set by using the training model according to the second measured data; generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data; acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set; and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance; wherein the first IC set and the second IC set are different, and the at least one outlier IC is withdrawn from the second IC set.”
Claims 1-10, in view of the claim limitations, recite the abstract idea of “acquiring first measured data of a first IC set; training the first measured data for establishing a training model; acquiring second measured data of a second IC set; generating predicted data of the second IC set by using the training model according to the second measured data; generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data; acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set; and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance; wherein the first IC set and the second IC set are different, and the at least one outlier IC is withdrawn from the second IC set.”
As a whole, in view of the claim limitations, but for the computer components and systems performing the claimed functions, the broadest reasonable interpretation of the recited “acquiring first measured data of a first IC set; training the first measured data for establishing a training model; acquiring second measured data of a second IC set; generating predicted data of the second IC set by using the training model according to the second measured data; generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data; acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set; and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance; wherein the first IC set and the second IC set are different, and the at least one outlier IC is withdrawn from the second IC set.”; therefore, the claims recite mental processes. Accordingly, the claims recite a mental process, and thus, the claims recite an abstract idea under the first prong of Step 2A.
This judicial exception is not integrated into a practical application under the second prong of Step 2A. In particular, the claims recite the additional elements beyond the recited abstract idea of“[a] computer- implemented method” and “the method is carried out by one or more physical processors configured by machine-readable instructions” as recited in claim 11, individually and when viewed as an ordered combination, and pursuant to the broadest reasonable interpretation, each of the additional elements are computing elements recited at high level of generality implementing the abstract idea on a computer (i.e. apply it), and thus, are no more than applying the abstract idea with generic computer components. Moreover, aside from the aforementioned additional elements, the remaining elements of dependent claims 12-20 do not integrate the abstract idea into a practical application because these claims merely recite further limitations that provide no more than simply narrowing the recited abstract idea.
The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception under Step 2B. As noted above, the aforementioned additional elements beyond the recited abstract idea, as an order combination, are no more than mere instructions to implement the idea using generic computer components (i.e. apply it), and further, generally link the abstract idea to a field of use, which is not sufficient to amount to significantly more than an abstract idea; therefore, the additional elements are not sufficient to amount to significantly more than an abstract idea. Additionally, these recitations as an ordered combination, simply append the abstract idea to recitations of generic computer structure performing generic computer functions that are well-understood, routine, and conventional in the field as evinced by Applicant’s Specification at [0029] (describing that the disclosure is not limited to the disclosed implementations, but, on the contrary, is intended to cover modifications and equivalent arrangements that are within the spirit and scope of the appended claims). Furthermore, as an ordered combination, these elements amount to generic computer components performing repetitive calculations, receiving or transmitting data over a network, which, as held by the courts, are well-understood, routine, and conventional. See MPEP 2106.05(d); July 2015 Update, p. 7. Moreover, aside from the aforementioned additional elements, the remaining elements of dependent claims 2-10 and 12-20 do not transform the recited abstract idea into a patent eligible invention because these claims merely recite further limitations that provide no more than simply narrowing the recited abstract idea. Looking at these limitations as an ordered combination adds nothing additional that is sufficient to amount to significantly more than the recited abstract idea because they simply provide instructions to use a generic arrangement of generic computer components and recitations of generic computer structure that perform well-understood, routine, and conventional computer functions that are used to “apply” the recited abstract idea. Thus, the elements of the claims, considered both individually and as an ordered combination, are not sufficient to ensure that the claim as a whole amounts to significantly more than the abstract idea itself. Since there are no limitations in these claims that transform the exception into a patent eligible application such that these claims amount to significantly more than the exception itself, claims 1-20 are rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Landman et al (US 11,762,013) disclose a computerized method for IC classification, outlier detection and/or anomaly detection that includes using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design includes a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC. Ophir et al (US 11,410,290) disclose a method that includes: calculating training data concerning metrology metric(s) from initial metrology measurements, applying machine learning algorithm(s) to the calculated training data to derive an estimation model of the metrology metric(s), deriving measurement data from images of sites on received wafers, and using the estimation model to provide estimations of the metrology metric(s) with respect to the measurement data. While the training data may use two images per site, in operation a single image per site may suffice—reducing the measurement time to less than half the current measurement time. Yennie et al (US 10,795,346) disclose a method that includes: receiving a plurality of sets of training data, storing a plurality of machine learning models, storing a plurality of physical process models, receiving a selection of a machine learning model from the plurality of machine learning models and a selection of a physical process model from the plurality of physical process models, generating an implemented machine learning model according to the selected machine learning model, calculating a characterizing value for each training spectrum in each set of training data thereby generating a plurality of training characterizing values with each training characterizing value associated with one of the plurality of training spectra, training the implemented machine learning model using the plurality of training characterizing values and plurality of training spectra to generate a trained machine learning model, and passing the trained machine learning model to a control system of the substrate processing system.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AN H DO whose telephone number is (571)272-2143. The examiner can normally be reached on M-F 7:00am-4:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ricardo Magallanes can be reached on 571-272-5960. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AN H DO/Primary Examiner, Art Unit 2853