DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election, without traverse, of Group I, claims 1-21 in the “Reply To Restriction Requirement” filed on February 3, 2026 is acknowledged. Claims 22-27 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to the nonelected inventions of Group II, claim 22 and Group III, claims 23-27, as detailed in the Restriction Requirement dated December 3, 2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9, 20, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0144309 A1 (Jeon).
Regarding claim 1, Jeon discloses, A display panel (display panel (100); FIG. 3; [0039])), comprising:
a substrate (substrate (110); FIG. 3; [0039]);
a first storage capacitor electrode (first storage capacitor electrode (141); FIG. 3; [0052]) disposed on the substrate (110);
an active layer (active layer (131); FIG. 3; [0057]) disposed on the first storage capacitor electrode (141) and including a first area (first area (131c); FIG. 3; [0058]), a second area (second area (131b); FIG. 3; [0058]) and a channel area (first area (131a); FIG. 3; [0058]) disposed between the first area (131c) and the second area (131b), wherein the first area (131c) and the second area (131b) of the active layer (131) are conductive areas ([0066]);
a gate electrode (gate electrode (134); FIG. 3; [0057]) disposed on the active layer (131) and overlapping with the channel area (131a) (FIG. 3); and
a metal layer (metal layer (170); FIG. 3; [0039]) disposed on the gate electrode (134); and
a conductive auxiliary layer (conductive auxiliary layer (132 and 133); FIG. 3; [0057])) disposed on the substrate (110) and overlapping with at least a portion of each of the first area (131c) and the second area (131b) and not overlapping with the channel area (131a) (FIG. 3).
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Regarding claim 2, Jeon discloses, The display panel (100) of claim 1, wherein the conductive auxiliary layer (132 and 133) is disposed on the active layer(131), and
wherein the conductive auxiliary layer (132 and 133) includes a first conductive auxiliary layer (133) overlapping with the first area (131c) of the active layer (131) (FIG. 3) and a second conductive auxiliary layer (132) overlapping with the second area (131b) of the active layer (131) (FIG. 3).
Regarding claim 3, Jeon discloses, The display panel (100) of claim 2, wherein the gate electrode (134) is disposed between the first conductive auxiliary layer (133) and the second conductive auxiliary layer (132) (FIG. 3).
Regarding claim 4, Jeon discloses, The display panel (100) of claim 3, wherein one side surface of the conductive auxiliary layer (133) contacts one side surface of the gate electrode (134) (FIG. 3; [0033] of Applicant’s specification—When it is mentioned that a first element “is connected or coupled to”, "contacts or overlaps" etc. a second element, it should be interpreted that, not only may the first element "be directly connected or coupled to" or "directly contact or overlap with" the second element, but a third element may also be "interposed" between the first and second elements, or the first and second elements may “be connected or coupled to”, "contact or overlap with", etc. each other via a fourth element. Here, the second element may be included in at least one of two or more elements that “are connected or coupled to”, "contact or overlap with," etc. each other).
Regarding claim 5, Jeon discloses, The display panel (100) of claim 3, wherein one side surface of the conductive auxiliary layer (132 and 133) is spaced apart from one side surface of the gate electrode (134) (FIG. 3).
Regarding claim 6, Jeon discloses, The display panel (100) of claim 1, further comprising a buffer layer (buffer layer (114); FIG. 3; [0039]) disposed between the first storage capacitor electrode (141) and the active layer (131),
wherein the first storage capacitor electrode (141) overlaps with the active layer (131), and
wherein the conductive auxiliary layer (132 and 133) is disposed between the first storage capacitor electrode (141) and the buffer layer (114) (FIG. 3).
Regarding claim 7, Jeon discloses, The display panel (100) of claim 1, further comprising a buffer layer (buffer layer (114); FIG. 3; [0039]) disposed between the first storage capacitor electrode (141) and the active layer (131),
wherein the conductive auxiliary layer (132 and 133) is disposed between the buffer layer (114) and the active layer (131).
Regarding claim 8, Jeon discloses, The display panel (100) of claim 7, wherein one surface (annotated FIG. 3, above) of the conductive auxiliary layer (132 and 133) contacts one surface of the first area (131c) of the active layer (131) and one surface of the second area (131b) of the active layer (131).
Regarding claim 9, Jeon discloses, The display panel (100) of claim 1, wherein a thickness (annotated FIG. 3, above) of the conductive auxiliary layer (132 and 133) increases as a distance between the conductive auxiliary layer (132 and 133) and the active layer (131) increases (annotated FIG. 3, above).
Regarding claim 20, Jeon discloses, The display panel (100) of claim 1, wherein the metal layer (170) and the active layer (131) overlap with each other (FIG. 3).
Regarding claim 21, Jeon discloses, The display panel (100) of claim 1, wherein auxiliary electrodes (auxiliary electrodes (150); FIG. 3; [0039]) are disposed on at least portions of respective upper surfaces of the first area (131c) and the second area (131b) of the active layer (131) (FIG. 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims, the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 10-18 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon.
Regarding claim 10, Jeon discloses, The display panel (100) of claim 1, further comprising:
a second storage capacitor electrode (second storage capacitor electrode (142); FIG. 3; [0055]) overlapping with the first storage capacitor electrode (141) (FIG. 3); and
a third storage capacitor electrode (third storage capacitor electrode (150); FIG. 3; [0039]) overlapping with the second storage capacitor electrode (142) and disposed on the conductive auxiliary layer (132 and 133),
wherein the metal layer (170) overlaps with the third storage capacitor electrode (150) (FIG. 3).
But, Applicant may argue that Jeon does not appear to explicitly disclose, that the third storage capacitor electrode disposed on the same layer as the active layer.
However, there are a finite number of predicable solutions regarding the problem of disposal of the third storage capacitor electrode of Jeon relative to the active layer of Jeon—i.e., (i) the third storage capacitor electrode can be disposed on a different layer than the active layer or (ii) the third storage capacitor electrode can be disposed on the same layer as the active layer—and, absent unexpected results, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try each of them with a reasonable expectation of success, one of which is: that the third storage capacitor electrode(150) is disposed on the same layer as the active layer (131), as recited in dependent claim 10. Please see, MPEP 2143(E)—“Obvious To Try”—Choosing From A Finite Number Of Identified, Predicable Solutions, With A Reasonable Expectation Of Success.
Regarding claim 11, Jeon discloses, The display panel (100) of claim 10, wherein the conductive auxiliary layer (132 and 133) overlaps with at least a portion of the second storage capacitor electrode (142) (FIG. 3 and [0033] of Applicant’s specification—When it is mentioned that a first element “is connected or coupled to”, "contacts or overlaps" etc. a second element, it should be interpreted that, not only may the first element "be directly connected or coupled to" or "directly contact or overlap with" the second element, but a third element may also be "interposed" between the first and second elements, or the first and second elements may “be connected or coupled to”, "contact or overlap with", etc. each other via a fourth element. Here, the second element may be included in at least one of two or more elements that “are connected or coupled to”, "contact or overlap with," etc. each other).
Regarding claim 12, Jeon discloses, The display panel (100) of claim 11, wherein the conductive auxiliary layer (132 and 133) is disposed between the active layer (131) and the third storage capacitor electrode (150).
Regarding claim 13, Jeon discloses, The display panel (100) of claim 11, further comprising a buffer layer (buffer layer (114); FIG. 3; [0039]) disposed between the first storage capacitor electrode (141) and the active layer (131),
wherein the conductive auxiliary layer (132 and 133) is disposed between the first storage capacitor electrode (141) and the buffer layer (114) (FIG. 3).
Regarding claim 14, Jeon discloses, The display panel (100) of claim 11, further comprising a buffer layer (buffer layer (114); FIG. 3; [0039]) disposed between the first storage capacitor electrode (141) and the active layer (131),
wherein the conductive auxiliary layer (132 and 133) is disposed between the buffer layer (114) and the second storage capacitor electrode (142).
Regarding claim 15, Jeon discloses, The display panel (100) of claim 14, wherein one surface of the conductive auxiliary layer (132 and 133) contacts one surface of the second storage capacitor electrode (142) (FIG. 3 and [0033] of Applicant’s specification—When it is mentioned that a first element “is connected or coupled to”, "contacts or overlaps" etc. a second element, it should be interpreted that, not only may the first element "be directly connected or coupled to" or "directly contact or overlap with" the second element, but a third element may also be "interposed" between the first and second elements, or the first and second elements may “be connected or coupled to”, "contact or overlap with", etc. each other via a fourth element. Here, the second element may be included in at least one of two or more elements that “are connected or coupled to”, "contact or overlap with," etc. each other).
Regarding claim 16, Jeon discloses, The display panel (100) of claim 10, wherein the metal layer (170) is either a source electrode or a drain electrode of a thin film transistor, (metal layer (170) is connected to drain (131c) of thin film transistor (131) via (133), (150), and (160), thereby making it a drain electrode).
wherein the metal layer (170) is electrically connected to the second storage capacitor electrode (142) (electrically connected via (150) and (160); FIG. 3), and
wherein the third storage capacitor electrode (150) is electrically connected to the first storage capacitor electrode (141) (FIG. 3 and [0033] of Applicant’s specification—When it is mentioned that a first element “is connected or coupled to”, "contacts or overlaps" etc. a second element, it should be interpreted that, not only may the first element "be directly connected or coupled to" or "directly contact or overlap with" the second element, but a third element may also be "interposed" between the first and second elements, or the first and second elements may “be connected or coupled to”, "contact or overlap with", etc. each other via a fourth element. Here, the second element may be included in at least one of two or more elements that “are connected or coupled to”, "contact or overlap with," etc. each other).
Regarding claim 17, Jeon discloses, The display panel (100) of claim 10, wherein a thickness (annotated FIG. 3, above) of the conductive auxiliary layer(132 and 133) increases as a distance between the conductive auxiliary layer (132 and 133) and the second storage capacitor electrode (142) increases (annotated FIG. 3, above).
Regarding claim 18, Jeon discloses, The display panel (100) of claim 10, further comprising a gate insulation film (gate insulation film (115); FIG. 3; [0039]) and an inter-layer insulation film (inter-layer insulating film (118); FIG. 3; [0039] and [0079]),
wherein the gate insulation film (115) is disposed between the second storage capacitor electrode (142) and the third storage capacitor electrode (150),
wherein the inter-layer insulation film (118) is disposed between the third storage capacitor electrode (150) and the metal layer (170), and
wherein a thickness of the inter-layer insulation film (118) is larger than a thickness of the gate insulation film (115) (FIG. 3).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of US 2020/0264484 A1 (Jinnai).
Regarding claim 19, Jeon does not appear to explicitly disclose, wherein the conductive auxiliary layer includes silicon nitride (SiNx) or silicon oxynitride (SiON).
However, in analogous art, Jinnai discloses that it is well known that a conductive layer (conductive layer (141); FIG. 2; [0051]) can be predicably fabricated to include silicon nitride (silicon nitride (142); FIG. 2; [0052]). Jinnai also that silicon nitride (142) is a capacitive insulating film ([0052]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Jeon and Jinnai before him/her that conductive auxiliary layer (132 and 133) of Jeon includes silicon nitride (SiNx), as taught by Jinnai, or silicon oxynitride (SiON) to provide a capacitive insulating film, as also taught by Jinnai ([0031] of Applicant’s specification—The terms such as "including," "having," "containing," "constituting" "make up of," and "formed of' used herein are generally intended to allow other components to be added unless the terms are used with the term "only."). See, also MPEP 2144(IV)—Rational Different From Applicant’s Is Permissible.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2023/0088235 A1 (Luo)—Discloses a display device (FIG. 1) that includes a substrate (100), an active layer (101) that includes a first area (102), a second area (103), and a channel area (101), a gate electrode (104), and a gate insulating layer (150). Luo also discloses a light shielding layer (130) and a storage capacitor (30) that includes a first storage capacitor electrode (301) and a second capacitor electrode (302).
US2021/0183977 A1 (Xiao)—Discloses a display device (FIG. 2) having a substrate (101), a light shielding layer (102), an active layer (104), a gate electrode (106), and a gate insulating layer (105). Also discloses a storage capacitor that includes a first capacitor electrode (115) and a second capacitor electrode (117).
US 2022/0208804 A1 (Jang)—Discloses a display device (FIG. 6B) having a first storage capacitor (Cst1_1) and a second storage capacitor (CST1_2).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812