CTNF 18/377,740 CTNF 101375 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This action is in response to the application and claims filed 10/06/2023. Claims 1-21 are pending and have been examined. Claims 1-21 are rejected. Priority The examiner acknowledges the priority benefit to U.S. Provisional Application No. 63/414,847, filed on 10/10/2022. The present application claims priority to U.S. Provisional Application No. 63/414,847, filed on 10/10/2022. Claim Objections Claim 1-21 are objected to because they are not numbered consecutively. Specifically, the claim listing omits claim numbers 8 and 18, jumping from claim 7 to 9 and from claim 17 to 19. Appropriate correction is required. 07-29-01 AIA Claim 7 and 17 are objected to because of the following informalities: The claim introduces “M” (uppercase) as the number of qubits in the quantum device, but then recites the size formula using “m” (lowercase) in exponent . Appropriate correction is required. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 11-20 rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because they are directed to a “A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations” which encompasses signal per se. The specification fails to provide a limiting definition. For example, see Paragraph 161 of the instant application where the “machine-readable medium” is described as to include “a non-transitory computer readable medium” but also “transitory computer machine-readable communication media (e.g., electrical, optical, acoustical or other form of propagated signals - such as carrier waves, infrared signals, digital signals, etc.).” Therefore, the specification fails to explicitly exclude signals per se and given the broadest reasonable interpretation in light of the specification , claims 11-20 include signals per se. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Examiner’s Note: Some rejections will include an Examiner’s Note (labeled ‘EN’) to provide additional context or rationale explaining the basis for the rejection. 07-15-aia AIA Claim(s) 1-4, 7, 9, 11-14, 17, 19, 21 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by non-patent literature Shirakawa et al. (“Automatic quantum circuit encoding of a given arbitrary quantum state”, hereinafter “Shirakawa”.) Claim 1 Shirakawa teaches: A method, comprising: (Page 1, “We propose a quantum-classical hybrid algorithm, named automatic quantum circuit encoding (AQCE)”) receiving an input tensor corresponding to a quantum state; (Page 8, “The inputs of the AQCE algorithm are a target quantum state |Ψ, a quantum circuit ˆC set to be the identity operator ˆI, and a set of bonds B of two qubits (or a set of clusters C of K qubits), as shown in Fig. 4(a).” Page 9, PNG media_image1.png 551 434 media_image1.png Greyscale Page 13, PNG media_image2.png 143 462 media_image2.png Greyscale EN: this denotes Ψ which corresponds to the input tensor which also corresponds to a quantum state.) performing a sequence of tensor network operations on the input tensor to determine an output tensor representing an ordered list of quantum gates to be executed by a specified target quantum device, (Page 1, “The key ingredient of the algorithm is the sequential determination of a set of optimal two-qubit unitary operators one by one via the singular value decomposition of the fidelity tensor. Once the optimal unitary operators are determined, including the location of qubits on which each unitary operator acts, elementary quantum gates are assigned algebraically.” Page 15, “Therefore, here we instead experimentally demonstrate that the AQCE algorithm indeed generates a quantum circuit that can be implemented on a real quantum device to produce a desired quantum state with reasonable accuracy. For this demonstration, we use a quantum device (ibmq_lima) provided by IBM Quantum” – EN: this denotes performing sequential tensor optimizations on the input state to determine optimal unitary gate operators that are decomposed into an ordered list of quantum gates to be used on the target quantum computer, such as the IBM Quantum.) wherein the sequence of tensor network operations include a plurality of singular value decomposition (SVD) operations and (Page 4, “ PNG media_image3.png 293 638 media_image3.png Greyscale Page 5, PNG media_image4.png 498 624 media_image4.png Greyscale EN: this denotes performing SVDs on the tensor matrices during each sequential optimization step to compute candidate gate updates.) one or more operations to ensure that the output tensor is unitary. (Page 4, PNG media_image5.png 179 648 media_image5.png Greyscale Page 6, PNG media_image6.png 104 611 media_image6.png Greyscale EN: this denotes the calculated output tensor representing the gate update is unitary by setting it equal to the matrix product of the unitary matrices X and Y obtained from the SVD.) Claim 2 Shirakawa teaches: The method of claim 1 wherein the sequence of tensor network operations are performed based on specified hardware capabilities of the target quantum device to execute the ordered list of quantum gates. (Page 17, “Considering a set of bonds B in the AQCE algorithm, it is wise to include only pairs of qubits that are physically connected in the quantum device so as to decrease the number of extra quantum gates.” – EN: this denotes performing the tensor network sequence based on target hardware capabilities. i.e. adjusting the candidate gate operations strictly to pairs of qubits that possess direct physical connections on the target execution device.) Claim 3 Shirakawa teaches: The method of claim 2 wherein the hardware capabilities of the target quantum device include a particular number of qubits and a particular connectivity between the qubits. (Page 16, PNG media_image7.png 414 925 media_image7.png Greyscale Also see page 17, “In the quantum device employed in this demonstration, there are only two pairs of qubits: B = {{0,1},{1,2}” -- EN: this denotes specifying a particular number of connected qubits and their specific connection topology on the execution device. Claim 4 Shirakawa teaches: The method of claim 1 wherein the plurality of SVD operations include one or more truncations, contractions, and/or decompositions. (Page 3, PNG media_image8.png 141 471 media_image8.png Greyscale EN: this denotes the SVD operations including contractions. Taking a partial trace over the remaining qubits requires summing over their shared inner components, this fundamentally uses a tensor contraction operation. Page 4, PNG media_image9.png 66 455 media_image9.png Greyscale EN: this denotes decomposition.) Claim 7 Shirakawa teaches: The method of claim 1 wherein for a quantum device comprising M qubits, the input tensor is limited to a size of N=2 m . (Page 2-3, PNG media_image10.png 302 473 media_image10.png Greyscale PNG media_image11.png 271 471 media_image11.png Greyscale EN: this denotes variable L which corresponds to the M in the claim. The Hilbert space spanned by zero-indexed states up to a (2 L – 1) which limits the input state tenor to a total size of N = 2 L . Example, if L = 3 qubits, the basis state indices n run from 0 to 2 3 – 1 = 7. Therefore, the states are: 0, 1, 2, 3, 4, 5, 6, 7 = 8 total elements (2 3 ). Claim 9 Shirakawa teaches: The method of claim 4 wherein each of the plurality of SVD operations are performed in view of a defined tensor network goal. (Page 12, “In order to optimize two qubit unitary operators ˆUm in the Trotter- and MERA like circuits for encoding a quantum state |Ψ, we perform 1000 sweeps of the forward and backward updates using the algorithm described in Sec. IID (also see Fig. 2), i.e., the quantum circuit encoding algorithm, but with the fixed circuit structures. – EN: this denotes that the SVD which involves contractions and decomposition as mapped to in claim 4 (“in Sec. IID (also see Fig. 2”) also are to strictly conform to pre-defined circuit structures (“with the fixed circuit structures”), thereby performing the operations in view of a defined tensor network goal (“In order to optimize… in the Trotter- and MERA like circuits… the fixed circuit structures”). Claim 11 Shirakawa teaches: A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of: (Page 20, “The calculation has been performed on the RIKEN supercomputer system (HOKUSAI Great Wave) and the supercomputer Fugaku installed in RIKEN R-CCS. – EN: The execution of the AQCE algorithm as numerical simulations on the supercomputers requires program code stored on a machine-readable medium.” The rest of claim 11 are substantially the same as claim 1, therefore claim 11 is rejected under the same rationale as claim 1. Claims 12-14, 17, 19 are machine-readable medium claims that recite the same limitations of claims 2-4, 7, 9 . Therefore, claims 12-14, 17, 19 are rejected under the same rationale as claim 2-4, 7, 9. Claim 21 An apparatus comprising: a memory to store program code and data; a processor to process the program code and data to perform a plurality of operations, comprising: (Page 20, “The calculation has been performed on the RIKEN supercomputer system (HOKUSAI Great Wave) and the supercomputer Fugaku installed in RIKEN R-CCS. – EN: The identified supercomputers are interpreted as apparatus that inherently comprise processors and memory storing program code and data, since performing the described numerical simulations require a processor executing stored program code operation on stored data.” The rest of claim 21 are substantially the same as claim 1, therefore claim 21 is rejected under the same rationale as claim 1 . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Examiner’s Note: Some rejections will include an Examiner’s Note (labeled ‘EN’) to provide additional context or rationale explaining the basis for the rejection. 07-21-aia AIA Claim s 5, 6, 15, 16 are rejected under 35 U.S.C. 103 as being unpatentable over non-patent literature Shirakawa et al. (“Automatic quantum circuit encoding of a given arbitrary quantum state”, hereinafter “Shirakawa”.) in view of non-patent literature Ran et al. (“Encoding of Matrix Product States into Quantum Circuits of One- and Two-Qubit Gates”, hereinafter “Ran”) . Claim 5 Ran teaches: The method of claim 1 wherein the one or more operations to ensure that the output tensor is unitary comprises adding indices to one or more gates of the ordered list of quantum gates. (Page 2, PNG media_image12.png 571 478 media_image12.png Greyscale EN: this denotes adding indices (expanding the tensor) to ensure it is a unitary quantum gate. Ran describes taking an MPS tensor, which is an isometry with 3 indices and mapping it to a two-qubit unitary gate, which requires 4 indices. To make the non-unitary tensor into a unitary gate, Ran adds an index (the i index), as shown in equation 7 and 8. Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to combine the SVD method and operations to get an output tensor that is unitary of Shirakawa with the index-adding technique during the process of generating the unitary output tensor of Ran. The motivation for doing so would be to be able to map lower-dimension, non-unitary tensors into unitary matrices so they can be executed as on one and two qubit gates on physical hardware. See the abstract on page 1 of Ran, “However, realizing an N-qubit MPS with large N and large entanglement on a quantum platform is extremely challenging, since it requires high-level qubits or n-qubit gates with n 2tocarryor produce the entanglement. In this work, an efficient method that accurately encodes a given MPS into a quantum circuit with only one- and two-qubit gates is proposed. Essentially different from the existing compiling methods, our idea is to construct the unitary matrix product operators that optimally disentangle the MPS to a product state.” Claim 6 Ran teaches: The method of claim 1 wherein the one or more operations to ensure that the output tensor is unitary comprises expanding a size of the input tensor while keeping one or more original scalar values fixed, and either (Page 2, PNG media_image13.png 111 417 media_image13.png Greyscale Page 3, PNG media_image14.png 57 414 media_image14.png Greyscale EN: The original MPS tensor A[n] is smaller than the gate tensor G[n]. Ran embeds (“keeps fixed”) the original values of A[n] into a specific block of larger tensor G[n]. For example, for a given 2x4 MPS tensor grid, we need to build a quantum gate. This may require a bigger table (4x4). Ran’s discloser teaches taking the 2x4 and pasting in into the top two rows of the new 4x4. Therefore, the original numbers don’t change, they sit where they were placed. Thus teaching “keeping one or more original scalar values fixed”. However, the table got bigger, from 2x4 to 4x4 thus teaching the “expanding a size of the input tensor”. determining vectors of a null space of original vectors in the input tensor and inserting these new vectors into new positions; or ( Page 2, (EN: this denotes for middle tensors) PNG media_image15.png 132 513 media_image15.png Greyscale Page 3, ( EN: this denotes for first tensor n =1) PNG media_image16.png 87 519 media_image16.png Greyscale Page 2, ( EN: this confirms the result is unitary) PNG media_image17.png 180 515 media_image17.png Greyscale EN: overall, this denotes after embedding A[n] into G[n], Ran fills in the remaining components by computing orthonormal vectors in the kernel (i.e., null space), and inserting those vectors into the unfilled spots of G[n].) (b) varying new scalar values variationally until the tensor is unitary. (EN: Ran does not explicitly teach option B, however claim 6 requires either A or B. Therefore, the claim as a whole is taught.) Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to combine the SVD method and operations to get an output tensor that is unitary of Shirakawa with the null-space kernel embedding technique of Ran. The motivation for doing so would be to provide an exact method of constructing unitary gates from the tensors in the MPS decomposition, thereby enabling the resulting quantum circuit to be made of valid one and two-qubit unitary gates that are prepared for implementation on the quantum hardware. See Equation 8 of Ran on page 2 and page 1 abstract, “This method paves a feasible and efficient path to realizing useful and/or exotic quantum states and MPS-based models as quantum circuits on the near-term quantum platforms.” Additionally, the instant application’s specification acknowledges the relevance of Ran’s technique at paragraph [0122]. Claims 15-16 are machine-readable medium claims that recite the same limitations of claims 5-6. Therefore, claims 15-16 are rejected under the same rationale as claim 5-6 . 07-21-aia AIA Claim s 10, 20 are rejected under 35 U.S.C. 103 as being unpatentable over non-patent literature Shirakawa et al. (“Automatic quantum circuit encoding of a given arbitrary quantum state”, hereinafter “Shirakawa”.) in view of US patent Ganzhorn et al. US 10452991 B1, hereinafter “Ganzhorn” . Claim 10 Ganzhorn teaches: performing one or more virtual compensation operations to mitigate errors when loading the ordered list of quantum gates on the target quantum device, (Col. 4, line 4-8, “A quantum gate for superconducting qubits is an electrical signal whose spectral content depends both on the desired gate and on the qubit parameters. Even a slight shift in qubit parameters (such as frequency) creates a mismatch between the signal applied and the system that this signal is driving” Col. 6, line 4-9, “Thus , and as the present Inventors have realized , an additional signal component can be embedded in the applied signals, which component is devised so as to shift ( in energy or frequency ) at least one state spanned by the quantum circuits , in order to compensate for cross - talk between the quantum circuits” – EN: this denotes that cross-talk causes gate errors and that a compensation operation is performed alongside gate execution to correct those errors.) the virtual compensation operations comprising generating pulses on one or more qubits (Col. 7, line 44-48, “The compensation signal may for instance simply be obtained by first generating S52 a signal with a frequency generator 52 , prior to gating S53 the generated signal to obtain a desired signal pulse , e . g . , using a gate 54 controlled by a gate controller 53 , as illustrated in FIG . 3” Col. 8, line 55-59, “In the example of FIG. 4 , the compensation signal is activated by applying a microwave tone on the tunable coupler 20 , which in turn induces a transition between the qubit states ( |11 ) and |02 > .” – EN: this denotes generating a gated microwave pulse that directly acts on the qubit energy levels.) based on data associated with the quantum device. (Col. 9, line 4-9, “Scanning the frequency of the compensation tone at a fixed power and measuring the induced frequency shift of 5 the 1 - ) state reveals that there is a point where the cross - talk induced 22 shift disappears , as identified by the dashed lines in FIG . 6, for a given set of qubit parameters” Col. 3, line 67 – Col. 4 line 3, “…the gate parameters no longer match the qubit parameters. All the more, this implies that transitions/gates on one qubit depends on the state of the other qubit in an uncontrolled manner.” – EN: this denotes the compensation pulse frequency and strength are determined by measuring the actual device’s qubit parameters and cross-talk characteristics, meaning the pulses are calibrated from device-specific data.) Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to combine the SVD method and operations to get an output tensor that is unitary of Shirakawa with the cross-talk compensation pulses applied during quantum gate execution of Ganzhorn. The motivation for doing so would be to mitigate hardware-induced errors that degrade gate fidelity. See Col. 4, line 4-13 of Ganzhorn, “A quantum gate for superconducting qubits is an electrical signal whose spectral content depends both on the desired gate and on the qubit parameters. Even a slight shift in qubit parameters (such as frequency) creates a mismatch between the signal applied and the system that this signal is driving. This hinders the operation of the qubits, inasmuch as it makes it difficult to achieve and calibrate single qubit gates that do not depend on the state of other qubits. Thus, such mismatches quickly deteriorate the accuracy of the quantum evolution” Claims 20 is a machine-readable medium claim that recite the same limitations of claims 10. Therefore, claim 20 are rejected under the same rationale as claim 10. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAYMUR RAHMAN ALI whose telephone number is (571)272-0007. The examiner can normally be reached Mon-Fri. 9:30-6:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexey Shmatov can be reached at (571)270-3428. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NAYMUR RAHMAN ALI/Examiner, Art Unit 2123 /ALEXEY SHMATOV/Supervisory Patent Examiner, Art Unit 2123 Application/Control Number: 18/377,740 Page 2 Art Unit: 2123 Application/Control Number: 18/377,740 Page 3 Art Unit: 2123 Application/Control Number: 18/377,740 Page 4 Art Unit: 2123 Application/Control Number: 18/377,740 Page 5 Art Unit: 2123 Application/Control Number: 18/377,740 Page 6 Art Unit: 2123 Application/Control Number: 18/377,740 Page 7 Art Unit: 2123 Application/Control Number: 18/377,740 Page 8 Art Unit: 2123 Application/Control Number: 18/377,740 Page 9 Art Unit: 2123 Application/Control Number: 18/377,740 Page 10 Art Unit: 2123 Application/Control Number: 18/377,740 Page 11 Art Unit: 2123 Application/Control Number: 18/377,740 Page 12 Art Unit: 2123 Application/Control Number: 18/377,740 Page 13 Art Unit: 2123 Application/Control Number: 18/377,740 Page 14 Art Unit: 2123 Application/Control Number: 18/377,740 Page 15 Art Unit: 2123
Prosecution Insights