Prosecution Insights
Last updated: August 17, 2026
Application No. 18/377,830

OPTIMIZING A NIC THAT EMULATES A LOCAL NVME STORAGE DEVICE FOR PROCESSES OF A HOST COMPUTER

Final Rejection §102§103
Filed
Oct 09, 2023
Examiner
SWIFT, CHARLES M
Art Unit
2196
Tech Center
2100 — Computer Architecture & Software
Assignee
VMware, Inc.
OA Round
2 (Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
722 granted / 891 resolved
+26.0% vs TC avg
Strong +22% interview lift
Without
With
+21.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
36 currently pending
Career history
936
Total Applications
across all art units

Statute-Specific Performance

§101
11.3%
-28.7% vs TC avg
§103
56.7%
+16.7% vs TC avg
§102
16.5%
-23.5% vs TC avg
§112
6.2%
-33.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 891 resolved cases

Office Action

§102 §103
DETAILED ACTION This office action is in response to amendment filed on 6/2/2026. Claims 1 and 18 are amended. Claims 3 and 19 are cancelled. Claims 1 – 2, 4 – 18 and 20 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 2, 4 – 18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cherian et al (US 20220100545, prior art part of IDS dated 3/6/2025, hereinafter Cherian), in view of Rajani et al (US 20140297941, hereinafter Rajani). As per claim 1, Cherian disclose: A method for configuring a network interface card (NIC) that is connected to a host computer and that emulates a local non-volatile memory express (NVMe) storage device for a set of processes executing on the host computer using a plurality of external storages, the method comprising: configuring, on an operating system (OS) of the NIC: a storage emulator program to present the plurality of external storages to the set of processes as the local NVMe storage device; (Cherian [0033]: “FIG. 1 illustrates one manner of using a smart NIC to emulate a local storage 160 that represents several external storages 140 to one or more virtual machines 112 executing over the operating system (OS) 100 of a host computer… the smart NIC performs storage emulation operations that represent multiple external storages 140 as the local storage 160 to the machines executing on the host computer. The smart NIC connects to PCIe bus 150 of the host.”) and a disk device to exchange NVMe requests and responses between the set of processes and the plurality of external storages by exchanging the NVMe requests and responses (i) with a virtual NVMe (vNVMe) controller of the NIC through the storage stack on the OS, or (ii) directly with the vNVMe controller such that the disk device bypasses the storage stack, wherein exchanging the NVMe requests and responses directly with the vNVMe controller optimizes performance of the NIC. (Cherian [0035]: “The NVMe driver 122 is a driver for the PCIe bus 150. This driver relays NVMe formatted R/W requests from the host hypervisor 114 to the storage processing layers, and relays responses to these requests from the storage processing layers to the host hypervisor 114.”; [0036]: “The smart NIC OS 120 uses the NVMeOF driver 124 in some embodiments to access one or more external storages 140. Specifically, the smart NIC OS 120 emulates a local NVMe storage 160 to represent several external storages 140 to the machines (e.g., VM 112) executing on the host. From the host point of view, the VM 112 operates on the emulated local storage 160 as if it was a local NVMe storage connected through the PCIe bus 150.”; [0082]: “the VFI module 1322 then transfers the NVMeOF packet either directly through the fast path to the NIC driver 1325, or indirectly to the NIC driver 1325 through the slow path that involves the virtual switch 1326. The NIC driver 1325 then forwards the NVMeOF packet through a shared port of the smart NIC, so that this packet can be forwarded through intervening network fabric (e.g., intervening switches/routers) to reach its destination external storage 1340. In some embodiments, the fast-path processing of the VF 1322 allows the VF to directly pass the packet to the shared port of the smart NIC.”.) Cherian did not explicitly disclose: a storage stack including a filesystem switching layer, a virtual volume switching layer, and a storage device switching layer; However, Rajani teaches: a storage stack including a filesystem switching layer, a virtual volume switching layer, and a storage device switching layer; (Rajani [0030]) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Rajani into that of Cherian in order to have a storage stack including a filesystem switching layer, a virtual volume switching layer, and a storage device switching layer. Rajani [0030] has shown that the claimed limitations are merely commonly known and used components for networked storage virtualization, and thus applicants have merely just claimed the combination of known parts in the field to achieve predictable results of virtualized networked storage and is therefore rejected under 35 USC 103. As per claim 2, the combination of Cherian and Rajani further teach: The method of claim 1, wherein the disk device is configured to exchange the NVMe requests and responses with the vNVMe controller through the storage stack or directly as configured by a network administrator. (Cherian [0035], [0036], [0040]) As per claim 4, the combination of Cherian and Rajani further teach: The method of claim 1, wherein the plurality of external storages comprises a set of one or more virtual volume (vVol) storages, and the storage emulator program is configured to present the set of vVol storages as the local NVMe storage device. (Cherian [0095]) As per claim 5, the combination of Cherian and Rajani further teach: The method of claim 4, wherein:the set of vVol storages is a first set of vVol storages, the plurality of external storages further comprises a particular set of one or more external storages that are not native vVol storages, and configuring the storage emulator program to present the plurality of external storages comprises configuring the storage emulator program to convert the particular set of external storages into a second set of vVol storages and to present the first and second sets of vVol storages as the local NVMe storage device. (Cherian [0035], [0036] and [0095]) As per claim 6, the combination of Cherian and Rajani further teach: The method of claim 5, wherein the storage emulator program presents the first and second sets of vVol storages as the local NVMe storage device through a virtual function (VF) of a physical function (PF) of an interface of a bus. (Cherian [0075] – [0077]) As per claim 7, the combination of Cherian and Rajani further teach: The method of claim 6, wherein the PF is a physical interface of the NIC. (Cherian [0074]) As per claim 8, the combination of Cherian and Rajani further teach: The method of claim 7, wherein the VF is a virtualized interface of the physical interface of the NIC. (Cherian [0075]) As per claim 9, the combination of Cherian and Rajani further teach: The method of claim 6, wherein the bus is a peripheral component interconnect express (PCIe) bus. (Cherian [0036]) As per claim 10, the combination of Cherian and Rajani further teach: The method of claim 5, wherein the storage emulator program is configured with a storage conversion application to convert the particular set of external storages into the second set of vVol storages. As per claim 11, the combination of Cherian and Rajani further teach: The method of claim 1, wherein the storage emulator program is implemented as a virtual machine (VM) executing on the NIC. (Cherian [0054]) As per claim 12, the combination of Cherian and Rajani further teach: The method of claim 1, wherein the storage emulator program is implemented as an application executing on the NIC. (Cherian [0035]) As per claim 13, the combination of Cherian and Rajani further teach: The method of claim 1, wherein the storage emulator program comprises a vNVMe interface to connect the storage emulator program to the vNVMe controller of the NIC. (Cherian [0035]) As per claim 14, the combination of Cherian and Rajani further teach: The method of claim 1, wherein the set of processes comprises a set of one or more machines executing on the host computer. (Cherian figure 1) As per claim 15, the combination of Cherian and Rajani further teach: The method of claim 14, wherein the set of machines is a first set of machines executing on the host computer, and a second set of one or more machines executing on the host computer are unaware of the emulated local VVol storage. (Cherian [0035] – [0036]) As per claim 16, the combination of Cherian and Rajani further teach: The method of claim 1, wherein the set of processes comprises a hypervisor executing on the host computer. (Cherian figure 1 and [0033]) As per claim 17, the combination of Cherian and Rajani further teach: The method of claim 1, wherein the set of processes comprises an OS of the host computer. (Cherian figure 1 and [0033]) As per claim 18, it is the non-transitory machine readable medium variant of claim 1 and is therefore rejected under the same rationale. As per claim 20, it is the non-transitory machine readable medium variant of claim 4 and is therefore rejected under the same rationale. Response to Arguments Applicant’s arguments with respect to claim(s) 1-2, 4-18 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M SWIFT whose telephone number is (571)270-7756. The examiner can normally be reached Monday - Friday: 9:30 AM - 7PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Blair can be reached at 5712701014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHARLES M SWIFT/Primary Examiner, Art Unit 2196
Read full office action

Prosecution Timeline

Oct 09, 2023
Application Filed
Feb 02, 2026
Non-Final Rejection mailed — §102, §103
Apr 28, 2026
Interview Requested
May 05, 2026
Examiner Interview Summary
May 05, 2026
Applicant Interview (Telephonic)
Jun 02, 2026
Response Filed
Jul 08, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+21.7%)
3y 0m (~2m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 891 resolved cases by this examiner. Grant probability derived from career allowance rate.

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