DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/10/2026 has been entered.
Claim Rejections - 35 USC § 112 1st
Claims 2-7, 9-17, and 19-23 are rejected under 35 U.S.C. 112, first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. Support for the amendments could not be found in cancelled claims 1, 8, and 19. The Instant Application (IA) does not disclose a limitation, ‘a quantity of the plurality of independent data channels is different than a quantity of the plurality of independent control lines.’ For example, where in the IA discloses that a quantity of data channel is more/less than (e.g. ‘different than’ or ‘not equal to’) quantity of control lines? Also, the IA does not discuss or discloses how these quantity differences effect the disclosed/claimed invention.
Similar problem exists in claims 22 and 23. The IA does not disclose a limitation, “a quantity of the plurality of independent control lines is less than a quantity of the plurality of memory devices, and wherein a quantity of the plurality of independent data channels is less than the quantity of the plurality of memory devices”. Also the IA does not disclose a limitation, “each independent control line of the plurality of independent control lines is associated with a first quantity of memory devices of the plurality of memory devices, and wherein each independent data channel of the plurality of independent data channels is associated with a second quantity of memory devices of the plurality of memory devices.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-7, 10-17, and 19-23 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. Publication 2019/0205225), hereinafter Kim in view of Lee et al. (U.S. Publication 2017/0147230), hereinafter Lee, further in view of common sense/knowledge.
Referring to claim 2, Kim teaches, as claimed, an apparatus, comprising:
a plurality of memory devices (first memory devices, see Paragraph 3; see Fig. 1, 102A and 102B) comprising memory type (SDRAM, see Paragraph 23);
a memory interface (memory controller with a physical layer interface (PHY), see Paragraph 31) circuitry operable to communicate command/address information (command and address information, see Paragraph 30) with the plurality of memory devices;
a circuit (memory interface buffer, see Paragraph 3) operable to communicate data with the plurality of memory devices;
a first parallel bus (see Fig. 1, Channel 0 and 1 are parallel) operably coupling the memory interface circuitry to the plurality of memory devices, the first parallel bus comprising a plurality of independent control lines (“independent of the command and address information”, see Paragraph 38; “The RCD 112 includes logic 150A for controlling channel 0 and logic 150B for controlling channel 1”, see Paragraph 30; and see Fig. 3, RCD 212 A, RCD 212 B, BUS 210A, BUS 210B, and Memory Controller 110); and
a second parallel bus operably coupling the circuit (interface buffer the… see Paragraph 3) to the plurality of memory devices, the second parallel bus comprising a plurality of independent data channels.
Kim does not disclose expressly a FIFO circuit and at least two different memory types, wherein a quantity of the plurality of independent data channels is different than a quantity of the plurality of independent control lines
Lee does disclose a FIFO circuit (FIFO buffer, see Paragraph 38) and at least two different memory types (heterogeneous memories having different hardware properties, see Paragraph 23).
At the time of the invention, it would have been obvious to a person of ordinary skill in the art to incorporate heterogenous memories of Lee into memory system of Kim.
The suggestion/motivation for doing so would have been to take advantage of heterogenous memory system that prevents data loss due to power outage because various type of memories would include non-volatile memories.
Common sense discloses that a quantity of the plurality of independent data channels is different than quantity of the plurality of independent control lines. Because only other option is that two quantities are equal, it is obvious to one of ordinary skilled in the art to experiment with the only other option to see if it would yield better or worst result. Normally, it is well known, data lane width is wider than control lane width because number of different control types do not ever exceed number of different values in data. For instance, standard DIMMs have a 64-bit physical data path (see Kim, Paragraph 2) that could represent 264 different values. In comparison, at most, number of different control signals would be in thousands which at most require 10 to 14 physical lines (e.g. 214 = 16384).
As to claim 3, the modification teaches the apparatus of claim 2, wherein the at least two different memory types comprise a volatile memory type (volatile memory, see Lee Paragraph 25) and a non-volatile memory type (non-volatile, see Lee Paragraph 25).
As to claim 4, the modification teaches the modification teaches the apparatus of claim 2, wherein the at least two different memory types comprise one or more of NAND (NAND, flash memory, a NOR … see Lee Paragraph 25), NOR, phase change memory (PCM), magnetoresistive memory (MRAM), DRAM, SRAM, or ferroelectric memory, or any combination thereof.
As to claim 5, the modification teaches the apparatus of claim 2, wherein the at least one FIFO circuit (FIFO buffer, see Lee Paragraph 38) comprises one or more multiplexers (multiplexer, see Kim Paragraph 61) configured to communicate data between a host device and the plurality of subsets of memory devices via the parallel bus.
As to claim 10, the modification teaches the apparatus of claim 2, wherein the at least one FIFO circuit includes a channel interface configured to communicate with a connected host device using a DDR5 protocol (DDR5, see Kim Paragraph 35).
As to claim 11, the modification teaches the apparatus of claim 2. The modification does not expressly disclose wherein the plurality of subsets of memory devices comprises chip scale packaging memory devices. However, chip scale packaging is well known memory device packaging. One of ordinary skilled in the art would have package the memory chip with known practices due to matter of convenience.
Referring to claim 12, Kim teaches, as claimed, a method, comprising:
receiving a plurality of command/address signals (command and address information, see Paragraph 30) at a memory interface circuitry (memory controller with a physical layer interface (PHY), see Paragraph 31) of an apparatus (see Fig. 1-3, Memory Module 100);
receiving a plurality of data signals at a circuit (memory interface buffer, see Paragraph 3) of the apparatus;
directing, using the memory interface circuitry, the plurality of command/address signals via a plurality of independent control lines (“independent of the command and address information”, see Paragraph 38; “The RCD 112 includes logic 150A for controlling channel 0 and logic 150B for controlling channel 1”, see Paragraph 30; and see Fig. 3, RCD 212 A, RCD 212 B, BUS 210A, BUS 210B, and Memory Controller 110) of a first parallel bus (see Fig. 1, Channel 0 and 1 are parallel) to one or more first memory devices of a plurality of memory devices (first memory devices, see Paragraph 3; see Fig. 1, 102A and 102B) of the apparatus, the plurality of memory devices comprising a memory type (SDRAM, see Paragraph 23),
wherein the plurality of memory devices is operably coupled to the memory interface circuitry via the first parallel bus (see Fig. 1-3; Note, all data channels and date lanes in each channel are parallel as illustrated); and
directing, using the circuit, the plurality of data signals via a plurality of independent data channels of a second parallel bus (interface buffer the… see Paragraph 3) to one or more memory devices of the plurality of memory devices,
wherein the plurality of memory devices is operably coupled to the circuit via the second parallel bus (see Fig. 1-3, Memory Devices 102A and 102B).
Kim does not disclose expressly a FIFO circuit and at least two different memory types, wherein a quantity of the plurality of independent data channels is different than a quantity of the plurality of independent control lines
Lee does disclose a FIFO circuit (FIFO buffer, see Paragraph 38) and at least two different memory types (heterogeneous memories having different hardware properties, see Paragraph 23).
At the time of the invention, it would have been obvious to a person of ordinary skill in the art to incorporate heterogenous memories of Lee into memory system of Kim.
The suggestion/motivation for doing so would have been to take advantage of heterogenous memory system that prevents data loss due to power outage because various type of memories would include non-volatile memories.
Common sense discloses that a quantity of the plurality of independent data channels is different than quantity of the plurality of independent control lines. Because only other option is that two quantities are equal, it is obvious to one of ordinary skilled in the art to experiment with the only other option to see if it would yield better or worst result. Normally, it is well known, data lane width is wider than control lane width because number of different control types do not ever exceed number of different values in data.
For instance, standard DIMMs have a 64-bit physical data path (see Kim, Paragraph 2) that could represent 264 different values. In comparison, at most, number of different control signals would be in thousands which at most require 10 to 14 physical lines (e.g. 214 = 16384).
As to claim 13, the modification teaches the method of claim 12, wherein the at least two different memory types comprise a volatile memory type (volatile memory, see Lee Paragraph 25) and a non-volatile memory type (non-volatile, see Lee Paragraph 25).
As to claim 14, the modification teaches the method of claim 12, wherein directing the plurality of data signals further comprises: directing, using one or more multiplexers (see Kim Fig. 2-3 and 7-10, MUX 280) of the FIFO circuit, the plurality of data signals from a host device to the plurality of subsets of memory devices via the second parallel bus.
As to claim 20, the modification teaches the method of claim 12, wherein the FIFO circuit and the memory interface circuitry are included in a buffering device (buffer, see Kim Paragraph 3) of the apparatus.
As to claim 21, it is directed to a device to implement the method as set forth in claim 12. Therefore, it is rejected on the same basis as set forth hereinabove.
As to claim 22, the modification teaches the apparatus of claim 2.
The modification does not expressly disclose, a quantity of the plurality of independent control lines is less than a quantity of the plurality of memory devices, and wherein a quantity of the plurality of independent data channels is less than the quantity of the plurality of memory devices.
Common sense discloses that a quantity of the plurality of independent control lines is less than a quantity of the plurality of memory devices, and wherein a quantity of the plurality of independent data channels is less than the quantity of the plurality of memory devices. For instance, standard DIMMs have a 64-bit physical data path (see Kim, Paragraph 2) that could represent 264 different values. In comparison, at most, number of different control signals would be in thousands which at most require 10 to 14 physical lines (e.g. 214 = 16384). The physical path of 64 or 14 are fixed. It is well known that number of memory device will need to exceed 14 or 64 (e.g. most likely during the upgrade) with more data to process.
As to claim 23, the modification teaches the apparatus of claim 2.
The modification does not expressly disclose, each independent control line of the plurality of independent control lines is associated with a first quantity of memory devices of the plurality of memory devices, and wherein each independent data channel of the plurality of independent data channels is associated with a second quantity of memory devices of the plurality of memory devices.
Common sense discloses that each independent control line of the plurality of independent control lines is associated with a first quantity of memory devices of the plurality of memory devices, and wherein each independent data channel of the plurality of independent data channels is associated with a second quantity of memory devices of the plurality of memory devices. Because it is well known that each memory devices having their own set control lines is well within one of ordinary skilled in the art to experiment with.
Allowable Subject Matter
Claims 6-7, 9, and 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable:
if rewritten in independent form including all of the limitations of the base claim and any intervening claims; and
if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 1st paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hyun Nam whose telephone number is (571) 270-1725 and fax number is (571) 270-2725. The examiner can normally be reached on Monday through Friday 8:30 AM to 5:00 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HYUN NAM/Primary Examiner, Art Unit 2183
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