DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election without traverse of Invention II (claims 10 – 20) in the reply filed on 16 January 2026 is acknowledged.
Claims 1 - 9 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention I, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 16 January 2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10, 11, and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chudzik et al; (Publication number: US 2005/0266652 A1), hereafter Chudzik.
Regarding claim 10:
Chudzik discloses a method for forming a semiconductor structure (Chudzik ABSTRACT; Figure 3 – 10), comprising:
providing a substrate (Chudzik Figure 3 substrate 12 provided);
forming a first dielectric layer over the substrate (Chudzik [0028] ILD layer 14 formed); removing the dielectric layer (Chudzik [0028] ILD layer removed by reactive ion etching);
forming a first opening through the first dielectric layer (Chudzik Figure 4 vias 16 are formed by removing first dielectric layer);
forming a first electrode in the opening (Chudzik [0029] vias 16 filled with conductor material 18; Figure 4);
forming a dielectric layer on a sidewall surface of the first electrode layer (Chudzik Figure 9 dielectric material 30 deposited on a sidewall of electrode 18; [0035]); and forming a second electrode layer over the substrate (Chudzik Figure 10 – top electrode layer 32 deposited over the substrate 12; [0035]),
wherein the second electrode layer is electrically isolated from the first layer by the dielectric layer (Chudzik Figure 10 – top electrode is separated from electrode 18 by dielectric 30), and the first electrode layer, the dielectric layer, and the second electrode layer are arranged in a direction parallel to a surface of the substrate (Chudzik Figure 11 – see disposition of electrode 18, dielectric 30, and electrode 32 with respect to substrate 12).
Regarding claim 11:
Chudzik discloses the method for forming the semiconductor structure according to claim 10, wherein the dielectric layer is further formed between a bottom surface of the first electrode layer and the substrate (Chudzik Figure 12 dielectric layer 30 formed between bottom surface of electrode layer and substrate when in stacked MIMCAP configuration).
Regarding claim 14:
Chudzik discloses the method for forming the semiconductor structure according to claim 10, wherein the dielectric layer on the sidewall surface of the first electrode layer is formed further above the substrate (Chudzik Figure 9 – dielectric 30 deposited on sidewall of via 16 is formed above substrate 12).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chudzik in view of SHROFF et al; (Publication number: US 2012/0068305 A1), hereafter SHROFF.
Regarding claim 17:
Chudzik does not disclose the method for forming the semiconductor structure according to claim 10, wherein the substrate comprises a first region and a second region and the first electrode layer and the second electrode layer are in the second region and a base (Chudzik Figure 1 4 substrate 12 includes base 10 which can be divided into first region and second region; first electrode 18 and second electrode 20 are in first region and second region).
Chudzik does not disclose the substrate further comprises: a device layer over the base, wherein the device layer includes a device structure; and a first interconnection layer is formed over the device layer, wherein the first interconnection layer over the first region of the substrate includes a first electrical connection structure, the first electrical connection structure is electrically connected to the device structure.
However, SHROFF discloses a lateral capacitor and method of making. More particularly, SHROFF discloses a device layer over the base (SHROFF Figure 1 active device region 14 over substrate 12), wherein the device layer includes a device structure (SHROFF [0027] active device region 14 includes transistors); and
a first interconnection layer is formed over the device layer, wherein the first interconnection layer over the first region of the substrate includes a first electrical connection structure, the first electrical connection structure is electrically connected to the device structure (SHROFF Figure 2 interconnect layer 46 is formed over substrate and active region 14 and includes electrical connection to the active device region 14).
It would have been obvious to modify Chudzik to include: a device layer over the base, wherein the device layer includes a device structure; and a first interconnection layer is formed over the device layer, wherein the first interconnection layer over the first region of the substrate includes a first electrical connection structure, the first electrical connection structure is electrically connected to the device structure, as claimed. Those skilled in the art would appreciate reducing an area required for capacitors without undue process complexity (SHROFF [0005]).
Allowable Subject Matter
Claims 12, 13, 15, 16, 18, 19, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 12:
The prior art discloses the method for forming the semiconductor structure according to claim 11, wherein the second electrode layer is formed after the first electrode layer is formed (Chudzik Figure 5 electrode 20 is formed over electrode 18), and the first electrode layer and the dielectric are formed by performing:
forming a dielectric material layer on a sidewall surface and a bottom surface of the first opening (Chudzik Figure 9 dielectric 30 is formed on sidewall and button of via 16), as well as on a top surface of the first dielectric layer (Chudzik Figure 5 – dielectric 30 extends over substrate 12);
However, the prior art does not further disclose:
forming a first electrode material layer on the dielectric material layer; planarizing the first electrode material layer and the dielectric material layer until the top surface of the first dielectric layer is exposed, thereby forming a dielectric layer in the first opening and the first element layer on the dielectric layer; forming a second opening over the substrate; forming a second electrode material layer in the second opening and on the first electrode layer; and planarizing the second electrode material layer until the surface of the first electrode layer is exposed, thereby forming a second electrode layer.
Regarding claim 13:
The prior art does not disclose the method for forming the semiconductor structure according to claim 11, wherein the first electrode layer is formed after the second electrode layer is formed (Chudzik Figure 5 electrode 20 is formed over electrode 18), and the first electrode layer, the dielectric layer, and the second electrode layer are formed by performing:
forming a dielectric material layer on a sidewall surface and a bottom surface of the first opening (Chudzik Figure 9 dielectric 30 is formed on sidewall and button of via 16), as well as on a top surface of the first dielectric layer (Chudzik Figure 5 – dielectric 30 extends over substrate 12).
However, the prior art does not disclose:
forming a sacrificial material layer on the dielectric material layer; planarizing the sacrificial material layer and the dielectric material layer until the top surface of the first dielectric layer is exposed, thereby forming a dielectric layer in the first opening and a sacrificial layer on the dielectric layer; forming a second opening over the substrate by removing the first dielectric layer after forming the sacrificial layer, the second opening exposing a sidewall surface of the dielectric layer; forming a second electrode material layer in the second opening and on the sacrificial layer; planarizing the second electrode material layer until a surface of sacrificial layer is exposed, thereby forming the second electrode layer; forming a third opening through the dielectric layer by removing the sacrificial layer; forming a first electrode material layer in the third opening and on the second electrode layer; planarizing the first electrode material layer until a surface of the second electrode layer is exposed, thereby forming the first electrode layer.
Regarding claim 15:
The prior art does not disclose the method for forming the semiconductor structure according to claim 14, wherein the second electrode layer is formed after the first electrode layer is formed (Chudzik Figure 5 electrode 20 is formed over electrode 18).
However, the prior art does not disclose: first electrode layer, the dielectric layer, and the second electrode layer are formed by performing:
forming a first electrode material layer in the first opening; planarizing the first electrode material layer until a surface of the first dielectric layer is exposed, thereby forming the first electrode layer in the first opening; forming a second opening over the substrate by removing the first dielectric layer after forming the first electrode layer, the second opening exposing the sidewall surface of the first electrode layer; forming a dielectric material layer on a sidewall surface and a top surface of the first electrode layer, as well as on a bottom surface of the second opening; forming a second electrode material layer on the dielectric material layer; and planarizing the second electrode material layer and the dielectric material layer until a surface of the first electrode layer is exposed, thereby forming the second electrode layer and the dielectric layer.
Regarding claim 16:
The prior art does not disclose the method for forming the semiconductor structure according to claim 14, wherein the first electrode layer is formed after the second electrode layer is formed (Chudzik Figure 5 electrode 20 is formed over electrode 18).
However, the prior art does not disclose: the first electrode layer, the dielectric layer, and the second electrode layer are formed by performing:
forming a sacrificial material layer in the first opening; planarizing the sacrificial material layer until a surface of the first dielectric layer is exposed, thereby forming a sacrificial layer in the first opening; forming a second opening over the substrate by removing the first dielectric layer after forming the sacrificial layer, the second opening exposing a sidewall surface of the sacrificial layer; forming a dielectric material layer on the sidewall surface and a top surface of the sacrificial layer, as well as a bottom surface of the second opening; forming a second electrode material layer on the dielectric material layer; planarizing the second electrode material layer and the dielectric material layer until a surface of the sacrificial layer is exposed, thereby forming the second electrode layer and the dielectric layer; forming a third opening through the dielectric layer by removing the sacrificial layer; forming a first electrode material layer in the third opening and on the second electrode layer; and planarizing the first electrode material layer until a surface of the second electrode layer is exposed, thereby forming the first electrode layer.
Regarding claim 18:
The prior art does not disclose the method for forming the semiconductor structure according to claim 17, further comprising: forming a second interconnection layer, and forming a second electrical connection structure in the second interconnection layer in the first region, wherein the second electrical connection structure is electrically connected to the first electrical connection structure in the first interconnection layer.
Regarding claim 19:
Claim 19 depends on claim 18 and is therefore similarly objected.
Regarding claim 20:
Claim 20 depends on claim 13 and is therefore similarly objected.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIHIR K RAYAN whose telephone number is (571)270-5719. The examiner can normally be reached Monday - Friday 9 - 5pm (EST).
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/MIHIR K RAYAN/ 6 May 2026Primary Examiner, Art Unit 2622
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