DETAILED ACTION This office action is in response to application filed on October 9, 2023. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement s (IDS) submitted on 10/09/2023 and 07/09/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement s are being considered by the examiner. Drawings The drawings are objected to because Figure 3 is not clear . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The disclosure is objected to because of the following informalities: Page 2 , line 26: Language “one refence clock based on the at least one timestamp for the at least one” should read “one refence reference clock based on the at least one timestamp for the at least one” in order to correct for minor informalities. Page 4 , line 15 : Language “refence clock based on the at least one timestamp for the at least one received” should read “ refence reference clock based on the at least one timestamp for the at least one received” in order to correct for minor informalities. Page 6 , line 8 : Language “a reference clock time for each of the at least one refence clock based on the” should read “a reference clock time for each of the at least one refence reference clock based on the” in order to correct for minor informalities. Page 11, line 26: Language “ relative times may include a timing error the protocol time, i.e., the protocol ” should read “ relative times may include a timing error of the protocol time, i.e., the protocol ” in order to correct for minor informalities. Page 1 4 , line 19 : Language “waveform from the physical clock to a refence clock to determine the time” should read “waveform from the physical clock to a refence reference clock to determine the time” in order to correct for minor informalities. Page 1 7 , line 1 : Language “determine a reference clock time for each of the at least one refence clock” should read “determine a reference clock time for each of the at least one refence reference clock” in order to correct for minor informalities. Appropriate correction is required. Claim Objections Claim 2 is objected to because of the following informalities: Claim language “ generating, by a reference clock module on the test system, a timestamp for each of the received at least one signal ” should read “ generating, by a reference clock module on the test system, a timestamp for each of the received at least one received signal ” in order to provide appropriate antecedence basis . Claim language “ determining, by the test system, a reference clock time for each of the at least one refence clock based on the at least one timestamp for the at least one received signal ” should read “ determining, by the test system, a reference clock time for each of the at least one refence reference clock based on the at least one timestamp for the at least one received signal ” in order to correct for minor informalities. Claim language “ correlating, by the test system, the physical clock timing error, the protocol time, and the at least one reference clock time to determine relative times of the physical clock timing error, the protocol time, and the at least one reference clock time ” should read “ correlating, by the test system, the physical clock timing error, the protocol time, and the at least one reference clock time to determine the relative times of the physical clock timing error, the protocol time, and the at least one reference clock time ” in order to provide appropriate antecedence basis. Claim language “ displaying, by the graphical user interface, a graphical representation of the relative times of the physical clock timing error, the protocol time, and the at least one reference time ” should read “ displaying, by the graphical user interface, [[ a ]] the graphical representation of the relative times of the physical clock timing error, the protocol time, and the at least one reference clock time ” in order to provide appropriate antecedence basis. Appropriate correction is required. Claim 3 is objected to because of the following informalities: Claim language should read “ The method of claim 2, wherein the graphical representation includes [[ a ]] the graphical representation comparing one of the at least one relative reference time to [[ the ]] other relative times ” in order to provide appropriate antecedence basis. Appropriate correction is required. Claim 4 is objected to because of the following informalities: Claim language should read “ The method of claim 2 comprising receiving, by the test system and from the DUT, the at least one signal indicating [[ a ]] the time generated by the at least one reference clock ” in order to provide appropriate antecedence basis. Appropriate correction is required. Claim 5 is objected to because of the following informalities: Claim language should read “ The method of claim 2 comprising receiving, by the test system and from at least one time reference source, the at least one signal indicating [[ a ]] the time generated by the at least one reference clock ” in order to provide appropriate antecedence basis. Appropriate correction is required. Claim 7 is objected to because of the following informalities: Claim language “ displaying, by the graphical user interface, a graphical representation comparing a relative reference time of the selected reference time to the other relative times ” should read “ displaying, by the graphical user interface, [[ a ]] the graphical representation comparing a relative reference time of the selected one of the at least one reference time clock to [[ the ]] other relative times ” in order to provide appropriate antecedence basis. Appropriate correction is required. Claim 9 is objected to because of the following informalities: Claim language should read “ The method of claim 8 wherein displaying the physical clock timing error and the protocol timing error includes displaying [[ the ]] timing errors as time varying waveforms on an interface designed to mimic an oscilloscope display ” in order to provide appropriate antecedence basis. Appropriate correction is required. Claim 11 is objected to because of the following informalities: Claim language “ The system of claim 11 wherein the test system is configured for: ” should read “ The system of claim [[ 11 ]] 10 wherein the test system is configured for: ” in order to provide appropriate dependency . Claim language “ generating, by a reference clock module on the test system, a timestamp for each of the received at least one signal ” should read “ generating, by a reference clock module on the test system, a timestamp for each of the received at least one received signal ” in order to provide appropriate antecedence basis . Claim language “ determining a reference clock time for each of the at least one refence clock based on the at least one timestamp for the at least one received signal ” should read “ determining a reference clock time for each of the at least one refence reference clock based on the at least one timestamp for the at least one received signal ” in order to provide appropriate antecedence basis. Claim language “ correlating the physical clock timing error, the protocol time, and the at least one reference clock time to determine relative times of the physical clock timing error, the protocol time, and the at least one reference clock time ” should read “ correlating the physical clock timing error, the protocol time, and the at least one reference clock time to determine the relative times of the physical clock timing error, the protocol time, and the at least one reference clock time ” in order to provide appropriate antecedence basis. Claim language “ displaying, by the graphical user interface, a graphical representation of the relative times of the physical clock timing error, the protocol time, and the at least one reference time ” should read “ displaying, by the graphical user interface, [[ a ]] the graphical representation of the relative times of the physical clock timing error, the protocol time, and the at least one reference clock time ” in order to provide appropriate antecedence basis. Appropriate correction is required. Claim 1 2 is objected to because of the following informalities: Claim language should read “ The system of claim [[ 12 ]] 11 , wherein the graphical representation includes [[ a ]] the graphical representation comparing one of the at least one relative reference time to [[ the ]] other relative times ” in order to provide appropriate dependency and antecedence basis . Appropriate correction is required. Claim 1 3 is objected to because of the following informalities: Claim language should read “ The system of claim 12 wherein the test system is configured for receiving, from the DUT, the at least one signal indicating [[ a ]] the time generated by the at least one reference clock ” in order to provide appropriate antecedence basis. Appropriate correction is required. Claim 1 4 is objected to because of the following informalities: Claim language should read “ The system of claim 12 wherein the test system is configured for receiving, from at least one time reference source, the at least one signal indicating [[ a ]] the time generated by the at least one reference clock ” in order to provide appropriate antecedence basis. Appropriate correction is required. Claim 1 5 is objected to because of the following informalities: Claim language should read “ The system of claim [[ 15 ]] 14 wherein the at least one time reference source includes a first time reference source implementing a Global Navigation Satellite System (GNSS) ” in order to provide appropriate dependency. Appropriate correction is required. Claim 1 6 is objected to because of the following informalities: Claim language “ displaying, on the graphical user interface, a graphical representation comparing a relative reference time of the selected reference time to the other relative times ” should read “ displaying, on the graphical user interface, [[ a ]] the graphical representation comparing a relative reference time of the selected one of the at least one reference time clock to [[ the ]] other relative times ” in order to provide appropriate antecedence basis . Appropriate correction is required. Claim 1 8 is objected to because of the following informalities: Claim language should read “ The system of claim 17 wherein displaying the physical clock timing error and the protocol timing error includes displaying [[ the ]] timing errors as time varying waveforms on an interface designed to mimic an oscilloscope display ” in order to provide appropriate antecedence basis. Appropriate correction is required. Claim 20 is objected to because of the following informalities: Claim language “ Receiving at least one signal indicating a time generated by at least one reference clock ” should read “ Receiving r eceiving at least one signal indicating a time generated by at least one reference clock ” in order to correct for minor informalities . Claim language “ generating a timestamp for each of the received at least one signal ” should read “ generating a timestamp for each of the received at least one received signal ” in order to provide appropriate antecedence basis. Claim language “ determining a reference clock time for each of the at least one refence clock based on the at least one timestamp for the at least one received signal ” should read “ determining a reference clock time for each of the at least one refence reference clock based on the at least one timestamp for the at least one received signal ” in order to provide appropriate antecedence basis . Claim language “ correlating the physical clock timing error, the protocol time, and the at least one reference clock time to determine relative times of the physical clock timing error, the protocol time, and the at least one reference clock time ” should read “ correlating the physical clock timing error, the protocol time, and the at least one reference clock time to determine relative times of the physical clock timing error, the protocol time, and the at least one reference clock time ” in order to provide appropriate antecedence basis. Claim language “ displaying a graphical representation of the relative times of the physical clock timing error, the protocol time, and the at least one reference time ” should read “ displaying [[ a ]] the graphical representation of the relative times of the physical clock timing error, the protocol time, and the at least one reference clock time ” in order to provide appropriate antecedence basis. Appropriate correction is required. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claim s 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception without significantly more. Regarding claim 1, the examiner submits that under Step 1 of the 2024 Guidance Update on Patent Subject Matter Eligibility, Including on Artificial Intelligence (see also 2019 Revised Patent Subject Matter Eligibility Guidance ) for evaluating claims for eligibility under 35 U.S.C. 101, the claim is to a process, which is one of the statutory categories of invention. Continuing with the analysis, under Step 2A - Prong One of the test (see italic text for abstract idea) : the limitation “ detecting , at a physical clock analyzer module on a test system, an edge transition of a physical layer waveform from a physical clock on a device under test (DUT) ” is a process that, under its broadest reasonable interpretation in light of the specification, covers performance of the limitation using mental processes to detect an event ( i.e., an edge transition ; see specification at p. 11, lines 17-19 ). Except for the recitation of the extra-solution activities (e.g., source/type of data being evaluated ), the particular technological environment or field of use, and the generic computer elements (i.e., a physical clock analyzer module on a test system ; see specification at p. 9, lines 17-28 ), the limitation in the context of the claim mainly refers to performing a mental evaluation to detect an edge transition o f a signal . the limitation “ generating , by the physical clock analyzer module, a timestamp for the detected edge transition ” is a process that, under its broadest reasonable interpretation in light of the specification, covers performance of the limitation using mental processes to record time information of an event ( i.e., a timestamp for the detected edge transition ; see specification at p. 1 2 , lines 16 -19 ). Except for the recitation of the extra-solution activities (e.g., source/type of data being evaluated), the particular technological environment or field of use, and the generic computer elements (i.e., the physical clock analyzer module ; see specification at p. 9, lines 17-28 ), the limitation in the context of the claim mainly refers to performing a mental evaluation to record the time of an edge transition of a signal . the limitation “ determining , by the physical clock analyzer module, a physical clock timing error based on the timestamp for the detected edge transition ” is a process that, under its broadest reasonable interpretation in light of the specification, covers performance of the limitation using mental processes and/or mathematical concepts to manipulate data and obtain a result (i.e., a physical clock timing error ; see specification at p. 11, line 27 – p. 13, line 4 ). Except for the recitation of the extra-solution activities (e.g., source/type of data being evaluated), the particular technological environment or field of use, and the generic computer elements (i.e., the physical clock analyzer module ; see specification at p. 9, lines 17-28 ), the limitation in the context of the claim mainly refers to performing a mental evaluation and/or applying mathematical concepts to manipulate data and obtain a result. the limitation “ exchanging, between the test system and the DUT, timing protocol messages, wherein the test system generates timestamps when transmitting or receiving the timing protocol messages and receives timestamp information from the DUT ” is a process that, under its broadest reasonable interpretation in light of the specification, covers performance of the limitation using mental processes to record time information of event s (i.e., timestamps when transmitting or receiving the timing protocol messages and receives timestamp information from the DUT ; see specification at p. 8 , line 12 – p. 9 , line 4 ; p. 10, lines 3-30 ). Except for the recitation of the extra-solution activities (e.g., source/type of data being evaluated), the particular technological environment or field of use, and the generic computer elements and computer implementation (i.e., the test system , transmission of data, reception of data ; see specification at p. 9, lines 17-28 ), the limitation in the context of the claim mainly refers to performing a mental evaluation to record the time during transmission and reception of messages . the limitation “ determining , by a timing protocol analyzer module on the test system, a protocol time based on the generated timestamps and the received timestamp information ” is a process that, under its broadest reasonable interpretation in light of the specification, covers performance of the limitation using mental processes and/or mathematical concepts to manipulate data and obtain a dditional information (i.e., a protocol time ; see specification at p. 9, lines 4-16; p. 10, line 30 – p. 11, line 16 ). Except for the recitation of the extra-solution activities (e.g., source/type of data being evaluated), the particular technological environment or field of use, and the generic computer elements (i.e., a timing protocol analyzer module on the test system ; see specification at p. 9, lines 17-28 ), the limitation in the context of the claim mainly refers to performing a mental evaluation and/or applying mathematical concepts to manipulate data and obtain a result. the limitation “ correlating , by the test system, the physical clock timing error and the protocol time to determine relative times of the physical clock timing error and the protocol time ” is a process that, under its broadest reasonable interpretation in light of the specification, covers performance of the limitation using mental processes and/or mathematical concepts to compare data to determine additional information (i.e., relative times ; see specification at p. 13, line 21 – p. 14, line 9 ). Except for the recitation of the extra-solution activities (e.g., source/type of data being evaluated), the particular technological environment or field of use, and the generic computer elements (i.e., the test system ; see specification at p. 9, lines 17-28 ), the limitation in the context of the claim mainly refers to performing a mental evaluation and/or applying mathematical concepts to compare data and obtain a result. Therefore, the claim recites a judicial exception under Step 2A - Prong One of the test . Furthermore, under Step 2A - Prong Two of the test, this judicial exception is not integrated into a practical application when considering the claim as a whole . In particular, the additional elements recited in the claim (see non-italic text for additional elements): “ A method for correlating and displaying physical layer and application layer timing information ” generally links the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)) ; “ detecting , at a physical clock analyzer module on a test system, an edge transition of a physical layer waveform from a physical clock on a device under test (DUT) ” adds generic computer elements (i.e., a physical clock analyzer module on a test system ; see specification at p. 9, lines 17-28) (see MPEP 2106.05(f)) while appending extra-solution activities (e.g., source/type of data being evaluated ) (see MPEP 2106.05( g )) ; “ exchanging, between the test system and the DUT, timing protocol messages, wherein the test system generates timestamps when transmitting or receiving the timing protocol messages and receives timestamp information from the DUT ” adds computer implementation (e.g., exchanging, transmitting, receiving data ) using elements recited at a high level of generality (i.e., the test system and the DUT ; see specification at p. 9, lines 17-28 ) (see MPEP 2106.05( f )) ; and “ displaying, by a graphical user interface on the test system, a graphical representation of the relative times of the physical clock timing error and the protocol time ” adds extra-solution activities (e.g., mere data outputting) (see MPEP 2106.05(g)) while using generic computer elements (i.e., a graphical user interface on the test system ; see specification at p. 9, lines 17-28 ) (see MPEP 2106.05( f )) . Accordingly, these additional elements, when considered individually and in combination, do not integrate the judicial exception into a practical application because they do not impose any meaningful limits on practicing the abstract idea when considering the claim as a whole. The claim is directed to a judicial exception under Step 2A of the test . Additionally, under Step 2B of the test, the claim, when considered as a whole, does not include additional elements that, when considered individually and in combination, are sufficient to amount to significantly more than the judicial exception because the additional elements : generally link the use of the judicial exception to a particular technological environment or field of use ( e.g., correlating time information ), which as indicated in the MPEP: “As explained by the Supreme Court, a claim directed to a judicial exception cannot be made eligible “simply by having the applicant acquiesce to limiting the reach of the patent for the formula to a particular technological use.” Diamond v. Diehr, 450 U.S. 175, 192 n.14, 209 USPQ 1, 10 n. 14 (1981). Thus, limitations that amount to merely indicating a field of use or technological environment in which to apply a judicial exception do not amount to significantly more than the exception itself, and cannot integrate a judicial exception into a practical application” (see MPEP 2106.05(h)) ; recite extra-solution activities (i.e., mere data gathering /outputting by selecting a particular data source/type to be manipulated) using computer elements specified at a high level of generality (i.e., test system, DUT, physical clock analyzer module, timing protocol analyzer module, graphical user interface) , which as indicated in the MPEP : “Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more in Step 2B is whether the additional elements add more than insignificant extra-solution activity to the judicial exception. The term “extra-solution activity” can be understood as activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim. Extra-solution activity includes both pre-solution and post-solution activity. An example of pre-solution activity is a step of gathering data for use in a claimed process , e.g., a step of obtaining information about credit card transactions, which is recited as part of a claimed process of analyzing and manipulating the gathered information by a series of steps in order to detect whether the transactions were fraudulent. An example of post-solution activity is an element that is not integrated into the claim as a whole, e.g., a printer that is used to output a report of fraudulent transactions, which is recited in a claim to a computer programmed to analyze and manipulate information about credit card transactions in order to detect whether the transactions were fraudulent ” (see MPEP 2106.05(g)) and “Use of a machine that contributes only nominally or insignificantly to the execution of the claimed method (e.g., in a data gathering step or in a field-of-use limitation) would not provide significantly more” (see MPEP 2106.05(b) , section III) ; and append generic computer components (i.e., test system, DUT, physical clock analyzer module, timing protocol analyzer module, graphical user interface ) used to facilitate the application of the abstract idea (i.e., mere computer implementation) , which as indicated in the MPEP: “Use of a computer or other machinery in its ordinary capacity for economic or other tasks ( e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea ( e.g., a fundamental economic practice or mathematical equation) does not provide significantly more” (see MPEP 2106.05(f), item 2) , The claim, when considered as a whole, does not provide significantly more under Step 2B of the test. Based on the analysis, the claim is not patent eligible . Similarly, independent claims 10 and 1 9 are directed to a judicial exception (abstract idea) without significantly more as explained above with regards to claim 1 . With regards to the dependent claims they are also directed to the non-statutory subject matter because : they just extend the abstract idea of the independent claims by additional limitations (Claims 2-3, 11-12 and 20 ), that under the broadest reasonable interpretation in light of the specification, cover performance of the limitations using mental processes and/or mathematical concepts, and the additional elements recited in the dependent claims, when considered individually and in combination , refer to extra-solution activities (e.g., mere data gathering /outputting using a data type or source), generic computer components and/or field of use (Claims 2- 9, 11-18 and 20 ), which as indicated in the Office’s guidance does not integrate the judicial exception into a practical application ( Step 2A – Prong Two ) and/or does not provide significantly more ( Step 2B ) when considering the claimed invention as a whole . Subject Matter Not Rejected Over Prior Art Claims 1-20 are distinguished over the prior art of record for the following reasons: Regarding claim 1. IP.com ( Clock Quality Analyzer with Falling Edge Support, IP com, Pub Id IPCOM000271874D (March 2023) , IDS reference ) discloses/teaches : A method (p. 1, section ‘Abstract’: a clock quality analyzer receives a clock signal and determines clock performance metrics such as time interval error (TIE) ) , the method comprising : detecting, at a physical clock analyzer module on a test system, an edge transition of a physical layer waveform from a physical clock on a device under test (DUT) (p. 1-2: a clock quality analyzer detects edge transition of a clock signal from a DUT ) ; generating, by the physical clock analyzer module, a timestamp for the detected edge transition (p. 1-2: the edge transition is timestamped (see Table 1) ) ; and determining, by the physical clock analyzer module, a physical clock timing error based on the timestamp for the detected edge transition (p. 4, section “Prior Solution Deficiencies”: time interval error (physical clock timing error) is determined based on timestamp vs. expected signal period ). Fonseca ( Fonseca, R., “ Time Travels: a Closer Look at PTP, ” Artel White Paper, June 2018 , IDS reference) discloses/teaches : A method (p. 1, section “PTP – Why it’s necessary”: Precision Timing Protocol synchronizes devices to a single shared clock ), the method comprising: exchanging, between the test system and the DUT, timing protocol messages, wherein the test system generates timestamps when transmitting or receiving the timing protocol messages and receives timestamp information from the DUT (p. 1-2, section “PTP Message Flow”: protocol messages are exchanged between master device and slave device, with these messages including timing information (see Fig. 1) ) ; and determining, by a timing protocol analyzer module on the test system, a protocol time based on the generated timestamps and the received timestamp information (p. 1-2, section “PTP Message Flow”: timing information is used to determine delay and offset in order to synchronize clocks ) . Mirabito ( US 11349633 B1 ) discloses: “ Techniques described herein may be used for determining an offset between clocks in a network. Such techniques may include obtaining, by a passive time device, a first timestamp pair corresponding to a first time protocol message; obtaining, by the passive time device, a second timestamp pair corresponding to a second time protocol message; and calculating, by the passive time device, a clock offset between a time protocol master and the passive time device using the first timestamp pair, the second timestamp pair, and a pre-determined time delay constant corresponding to a network tap ” (Abstract: time protocol messages are obtained by a passive time device in order to calculate a clock offset between a time protocol master and the passive time device ). The closest prior art of record, taken individually or in combination, fail to teach or suggest: “ A method for correlating and displaying physical layer and application layer timing information, the method comprising: correlating, by the test system, the physical clock timing error and the protocol time to determine relative times of the physical clock timing error and the protocol time; and displaying, by a graphical user interface on the test system, a graphical representation of the relative times of the physical clock timing error and the protocol time ” ( the examiner submits that the prior art of record discloses synchronization of time protocol messages as well as determining clock timing errors based on edge transition, however, the cited references do not correlate a physical clock timing error based on a timestamp for a detected edge transition and a protocol time to determine relative times ) in combination with all other limitations within the claim, as claimed and defined by the applicant. Regarding claim 10. IP.com (Clock Quality Analyzer with Falling Edge Support, IP com, Pub Id IPCOM000271874D (March 2023), IDS reference) discloses/teaches: A system, the system comprising a test system , the test system comprising : a physical clock analyzer module (p. 1, section ‘Abstract’: a clock quality analyzer receives a clock signal and determines clock performance metrics such as time interval error (TIE) ) configured for : detecting an edge transition of a physical layer waveform from a physical clock on the DUT (p. 1-2: a clock quality analyzer detects edge transition of a clock signal from a DUT ) ; generating a timestamp for the detected edge transition (p. 1-2: the edge transition is timestamped (see Table 1) ) ; and determining a physical clock timing error based on the timestamp for the detected edge transition (p. 4, section “Prior Solution Deficiencies”: time interval error (physical clock timing error) is determined based on timestamp vs. expected signal period ). Fonseca (Fonseca, R., “Time Travels: a Closer Look at PTP,” Artel White Paper, June 2018, IDS reference) discloses /teaches : A system (p. 1, section “PTP – Why it’s necessary”: Precision Timing Protocol synchronizes devices to a single shared clock ), the system comprising : a test system configured for exchanging, with a device under test (DUT), timing protocol messages, wherein the test system generates timestamps when transmitting or receiving the timing protocol messages and receives timestamp information from the DUT (p. 1-2, section “PTP Message Flow”: protocol messages are exchanged between master device and slave device, with these messages including timing information (see Fig. 1) ) , the test system comprising: a timing protocol analyzer module configured for: determining a protocol time based on the generated timestamps and the received timestamp information (p. 1-2, section “PTP Message Flow”: timing information is used to determine delay and offset in order to synchronize clocks ). Mirabito (US 11349633 B1) discloses: “Techniques described herein may be used for determining an offset between clocks in a network. Such techniques may include obtaining, by a passive time device, a first timestamp pair corresponding to a first time protocol message; obtaining, by the passive time device, a second timestamp pair corresponding to a second time protocol message; and calculating, by the passive time device, a clock offset between a time protocol master and the passive time device using the first timestamp pair, the second timestamp pair, and a pre-determined time delay constant corresponding to a network tap” (Abstract: time protocol messages are obtained by a passive time device in order to calculate a clock offset between a time protocol master and the passive time device ). The closest prior art of record, taken individually or in combination, fail to teach or suggest: “ A system for correlating and displaying physical layer and application layer timing information, the system comprising: a graphical user interface configured for displaying a graphical representation of relative times of the physical clock timing error and the protocol time; wherein the test system is configured for correlating the physical clock timing error and the protocol time and determining the relative times of the physical clock timing error and the protocol time ” ( the examiner submits that the prior art of record discloses synchronization of time protocol messages as well as determining clock timing errors based on edge transition, however, the cited references do not correlate a physical clock timing error based on a timestamp for a detected edge transition and a protocol time to determine relative times ) in combination with all other limitations within the claim, as claimed and defined by the applicant. Regarding claim 19. IP.com (Clock Quality Analyzer with Falling Edge Support, IP com, Pub Id IPCOM000271874D (March 2023), IDS reference) discloses/teaches: A non-transitory computer readable medium having stored thereon executable instructions that when executed by at least one processor of at least one computer cause the at least one computer to perform steps (p. 1, section ‘Abstract’: a clock quality analyzer receives a clock signal and determines clock performance metrics such as time interval error (TIE) ; examiner interprets clock quality analyzer to be a computer system including memory and processing capabilities to perform the analysis ) comprising : detecting an edge transition of a physical layer waveform from a physical clock on a device under test (DUT) (p. 1-2: a clock quality analyzer detects edge transition of a clock signal from a DUT ) ; generating a timestamp for the detected edge transition (p. 1-2: the edge transition is timestamped (see Table 1) ) ; and determining a physical clock timing error based on the timestamp for the detected edge transition (p. 4, section “Prior Solution Deficiencies”: time interval error (physical clock timing error) is determined based on timestamp vs. expected signal period ). Fonseca (Fonseca, R., “Time Travels: a Closer Look at PTP,” Artel White Paper, June 2018, IDS reference) discloses/teaches: exchanging, with the DUT, timing protocol messages, wherein the test system generates timestamps when transmitting or receiving the timing protocol messages and receives timestamp information from the DUT (p. 1-2, section “PTP Message Flow”: protocol messages are exchanged between master device and slave device, with these messages including timing information (see Fig. 1) ) ; and determining a protocol time based on the generated timestamps and the received timestamp information (p. 1-2, section “PTP Message Flow”: timing information is used to determine delay and offset in order to synchronize clocks ). Mirabito (US 11349633 B1) discloses: “Techniques described herein may be used for determining an offset between clocks in a network. Such techniques may include obtaining, by a passive time device, a first timestamp pair corresponding to a first time protocol message; obtaining, by the passive time device, a second timestamp pair corresponding to a second time protocol message; and calculating, by the passive time device, a clock offset between a time protocol master and the passive time device using the first timestamp pair, the second timestamp pair, and a pre-determined time delay constant corresponding to a network tap” (Abstract: time protocol messages are obtained by a passive time device in order to calculate a clock offset between a time protocol master and the passive time device ). The closest prior art of record, taken individually or in combination, fail to teach or suggest: “ correlating the physical clock timing error and the protocol time to determine relative times of the physical clock timing error and the protocol time; and displaying a graphical representation of the relative times of the physical clock timing error and the protocol time ” ( the examiner submits that the prior art of record discloses synchronization of time protocol messages as well as determining clock timing errors based on edge transition, however, the cited references do not correlate a physical clock timing error based on a timestamp for a detected edge transition and a protocol time to determine relative times ) in combination with all other limitations within the claim, as claimed and defined by the applicant. Regarding claim s 2 -9, 11-18 and 20 . The y are also distinguished over the prior art of record due to their dependency . Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Magee; Anthony et al. , US 20140149526 A1 , Latency Monitoring Function Reference discloses calculating latency between master node and slave node based on timestamp information exchanged during time alignment protocol. Hadzic, Ilija et al. , US 20040062278 A1 , Systems and methods for synchronization in asynchronous transport networks Reference discloses clock frequency synchronization in network time protocol methods. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT LINA CORDERO whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-9969 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 9:30 am - 6:00 pm . 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