CTFR 18/378,186 CTFR 79873 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claims 1, 11, and 20, the claims recite reordering, by the one or more processors based on the timestamp, one or more packets of the plurality of packets in the respective timeslot , for example see claim 1, lines 7 and 8. However, the preceding limitation recites “allocating . . . each of the plurality of packets to respective timeslots in the packet reorder data structure.” The claim limitation is interpreted as each packet is allocated to a respective timeslot; thereby, each timeslot comprises a single packet. Therefore, “reordering . . . one or more packets of the plurality of packets in the respective timeslot” is inconsistent with the preceding claim limitation as each “respective timeslot” comprises merely a single packet, which does not require reordering. The claim does not set forth the conditions under which reordering is performed or triggered to be performed because the claim does not mention any out-of-order or out-of-sequence packets based on a particular timestamp but merely a reordering. So, the manner in which reordering is performed according to the amended claim limitation is unclear form the context of the claim. Reordering would only occur if a “respective timeslot” comprised a “plurality of packets” which were out-of-order based upon timestamps. However, the claim as amended recites each packet is allocated to a timeslot, such that a “respective timeslot” would not comprise out-of-order packets but merely “a” packet. For the purposes of this examiner the Examiner interprets the claim as reordering, based on the timestamp, one or more packets of the plurality of packets. The claim should be amended to either more explicitly recite the manner in which the plurality of packets are allocated to timeslots and the manner/conditions for reordering the plurality of packets in a timeslot when the timeslot comprises a plurality of packets. Appropriate clarification and correction is required. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-3, 5-13, and 15-20 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Browne et al. (US 2019/0155645 A1), hereinafter referred to as D1 . Regarding claims 1, 11, and 20, D1 discloses distribution of network traffic to processor cores, which comprises: receiving, by one or more processors at a packet reorder data structure, a plurality of packets wherein each of the plurality of packets includes a timestamp corresponding to a time a respective packet was received at an ingress port of a network (Referring to Figures 1-3 and 6, receiving packets by a processor. For a received packet of type UDP and traffic class real-time, interface divider 206 applies divider policy 1 whereby received packets of type UDP and traffic class real-time are allocated to one of 10 timeslot queues. Interface divider 206 checks a current timestamp of a received packet of type UDP (timestamp corresponding to a time a respective packet was received at an ingress port of a network) and traffic class real-time and maps the received packet to a timeslot queue associated with the current timestamp. See paragraphs 0026-0028.) ; allocating, by the one or more processors based on the timestamp, each of the plurality of packets to respective timeslots in the packet reorder data structure (Referring to Figures 1-3 and 6, Interface divider 206 checks a current timestamp of a received packet of type UDP (timestamp corresponding to a time a respective packet was received at an ingress port of a network) and traffic class real-time and maps the received packet to a timeslot queue associated with the current timestamp. See paragraphs 0026-0028.) ; and reordering, by the one or more processors based on the timestamp, one or more packets of the plurality of packets in the respective timeslot (See 112 rejection above for the Examiner’s claim interpretation. Referring to Figures 1-3 and 6, timeslot scheduler 402 can attempt to maintain receive packet order or reorder packets into an output timeslot queue (after out-of-order processing) using the timeslot number of the packet to maintain order. Because groups of packets are tagged that arrive with the timeslot they arrive in, an order of received packets, relative to each other, can be maintained. Timeslot scheduler 402 can attempt to prevent received packets from going out-of-order because all packets in an input timeslot stay together when mapped and scheduled to transmit timeslots and output ports. In a case of state-less packet processing (e.g., packets have no shared context, flow, or connection, or such characteristics can be ignored (e.g., UDP)), packets are ordered for a destination queue or transmission using standard re-ordering methods (e.g., arrival timestamp based re-ordering or arrival sequence number based reordering). See paragraphs 0033-0035 and 0042-0044.) Regarding claims 2 and 12, D1 discloses dynamically adjusting, by the one or more processors, a duration of the timeslots (Referring to Figures 1-3 and 6, if one or more cores are determined to be overloaded or packet processing latency is excessive, a timeslot size can be adjusted to be smaller. The number of input timeslot queues can be increased for a smaller timeslot size. Conversely, if one or more cores are determined to be underutilized and packet processing latency is acceptable, a timeslot size can be adjusted to be larger. A number of input timeslot queues (and cores) can be decreased for a larger timeslot size. In addition, a number of cores can be decreased so that cores can process more packets from each input timeslot queue. See paragraphs 0021-0026.) Regarding claims 3 and 13, D1 discloses wherein the dynamic adjustment occurs based on at least one of a fixed time interval, a volume of packet traffic, a sample interval, or a maximum network delay (Referring to Figures 1-3 and 6, if one or more cores are determined to be overloaded or packet processing latency is excessive (volume and maximum network delay), a timeslot size can be adjusted to be smaller. The number of input timeslot queues can be increased for a smaller timeslot size. Conversely, if one or more cores are determined to be underutilized and packet processing latency is acceptable, a timeslot size can be adjusted to be larger. A number of input timeslot queues (and cores) can be decreased for a larger timeslot size. In addition, a number of cores can be decreased so that cores can process more packets from each input timeslot queue. See paragraphs 0021-0026.) Regarding claims 5 and 15, D1 discloses comparing, by the one or more processors, a timestamp of a packet of the plurality of packets to a time interval of the respective timeslot; and allocating, by the one or more processors based on the comparison, the packet to a respective timeslot, wherein the respective timeslot includes a time corresponding to the timestamp of the packet (Referring to Figures 1-3 and 6, receiving packets by a processor. For a received packet of type UDP and traffic class real-time, interface divider 206 applies divider policy 1 whereby received packets of type UDP and traffic class real-time are allocated to one of 10 timeslot queues. Interface divider 206 checks a current timestamp of a received packet of type UDP (timestamp corresponding to a time a respective packet was received at an ingress port of a network) and traffic class real-time and maps the received packet to a timeslot queue associated with the current timestamp. See paragraphs 0026-0028.) Regarding claim 6, D1 discloses appending, by the one or more processors, a respective timestamp to the plurality of packets (Referring to Figures 1-3 and 6, a timeslot is selected for the one or more received packets based on the timeslot policy. A timeslot can be assigned to a received packet based on based on the received packet's timestamp. A packet descriptor or meta-data can be formed that identifies an addressable region in memory that stores the one or more received packets and identifies a timeslot of a received packet (appending a respective timestamp to the one or more packets). The one or more packets can be stored in a region of memory (e.g., queue) associated with a timeslot. At 610, the received packets allocated to a timeslot are processed by one or more cores associated with the timeslot. The one or more cores can process contents of packets (e.g., header or payload) in the region of memory associated with the timeslot. Processed contents of one or more received packets can be stored in a region of memory. Processing of received packets can include one or more of: metering, marking, encryption, decryption, compression, decompression, packet inspection, denial of service protection, rate limiting, scheduling based on priority, traffic shaping, or packet filtering based on IP filter rules. See paragraphs 0053-0055.) Regarding claims 7 and 16, D1 discloses encapsulating, by the one or more processors, a respective packet, or tacking, by the one or more processors, the respective timestamp to an end of the respective packet such that the bytes in the packet are not rearranged (Referring to Figures 1-3 and 6, a timeslot is selected for the one or more received packets based on the timeslot policy. A timeslot can be assigned to a received packet based on based on the received packet's timestamp. A packet descriptor or meta-data can be formed that identifies an addressable region in memory that stores the one or more received packets and identifies a timeslot of a received packet (encapsulating). The one or more packets can be stored in a region of memory (e.g., queue) associated with a timeslot. At 610, the received packets allocated to a timeslot are processed by one or more cores associated with the timeslot. The one or more cores can process contents of packets (e.g., header or payload) in the region of memory associated with the timeslot. Processed contents of one or more received packets can be stored in a region of memory. Processing of received packets can include one or more of: metering, marking, encryption, decryption, compression, decompression, packet inspection, denial of service protection, rate limiting, scheduling based on priority, traffic shaping, or packet filtering based on IP filter rules. See paragraphs 0053-0055.) Regarding claims 8 and 17, D1 discloses wherein appending the respective timestamp to the plurality of packets occurs at a switch in the network (Referring to Figures 1-3 and 6, performed by the cores (switch in the network), a timeslot is selected for the one or more received packets based on the timeslot policy. A timeslot can be assigned to a received packet based on based on the received packet's timestamp. A packet descriptor or meta-data can be formed that identifies an addressable region in memory that stores the one or more received packets and identifies a timeslot of a received packet (appending). The one or more packets can be stored in a region of memory (e.g., queue) associated with a timeslot. At 610, the received packets allocated to a timeslot are processed by one or more cores associated with the timeslot. The one or more cores can process contents of packets (e.g., header or payload) in the region of memory associated with the timeslot. Processed contents of one or more received packets can be stored in a region of memory. Processing of received packets can include one or more of: metering, marking, encryption, decryption, compression, decompression, packet inspection, denial of service protection, rate limiting, scheduling based on priority, traffic shaping, or packet filtering based on IP filter rules. See paragraphs 0053-0055.) Regarding claims 9 and 18, D1 discloses wherein when receiving the plurality of packets, the method further comprises identifying, by the one or more processors, the timestamp for a respective packet of the plurality of packets (Referring to Figures 1-3 and 6, receiving packets by a processor. For a received packet of type UDP and traffic class real-time, interface divider 206 applies divider policy 1 whereby received packets of type UDP and traffic class real-time are allocated to one of 10 timeslot queues. Interface divider 206 checks a current timestamp of a received packet of type UDP (identifying, by the one or more processors, the timestamp for respective packet of the one or more packets) and traffic class real-time and maps the received packet to a timeslot queue associated with the current timestamp. See paragraphs 0026-0028.) Regarding claims 10 and 19, D1 discloses wherein the timestamp corresponds to a time a client network transmitting the plurality of packets loses control of the plurality of packets to a receiving network (Referring to Figures 1-3 and 6, receiving packets by a processor. For a received packet of type UDP and traffic class real-time, interface divider 206 applies divider policy 1 whereby received packets of type UDP and traffic class real-time are allocated to one of 10 timeslot queues. Interface divider 206 checks a current timestamp of a received packet of type UDP (interpreted as corresponding to a time a client network transmitting the one or more packets loses control of the one or more packets to a receiving network) and traffic class real-time and maps the received packet to a timeslot queue associated with the current timestamp. See paragraphs 0026-0028.) Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over D1 in view of Lee et al. (US 2023/0246946 A1), hereinafter referred to as D2 . Regarding claims 4 and 14, D1 further teaches dynamically increasing the duration of the timeslots or dynamically decreasing the duration of the timeslots (Referring to Figures 1-3 and 6, if one or more cores are determined to be overloaded or packet processing latency is excessive (volume and maximum network delay), a timeslot size can be adjusted to be smaller (dynamically decreasing the duration of the timeslots). The number of input timeslot queues can be increased for a smaller timeslot size. Conversely, if one or more cores are determined to be underutilized and packet processing latency is acceptable, a timeslot size can be adjusted to be larger (dynamically increasing the duration of the timeslots). A number of input timeslot queues (and cores) can be decreased for a larger timeslot size. In addition, a number of cores can be decreased so that cores can process more packets from each input timeslot queue. See paragraphs 0021-0026.) D1 does not disclose determining, by the one or more processors, a number of packets received out of order; comparing, by the one or more processors, the number of packets received out of order to a threshold number of packets; and when the number of packets received out of order exceeds/below the threshold number of packets perform an adjustment. D2 teaches the multicast flow analyzer 119 may determine that at TO of the content out-of-order RTP packet count is 0; at T1 out-of-order RTP packet count is 1; and at T2 out-of-order RTP packet count is 2. For example, the multicast flow analyzer 119 may determine that any out-of-order RTP packet count in the multicast of content over 0 or another out-of-order RTP packet count threshold signifies a quality issue related to out-of-order RTP packet count for the multicast of the content (determining a number of packets received out of order and comparing the packets received out of order to a threshold number of packets). For example, the multicast flow analyzer 119 may determine that a trending increase in out-of-order RTP packet count over two or more of the time samples signifies a quality issue related to out-of-order RTP packet count for the multicast of the content. The multicast flow analyzer 119 may store data associated with the quality issue in the quality analysis database 115. For example, the data may include the type of quality issue (e.g., out-of-order RTP packet count), the values of out-of-order RTP packet count determined, and/or the time or time period of the samples evaluated from the multicast of the content that were determined to identify the quality issue. For multicasts of content where quality issues are identified, the multicast flow analyzer 119 may cause the receipt of the multicast of the content by the user devices 130a-c to change from the current content source 102 to a different content source (when the number of packets received out of order exceeds/below the threshold perform an adjustment). For example, the multicast flow analyzer 119 may evaluate timing data associated with one or more user devices 130a-c receiving the multicast of the content to determine if the particular user device 130a-c was receiving the multicast of the content during the time or time period during which the quality issue was identified in the multicast of the content. See paragraphs 0047-0050. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to implement the well-known technique of a responsive technique due to out of order packets exceeding a threshold of D2 in the well-known system of timeslot adjustment of D1. One of ordinary skill in the art before the effective filing date of the invention would have been motivated to implement the well-known technique of D2, counting out of order packets and performing an adjustment based on the out of order packets exceeding a threshold, in the well-known system of time-slot adjustment of D1. In so doing, the well-known system of D1 would be responsive to out of order packets, as opposed to merely packet delay, as taught by D2; thereby, improving system processing for out of order UDP packets despite best efforts to maintain order according to time slots . Response to Arguments Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection was necessitated by the amendment to the claims. Further, the manner in which the amendment raises 112 specific issues and the manner in which the claim interpretation is affected in light of the amendment is addressed in the 112 rejection. The prior art rejection is maintained in light of the Examiner’s claim interpretation and further guidance for overcoming the rejection is recited above. Furthermore, regarding claim 1, the Applicant argues that D1 does not disclose reordering, by the one or more processors based on the time stamp. The Examiner respectfully disagrees. D1 discloses utilizing timestamps as part of the reordering process and, as such, is “based” on timestamps. In addition, the claim limitation “respective timeslot” presents a series of 112 issues addressed in the rejection above. The claim should be amended for clarification and to overcome the newly necessitated amendment. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zhu et al. (US 2022/0116334 A1) - packet reordering techniques for inter-radio access technology (RAT) and intra-RAT traffic steering. The multi-queue management and packet reordering techniques may be used in Multi-Access Management Services (MAMS) framework, which is a programmable framework that provides mechanisms for the flexible selection of network paths in a multi-access (MX) communication environment, based on an application's needs. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD L MILLS whose telephone number is (571)272-3094. The examiner can normally be reached Monday through Friday from 9-5 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yemane Mesfin can be reached at 571-272-3927. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. DONALD L. MILLS Primary Examiner Art Unit 2462 /Donald L Mills/ Primary Examiner, Art Unit 2462 Application/Control Number: 18/378,186 Page 2 Art Unit: 2462 Application/Control Number: 18/378,186 Page 3 Art Unit: 2462 Application/Control Number: 18/378,186 Page 4 Art Unit: 2462 Application/Control Number: 18/378,186 Page 5 Art Unit: 2462 Application/Control Number: 18/378,186 Page 6 Art Unit: 2462 Application/Control Number: 18/378,186 Page 7 Art Unit: 2462 Application/Control Number: 18/378,186 Page 8 Art Unit: 2462 Application/Control Number: 18/378,186 Page 9 Art Unit: 2462 Application/Control Number: 18/378,186 Page 10 Art Unit: 2462 Application/Control Number: 18/378,186 Page 11 Art Unit: 2462 Application/Control Number: 18/378,186 Page 12 Art Unit: 2462 Application/Control Number: 18/378,186 Page 13 Art Unit: 2462
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