Prosecution Insights
Last updated: October 25, 2026
Application No. 18/378,615

System and Methods Involving Features of Hardware Virtualization, Hypervisors, APIs of Interest and/or Other Features

Final Rejection §103§112
Filed
Oct 10, 2023
Priority
May 15, 2014 — provisional 61/993,291 +13 more
Examiner
CHOY, KA SHAN
Art Unit
2435
Tech Center
2400 — Computer Networks
Assignee
Lynx Software Technologies
OA Round
4 (Final)
93%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
256 granted / 275 resolved
+35.1% vs TC avg
Moderate +10% lift
Without
With
+10.0%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
7 currently pending
Career history
288
Total Applications
across all art units

Statute-Specific Performance

§101
8.4%
-31.6% vs TC avg
§103
44.5%
+4.5% vs TC avg
§102
17.0%
-23.0% vs TC avg
§112
19.6%
-20.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 275 resolved cases

Office Action

§103 §112
DETAILED ACTION This office action is in response to the correspondence filed on 07/15/2026. This application is a continuation or CIP of various applications that have provisional applications with earliest filing date of 05/15/2014. Claims 6, 20, 25-26, 30-40, 43, and 60-68 are pending and are examined. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Applicant's claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Response to Arguments The amendments and/or arguments submitted by Applicants for the objection(s)/rejection(s)) listed below have been considered and are persuasive; thus, they have been withdrawn: Claim Objection(s) 35 U.S.C. §112 Rejection(s) Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim 68 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claim 68, this claim is essentially previously presented claim 60 with a broaden breadth of the claim limitations. To comply with the written description requirement of 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, or to be entitled to an earlier priority date or filing date under 35 U.S.C. 119, 120, or 365(c), each claim limitation must be expressly, implicitly, or inherently supported in the originally filed disclosure. Per MPEP § 2163.05, a claim that omits an element which applicant describes as an essential or critical feature of the invention originally disclosed does not comply with the written description requirement. A claim which omits matter disclosed to be essential to the invention as described in the specification or in other statements of record may be subject to rejection under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as not enabling, or under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976); In re Venezia, 530 F.2d 956, 189 USPQ 149 (CCPA 1976); and In re Collier, 397 F.2d 1003, 158 USPQ 266 (CCPA 1968). See also MPEP § 2172.01. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 68 is rejected under 35 U.S.C. 103 as being unpatentable over Day et al. (US Pub No. “Hardware Virtualization puts a new spin on secure System” per IDS submitted on 02/25/2022, referred to as Day), in view of Osiseket al. (US Patent No. 5,555,385, referred to as Osiseket), further in view of Dalal et al. (US Patent No. US 9792431 B1, referred to as Dalal). Regarding claim 68, Day discloses, 68 (new) A method for processing information securely, the method comprising: partitioning hardware platform resources via a separation kernel hypervisor into a plurality of guest operating system virtual machine protection domains; (See Day, page 3; leveraging Multicore Processors; Software virtualization can be used across single-core processors, but when running larger desktop operating system that are used to having full control of a processor, multicore parts that often also have hardware virtualization support are the best way to maintain near-native performance of all of the secure domains. See also fig 1; separation kernel technology) isolating the domains in time and/or space from each other; (See Day, page 1-2; separation kernel technology and fig 1: the separate kernel a technology that provides an underlying real-time platform with multiple secure domains housing software applications that cannot interfere with each other) Day does not explicitly disclose, however Osiseket teaches, sharing a list of memory locations of an authorized guest to another guest; (Osiseket: P. 22; Summary of the Invention; a virtual machine computer system which permits more than one guest/virtual machine to share a single address space (memory locations) and each control access by its applications to the shared address space. The computer system comprises a host operating system for creating first (authorized guest) and second (another guest) virtual machine guests.) hosting a mechanism to control access to …from the another guest; and hosting a mechanism to control access to specified locations and/or pages from the another guest. (Osiseket: P. 22; Summary of the Invention; the first guest responds to a request from a first application executing in the first guest to allocate an address space, by determining at least in part a storage region for the address space. The first guest also responds to a request from the first application to grant shared access by a second application executing in the second guest to the address space, by notifying the host operating system that the second guest or the second application is authorized to access the address space (a mechanism to control access).) It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to implement the teachings of Osiseket into the teachings of Day with a motivation to provide an address space allocation process within a virtual machine environment which permits more than one guest/virtual machine to share a single address space and each central access by its applications to the shared address space by using a request mechanism between two guests (Osiseket: Coln. 2, l. 66 - Coln. 3, l. 3). The combination of Day and Osiseket does not explicitly disclose; however, Dalal teaches, …application programming interfaces (Dalal: Coln. 5; ls. 36-39; access to the virtual storage configuration of a virtual machine through an Application Programming Interface (API).) processing an attempted access of an application programming interface by detecting the attempted access via a detection mechanism. (Dalal: Coln. 5; ls. 49-64; interception module 106 may be running as a process of computing device 202 with an elevated privilege level, equal to or greater than the virtual machine, and thereby have the ability to intercept read operations directed to the physical storage device containing the file representing the virtual storage device. Interception module 106 (detection mechanism) may use the virtual storage configuration obtained in step 302 to determine (detecting) whether the virtual machine process is attempting to read data on a virtual storage device containing protected data. In one embodiment, the process executing outside the virtual machine is a module of a hypervisor that provides the ability to intercept attempts to read data from the virtual storage device via an API.) It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to implement the teachings of Dalal into the combination of Day and Osiseket with a motivation to protect data from being accessed by those who are not authorized to access it by detecting unauthorized data access in virtual storage devices (Dalal abstract and Coln. 1, ls. 7-21). Allowable Subject Matter Claims 6, 20, 25-26, 30-40, 43, and 60-67 are allowed. The following is an examiner’s statement of reasons for allowance: prior art rejections are already resolved in a previous office action. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. CORRIE; Benjamin J. US-PGPUB US 20130160011 A1 Hibernate mechanism for virtualized java virtual machines Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KA SHAN CHOY whose telephone number is (571) 272-1569. The examiner can normally be reached on MON - FRI: 9AM-5:30PM EST Alternate Fridays. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Mehrmanesh can be reached at (571) 270-3351. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KA SHAN CHOY/Primary Examiner, Art Unit 2435
Read full office action

Prosecution Timeline

Show 2 earlier events
May 21, 2025
Response Filed
Jun 04, 2025
Final Rejection mailed — §103, §112
Dec 04, 2025
Request for Continued Examination
Dec 18, 2025
Response after Non-Final Action
Jan 07, 2026
Examiner Interview (Telephonic)
Jan 15, 2026
Non-Final Rejection mailed — §103, §112
Jul 15, 2026
Response Filed
Sep 11, 2026
Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12764540
SYSTEM AND METHOD FOR CLASSIFYING INCOMING EVENTS BY USER'S MOBILE DEVICE BASED ON USER PREFERENCES
2y 5m to grant Granted Oct 13, 2026
Patent 12744803
MULTI-LAYER ANOMALY DETECTOR
2y 10m to grant Granted Sep 22, 2026
Patent 12726497
METHOD, PRODUCT, AND SYSTEM FOR AUTOMATICALLY ISOLATING MALICIOUS SECURITY ALERTS FROM BENIGN ALERTS USING AN ENSEMBLE MODEL OF PATTERN RECOGNITION TECHNIQUES
2y 9m to grant Granted Sep 01, 2026
Patent 12724923
METHODS, SYSTEMS, ARTICLES OF MANUFACTURE AND APPARATUS TO PRIVATIZE CONSUMER DATA
1y 11m to grant Granted Sep 01, 2026
Patent 12719900
SYSTEM AND METHOD FOR DETECTING ANOMALIES IN A CYBER-PHYSICAL SYSTEM IN REAL TIME
2y 5m to grant Granted Aug 25, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

5-6
Expected OA Rounds
93%
Grant Probability
99%
With Interview (+10.0%)
2y 2m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 275 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month