DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 21-22, 25 and 28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shih et al. (US 20200006159 A1, hereinafter Shih’159)
Regarding independent claim 1, Shih’159 teaches, “A semiconductor device (fig. 1-11; ¶ [0001] - ¶ [0064]), comprising:
a substrate (202, 204) having a first region (210A) and a second region (210B);
a first oxide layer disposed on the first region (210A), wherein the first oxide layer comprises a first thermal oxide layer (222, silicon oxide, ¶ [0027]) and a first deposited oxide layer (224, silicon oxide, ¶ [0028]);
a first high-k material layer (224, ¶ [0028] describes, ‘The gate dielectric layer 224 may include silicon oxide (SiO2), silicon oxynitride (SiON), aluminum silicon oxide (AlSiO), a high-k dielectric material such as hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), other suitable metal-oxides, or combinations thereof) disposed on the first deposited oxide layer (224);
a first gate material layer (226, 228) disposed on the first high-k material layer (224);
a first spacer (224 or 212) surrounding the first gate material layer (226, 228) and disposed on the first deposited oxide layer (224);
a second oxide layer disposed on the second region (210B), wherein the second oxide layer comprises a second thermal oxide layer (222, silicon oxide, ¶ [0027]) and a second deposited oxide layer (224, silicon oxide, ¶ [0028]);
a second high-k material layer (224, ¶ [0028] describes, ‘The gate dielectric layer 224 may include silicon oxide (SiO2), silicon oxynitride (SiON), aluminum silicon oxide (AlSiO), a high-k dielectric material such as hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), other suitable metal-oxides, or combinations thereof) disposed on the second deposited oxide layer (224); and
a second gate material layer (226, 228) disposed on the second high-k material layer (224)”.
The limitataion “on” above is explained using broadest reasonable interpretation. “ON” is a directional phrase, meaning an object can be above or below or left or right of another object with or without other objects in between. Also, the object can be in direct contact with or near or next to or adjacent to or covering the another object.
The limitations, ‘thermal oxide’, ‘deposited oxide’, are directed towards the process of making an oxide by thermal process, an oxide by deposition process and a thermal oxide layer formed by a pad oxide layer respectively. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language "thermal oxide", ‘deposited oxide’, only requires an oxide layer in the claimed semiconductor device, which does not distinguish the invention from Shih’159, who teaches the structure as claimed.
Regarding claim 2, Shih’159 further teaches, “The semiconductor device of claim 1, wherein the first thermal oxide layer, the first deposited oxide layer, the second thermal oxide layer, and the second deposited oxide layer comprise a same material (silicon oxide)”.
Regarding claim 3, Shih’159 further teaches, “The semiconductor device of claim 1, wherein the first high-k material layer and the second high-k material layer (224, ¶ [0028]) each comprise hafnium oxide, hafnium silicon oxide, or hafnium silicon oxynitride”.
Regarding claim 4, Shih’159 further teaches, “The semiconductor device of claim 1, further comprising: a second spacer (224 in region 210B) surrounding the second gate material layer (226, 228) and disposed on the second deposited oxide layer (224)”.
Regarding claim 5, Shih’159 further teaches, “The semiconductor device of claim 4, wherein an outer side surface of the first spacer (224 in region 210A) is aligned with a side surface of the first oxide layer (222, 224), and an outer side surface of the second spacer (224 in region 210B) is aligned with a side surface of the second oxide layer (222, 224)”.
Regarding claim 6, Shih’159 further teaches, “The semiconductor device of claim 1, wherein a thickness of the first deposited oxide layer (224 in region 210A, silicon oxide, ¶ [0028]) is equal to a thickness of the second deposited oxide layer (224 in region 210B, silicon oxide, ¶ [0028])”.
Regarding claim 21, Shih’159 further teaches, “The semiconductor device of claim 1, wherein the first spacer (212) directly contacts a side surface of the first high-k material layer (224)”.
Regarding claim 22, Shih’159 further teaches, “The semiconductor device of claim 4, further comprising: a third spacer (212) surrounding the first spacer (224) and the first oxide layer (222, 224), wherein the third spacer (212) directly contacts a top surface of the substrate (202, 204) in the first region (210A); and a fourth spacer (212) surrounding the second spacer and the second oxide layer, wherein the fourth spacer directly contacts a top surface of the substrate in the second region (210B)”.
Regarding claim 25, Shih’159 further teaches, “The semiconductor device of claim 1, wherein the first gate material layer and the second gate material layer (226, 228) each comprise a metallic conductive material (¶ [0029])”.
Regarding claim 28, Shih’159 further teaches, “The semiconductor device of claim 4, wherein the first spacer and the second spacer (224 or 212, ¶ [0027], ¶ [0031]) each independently comprise silicon dioxide, silicon nitride, silicon oxynitride, or silicon carbonitride”.
Claims 1, 7-10 and 29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 20190157421 A1, hereinafter Wang’421).
Regarding independent claim 1, Wang’421 teaches, “A semiconductor device (fig. 1-10; ¶ [0012] - ¶ [0030]), comprising:
a substrate (110, fig. 10) having a first region (B) and a second region (A);
a first oxide layer (120b) disposed on the first region, wherein the first oxide layer comprises a first thermal oxide layer (lower part of 120b, 120bl) and a first deposited oxide layer (upper part of 120b, 120bu);
a first high-k material layer (122b) disposed on the first deposited oxide layer (120bu);
a first gate material layer (M2) disposed on the first high-k material layer (122b);
a first spacer (142b, 152b) surrounding the first gate material layer (M2) and disposed on the first deposited oxide layer (120bu);
a second oxide layer (120a) disposed on the second region, wherein the second oxide layer comprises a second thermal oxide layer (lower part of 120a, 120al) and a second deposited oxide layer (upper part of 120a, 120au);
a second high-k material layer (122a) disposed on the second deposited oxide layer (120au); and
a second gate material layer (M1) disposed on the second high-k material layer (120au)”.
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The limitataion “on” above is explained using broadest reasonable interpretation. “ON” is a directional phrase, meaning an object can be above or below or left or right of another object with or without other objects in between. Also, the object can be in direct contact with or near or next to or adjacent to or covering the another object.
The limitations, ‘thermal oxide’, ‘deposited oxide’, are directed towards the process of making an oxide by thermal process, an oxide by deposition process and a thermal oxide layer formed by a pad oxide layer respectively. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language "thermal oxide", ‘deposited oxide’, only requires an oxide layer in the claimed semiconductor device, which does not distinguish the invention from Wang’421, who teaches the structure as claimed.
Regarding claim 7, Wang’421 further teaches, “The semiconductor device of claim 1, wherein a thickness of the first oxide layer (120b) is greater than a thickness of the second oxide layer (120a)”.
Regarding claim 8, Wang’421 further teaches, “The semiconductor device of claim 1, wherein a thickness of the first oxide layer (120b) is greater than a thickness of the second thermal oxide layer (120al)”.
Regarding claim 9, Wang’421 further teaches, “The semiconductor device of claim 1, wherein in the first oxide layer, a thickness of the first thermal oxide layer is greater than a thickness of the first deposited oxide layer (the dividing line between the first thermal oxide layer and the first deposited oxide layer can be adjusted accordingly)”.
Regarding claim 10, Wang’421 further teaches, “The semiconductor device of claim 1, wherein in the second oxide layer, a thickness of the second thermal oxide layer is greater than a thickness of the second deposited oxide layer (the dividing line between the second thermal oxide layer and the second deposited oxide layer can be adjusted accordingly)”.
Regarding claim 29, Wang’421 further teaches, “The semiconductor device of claim 8, wherein a ratio of a thickness of the first thermal oxide layer to a thickness of the second thermal oxide layer is 1.3 to 1.4 (the first thermal oxide layer and the second thermal oxide layer can be defined accordingly)”.
Claims 1, 8 and 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (US 20220376071 A1, hereinafter Tsai’071).
Regarding independent claim 1, Tsai’071 teaches, “A semiconductor device (fig. 1-11; ¶ [0001] - ¶ [0042]), comprising:
a substrate (10, fig. 11) having a first region (R1) and a second region (R2);
a first oxide layer (22) disposed on the first region (R1), wherein the first oxide layer comprises a first thermal oxide layer (22) and a first deposited oxide layer (22);
a first high-k material layer (70) disposed on the first deposited oxide layer (22);
a first gate material layer (MG1) disposed on the first high-k material layer (70);
a first spacer (S1) surrounding the first gate material layer (MG1) and disposed on the first deposited oxide layer (22);
a second oxide layer (24) disposed on the second region (R2), wherein the second oxide layer (24) comprises a second thermal oxide layer (24) and a second deposited oxide layer (24);
a second high-k material layer (70) disposed on the second deposited oxide layer (24); and
a second gate material layer (MG2) disposed on the second high-k material layer (70)”.
The limitataion “on” above is explained using broadest reasonable interpretation. “ON” is a directional phrase, meaning an object can be above or below or left or right of another object with or without other objects in between. Also, the object can be in direct contact with or near or next to or adjacent to or covering the another object.
The limitations, ‘thermal oxide’, ‘deposited oxide’, are directed towards the process of making an oxide by thermal process, an oxide by deposition process and a thermal oxide layer formed by a pad oxide layer respectively. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language "thermal oxide", ‘deposited oxide’, only requires an oxide layer in the claimed semiconductor device, which does not distinguish the invention from Tsai’071, who teaches the structure as claimed.
Regarding claim 8, Tsai’071 further teaches, “The semiconductor device of claim 1, wherein a thickness of the first oxide layer (22) is greater than a thickness of the second thermal oxide layer (24)”.
Regarding claim 27, Tsai’071 further teaches, “The semiconductor device of claim 8, wherein a top surface of the first oxide layer (22) is higher than a top surface of the second oxide layer (24)”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 24 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Wang’421.
Regarding claim 24, “The semiconductor device of claim 1, wherein an operation voltage sustained by a device disposed in the first region is greater than an operation voltage sustained by a device disposed in the second region”, this limitation describes how the claimed device to be operated/employed. Prior art Wang’421 teaches all the elements of the claimed device and the subject limitation does not make the claimed structure different from the one described in the prior art. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP § 2114.II.
Regarding claim 30, “The semiconductor device of claim 7, wherein a ratio of a thickness of the first oxide layer to a thickness of the second oxide layer is 1.20 to 1.28”, Wang’421 teaches a thickness of the first oxide layer (t2, fig. 1) is larger than a thickness of the second oxide layer (t1). While the cited prior art does not explicitly disclose the particular claimed value, the teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization. The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Wang’421 as applied to claim 1 and further in view of Ikeda (US 20080064156 A1, hereinafter Ikeda’156).
Regarding claim 23, Wang’421 teaches all the limitations described in claim 1.
But Wang’421 is silent upon the provision of wherein the semiconductor device of claim 1, further comprising: a first well region in the first region of the substrate; a second well region in the second region of the substrate; two first light doped drains located at two opposite sides of the first well region; and two second light doped drains located at two opposite sides of the second well region.
However, Ikeda’156 teaches a semiconductor device of claim 1, further comprising: a first well region (11, fig. 44) in the first region of the substrate; a second well region (21) in the second region of the substrate; two first light doped drains (15) located at two opposite sides of the first well region; and two second light doped drains (25) located at two opposite sides of the second well region”.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Wang’421 and Ikeda’156. to include LDD regions according to the teachings of Ikeda’156 with a motivation of reducing junction leakage as described by Ikeda’156, ¶ [0181], ¶ [0212].
Note: Claim 23 can also be rejected by Su; Kuan-Wei et al. (US 20200006152 A1).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Wang’421 as applied to claim 1 and further in view of Li (US 20200388614 A1, hereinafter Li’614).
Regarding claim 26, Wang’421 teaches all the limitations described in claim 1.
But Wang’421 is silent upon the provision of wherein the semiconductor device of claim 1, further comprising: an insulating structure disposed in the substrate between the first region and the second region, wherein a top surface of the insulating structure is higher than a top surface of the substrate in the first region and higher than a top surface of the substrate in the second region.
However, Li’614 teaches a similar device (fig. 5) comprising: an insulating structure (108) disposed in the substrate (102) between the first region (110A) and the second region (110B), wherein a top surface of the insulating structure (108) is higher than a top surface of the substrate (102) in the first region (110A) and higher than a top surface of the substrate (102) in the second region (110B).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Wang’421 and Li’614 to form the insulating structure according to the teachings of Li’614 with a motivation of reducing gate-induced drain leakage (GIDL) and hot carrier effect. See Li’614., ¶ [0004].
Response to Arguments
Applicant's arguments filed 07/30/2026 have been fully considered but they are not persuasive.
Applicant argues:
[Page 10-11] of REMARKS,
Wang fails to disclose the features of "the first oxide layer comprises a first thermal oxide layer and a first deposited oxide layer" and "a first spacer disposed on the first deposited oxide layer" of amended Claim 1. Also, in FIG. 10 of Wang, there is no element corresponding to the second deposited oxide layer of the present application. Accordingly, Wang fails to disclose the features of "the second oxide layer comprises a second thermal oxide layer and a second deposited oxide layer" of amended Claim 1.
Examiner’s reply:
The applicant is being requested here to see the rejections above using Wang including the element mapping.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266. The examiner can normally be reached 9AM-7PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
