DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-16 are pending in this application. Claims 1, 4-5, 11-14, and 16 are amended.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/12/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
Claims 1, 12-14, and 16 are amended to address the claim objections of the previous office action dated 10/21/25. The objections are therefore withdrawn. The specification was amended to address an objection for the error in par 51, and is therefore withdrawn. The claims were amended to address the antecedent specification objections regarding “first stack”, “second stack”, “third stack”, “fourth stack”, however confusion is still present as to which transistors now make up ““first circuit”, “second circuit”, “third circuit”, “fourth circuit”, and “first amplification stage”. The amendment to claim 11 appears to overcome the “first amplification stage” objection, but the specification fails to disclose which transistors are the eleventh and twelfth transistors as claimed. New objections are introduced below.
Response to Arguments
Applicant's arguments filed 01/20/26 have been fully considered but they are not persuasive. On page 8 and 9 of Remarks of 01/20/26, applicant argues, that Qaiyum (US 2015/0309088) in combination with Luzzi (US 2011/0001555) fail to teach the claim limitation, "wherein the fourth transistor is of a same type as the second transistor."
Examiner respectfully disagrees. In the instant application par [11] “the first, second, third, and fourth transistors are MOS transistors”. As stated in the previous office action specification objection, it is unclear from the specification which transistors make up first stack, second stack, etc. Examiner interprets the second transistor of the instant application to be TM6 and the fourth transistor to be TM12. Both are mos transistors. Examiner submits that Qaiyum does not explicitly disclose the fourth transistor (fig 1B, PMOS transistor 127) is of a same type as the second transistor (bipolar junction BJT 1X). Examiner relies on Luzzi to teach the fourth transistor is of a same type as the second transistor and provides motivation to combine references Qaiyum and Luzzi. Luzzi discloses a fourth transistor (fig 3A, PMOS transistor M8) is of a same type as the second transistor (fig 1, PMOS transistor M6, both transistors are PMOS transistors). Therefore Luzzi does teach the claim limitation “wherein the fourth transistor is of a same type as the second transistor”.
On page 10 of remarks, regarding claim 13, applicant further argues, “’wherein the second circuit is a replica of the first circuit’, but neither the disclosure of Qaiyum nor the disclosure of Luzzi expressly teaches such a replica identity”.
Examiner respectfully disagrees. The instant application par [53] describes the replica transistors “a MOS transistor TM11 (e.g., a replica of transistor TM5), for example, with a P channel, having its source coupled, preferably connected, to the source of power supply voltage Vcc, and having its gate receiving voltage pbias; a MOS transistor TM12 (e.g., a replica of transistor TM6), for example, with a P channel, having its source coupled, preferably connected, to the drain of MOS transistor TM11, and having its gate receiving the voltage Vc_TB3 at the collector of bipolar transistor TB3”. Examiner submits that Qaiyum does not disclose wherein the second stack of transistors is a replica of the first stack of transistors. Examiner relies on Luzzi to teach “the second stack of transistors is a replica of the first stack of transistors” and provides motivation to combine references Qaiyum and Luzzi. Luzzi’s second stack of transistors (fig 3A, PMOS transistors M7 and M8) is a replica of the first stack of transistors (fig 1, PMOS transistors M5 and M6). Luzzi’s second stack M7/M8 (replica of M5/M6) having its source coupled to the source of power supply voltage Vdd and having its gate receiving voltage pbias. Luzzi’s M8 having its source coupled to the drain of MOS transistor M7, and having its gate receiving the voltage pcasc_bias. Therefore Luzzi does teach the claim limitation “’wherein the second circuit is a replica of the first circuit”.
Drawings
The drawings were received on 10/12/2023.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the
“first circuit” of claim 1
“second circuit” of claim 1
“third circuit” of claim 5
“fourth circuit” of claim 5
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Claim 1 line 5 “first circuit” – specification mentions first stack but does not disclose what the first stack comprises of nor does it point to which first and second transistor make up the “first stack”.
Claim 1 line 10 “second circuit” – specification mentions second stack but does not disclose what the second stack comprises of nor does it point to which third and fourth transistor make up the “second stack”.
Claim 5 line 2 “third circuit” – specification mentions third stack but does not disclose what the third stack comprises of nor does it point to which seventh and eighth transistor make up the “third stack”.
Claim 5 line 7 “fourth circuit” – specification mentions fourth stack but does not disclose what the fourth stack comprises of nor does it point to which ninth and tenth transistor make up the “fourth stack”.
Claim 11 line 5 “first amplification stage” – specification discloses first amplification stage comprises transistors TB3, TB4, TM3, TM4, TM5, TM6, and TM7 but does not point to which transistors are the eleventh and twelfth transistors.
Appropriate correction is required.
Claim Objections
Claim 13 objected to because of the following informalities:
Claim 13 line 4 “the circuit” should be replaced with “the start check circuit”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 12-13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Qaiyum et al. (US 20150309088 A1) hereinafter Qaiyum and further in view of Luzzi et al. (US 20110001555 A1) hereinafter Luzzi.
Regarding claim 1, Qaiyum discloses an electronic circuit (fig 1B, BGR startup verification circuit 100, BGR circuit 160, and startup circuit not shown; par [0016] “A startup circuit for the BGR circuit 160 is not shown in FIGS. 1A or 1B, but can generally comprise any startup circuit, which can be optionally be included on the same chip with the BGR circuit 160 and the startup verification circuit 100.”), comprising: a reference voltage circuit (fig 1B, BGR Circuit 160 and current mirror 110); and a start check circuit (fig 1B, Startup verification circuit 100) configured to check starting operation of the reference voltage circuit (abstract “circuitry for processing these outputs to determine whether the BGR circuit has properly started”); wherein the reference voltage circuit comprises: a first circuit comprising a first transistor (fig 1B, top PMOS transistor in circuit 160) and a second transistor (fig 1B, bottom bipolar junction BJT 1X transistor in circuit 160), wherein the first transistor comprises a first control terminal (fig 1B, top PMOS transistor gate) configured to receive a first control signal (fig 1B, En_BG), and wherein the second transistor comprises a second control terminal (fig 1B, bipolar junction BJT 1X base) configured to receive a second control signal (fig 1B, VSS); wherein the start check circuit configured to check starting operation comprises: at least one first elementary test circuit (fig 1B, first verification sub-circuit 120) including a second stack of a third transistor (fig 1B, PMOS transistor 126) and a fourth transistor (fig 1B, PMOS transistor 127) configured to deliver a first binary signal (fig 1B, OK1), wherein the third transistor is of a same type as the first transistor (both PMOS transistors) and comprises a third control terminal (fig 1B, 126 PMOS transistor gate) configured to receive the first control signal (fig 1B, EN_OK1), and comprises a fourth control terminal (fig 1B, 127 PMOS transistor gate) configured to receive the second control signal (fig 1B, EN_OK1).
Qaiyum does not explicitly disclose the fourth transistor (fig 1B, PMOS transistor 127) is of a same type as the second transistor (bipolar junction BJT 1X). Qaiyum discloses in par [0015] “The BGR circuit 160 shown in FIG. 1B is a continuous time BG circuit having a self-biased amplifier 161 and Delta-VBE-over-R bias circuit 162 shown including a PNP-bipolar current mirror. However, disclosed embodiments are generally applicable to any type of BGR circuit, such as a classical Widlar Bandgap Voltage Reference, a CMOS Bandgap Reference using PNP Lateral bipolar junction transistors (BJTs), a CMOS Bandgap Reference using substrate PNP BJTs, a weak inversion Bandgap Voltage Reference, and a Brokaw reference circuit.” The instant application’s reference voltage circuit closely resembles a Brokaw reference circuit. The indication that Qaiyum’s BGR circuit 160 could be of a different type of bandgap voltage reference circuit allows one of ordinary skill in the art to recognize that substituting or adding additional components, in this case, implementing a PMOS transistor in series with the top PMOS transistor of circuit 160 as the second transistor of the transistor stack in circuit 160 is an art recognized equivalent. Qaiyum’s BGR circuit 160, the component labeled "1X" is depicted as a bipolar junction transistor (BJT). It is part of a current mirror or a proportional-to-absolute-temperature (PTAT) current generator, which is a common building block in bandgap reference circuits. Specifically, 1X, along with 162 and 161, forms a structure for generating a current that is proportional to absolute temperature (PTAT current), which is crucial for temperature compensation in the bandgap reference. A MOSFET can be used to implement current mirrors and current sources, similar to how BJTs are used.
Luzzi discloses a test circuit to monitor a bandgap circuit that outputs a bandgap reference voltage. Luzzi discloses a fourth transistor (fig 3A, PMOS transistor M8) is of a same type as the second transistor (fig 1, PMOS transistor M6, both transistors are PMOS transistors).
Some teaching, suggestion, or motivation in the prior art would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the BGR circuit 160 of Qaiyum to include a PMOS transistor as the second transistor as taught by Luzzi to provide the advantage of having the second and fourth transistors being the same type as an optional design choice.
Regarding claim 2, Qaiyum and Luzzi disclose the electronic circuit according to claim 1, wherein the reference voltage circuit is configured to be connected to a source of a power supply voltage and to a source of a reference potential (Qaiyum fig 1B, BGR circuit 160 and 110 is connected between VDD power supply and VSS ground), wherein the first transistor and the second transistor are series-coupled between the source of the power supply voltage and the source of the reference potential (Qaiyum fig 1B, top PMOS transistor in circuit 160 and second transistor bottom bipolar junction BJT 1X (modified as a PMOS transistor) are shown series coupled between VDD and VSS), and wherein the third transistor and the fourth transistor are series-coupled between the source of the power supply voltage and the source of the reference potential (Qaiyum fig 1B, third transistor 126 and the fourth transistor 127 are series coupled between VDD and VSS).
Regarding claim 3, Qaiyum and Luzzi disclose the electronic circuit according to claim 1, wherein the first, second, third, and fourth transistors are MOS transistors (Qaiyum fig 1B, first top PMOS transistor, second bottom bipolar junction BJT 1X (modified as a PMOS transistor) in circuit 160, third PMOS transistor 126 and fourth PMOS transistor 127 in circuit 120 are all PMOS transistors).
Regarding claim 12, it is the method version of claim 1 and is rejected for the reasons above.
Regarding claim 13, Qaiyum discloses an electronic circuit (fig 1B, BGR startup verification circuit 100, BGR circuit 160, and startup circuit not shown; par [0016] “A startup circuit for the BGR circuit 160 is not shown in FIGS. 1A or 1B, but can generally comprise any startup circuit, which can be optionally be included on the same chip with the BGR circuit 160 and the startup verification circuit 100.”), comprising: a reference voltage circuit (fig 1B, BGR Circuit 160 and current mirror 110) including a first circuit comprising transistors (fig 1B, top PMOS transistor and bottom bipolar junction BJT 1X transistor in circuit 160); and a start check circuit (fig 1B, Startup verification circuit 100) configured to check starting operation of the reference voltage circuit (abstract “circuitry for processing these outputs to determine whether the BGR circuit has properly started”); wherein the start check circuit configured to check starting operation comprises a second circuit comprising transistors (fig 1B, PMOS transistor 126 and PMOS transistor 127); wherein one or more signals input to the first circuit are also input to the second circuit (fig 1B, they share the signal input VBG); and wherein an output of the second circuit provides a first test signal (fig 1B, OK1).
Qaiyum does not disclose wherein the second stack of transistors is a replica of the first stack of transistors. Qaiyum’s first, second, and fourth transistors are PMOS transistors and the second transistor is a bipolar junction BJT. Qaiyum discloses in par [0015] “The BGR circuit 160 shown in FIG. 1B is a continuous time BG circuit having a self-biased amplifier 161 and Delta-VBE-over-R bias circuit 162 shown including a PNP-bipolar current mirror. However, disclosed embodiments are generally applicable to any type of BGR circuit, such as a classical Widlar Bandgap Voltage Reference, a CMOS Bandgap Reference using PNP Lateral bipolar junction transistors (BJTs), a CMOS Bandgap Reference using substrate PNP BJTs, a weak inversion Bandgap Voltage Reference, and a Brokaw reference circuit.” The instant application reference voltage circuit closely resembles a Brokaw reference circuit. The indication that Qaiyum’s BGR circuit 160 could be of a different type of bandgap voltage reference circuit allows one of ordinary skill in the art to recognize that substituting or adding additional components, in this case, implementing a PMOS transistor in series with the top PMOS transistor of circuit 160 as the second transistor of the transistor stack in circuit 160 is an art recognized equivalent. Qaiyum’s BGR circuit 160, the component labeled "1X" is depicted as a bipolar junction transistor (BJT). It is part of a current mirror or a proportional-to-absolute-temperature (PTAT) current generator, which is a common building block in bandgap reference circuits. Specifically, 1X, along with 162 and 161, forms a structure for generating a current that is proportional to absolute temperature (PTAT current), which is crucial for temperature compensation in the bandgap reference. A MOSFET can be used to implement current mirrors and current sources, similar to how BJTs are used.
Luzzi discloses a test circuit to monitor a bandgap circuit that outputs a bandgap reference voltage. Luzzi discloses a second stack of transistors (fig 3A, PMOS transistors M7 and M8) is a replica of the first stack of transistors (fig 1, PMOS transistors M5 and M6).
Some teaching, suggestion, or motivation in the prior art would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the BGR circuit 160 of Qaiyum to include a PMOS transistor as the second transistor as taught by Luzzi to provide the advantage of having the first, second, third, and fourth transistors being the same type as an optional design choice for replication of series PMOS transistors throughout the circuit.
Regarding claim 16, Qaiyum and Luzzi disclose the electronic circuit of claim 13, wherein the reference voltage circuit is configured to be connected to a source of a power supply voltage and to a source of a reference potential (Qaiyum fig 1B, BGR circuit 160 and 110 is connected between VDD power supply and VSS ground), wherein the first circuit is coupled between the source of the power supply voltage and the source of the reference potential (Qaiyum fig 1B, top PMOS transistor in circuit 160 and second transistor bottom bipolar junction BJT 1X (modified as a PMOS transistor) are shown series coupled between VDD and VSS), and wherein the second circuit is coupled between the source of the power supply voltage and the source of the reference potential (Qaiyum fig 1B, third transistor 126 and the fourth transistor 127 are series coupled between VDD and VSS).
Allowable Subject Matter
Claims 4-11 and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, Qaiyum and Luzzi disclose the electronic circuit according to claim 1, wherein the first transistor is of a same type as the second transistor (Qaiyum fig 1B, first top PMOS transistor, second bottom bipolar junction BJT 1X (modified as a PMOS transistor) in circuit 160), wherein the first elementary test circuit (Qaiyum fig 1B, first verification sub-circuit 120).
Qaiyum fails to disclose the first elementary test circuit, wherein the sixth transistor comprises a sixth control terminal configured to receive a signal at an intermediate node of the second circuit, and wherein the first binary signal corresponds to a voltage at the junction node between the fifth transistor and the sixth transistor.
Luzzi et al. (US 20110001555 A1) discloses a test circuit for monitoring a bandgap circuit. Luzzi discloses a first elementary test circuit (fig 3A, reference voltage test module; shown in the figure is a detailed version of 210 in fig 2) further comprises a fifth transistor in series with a sixth transistor (fig 3A, M5 in series with M6), wherein the fifth transistor comprises a fifth control terminal (fig 3A, M5 gate) configured to receive the first control signal (fig 3A, pbias), wherein the sixth transistor comprises a sixth control terminal (fig 3A, M6 gate).
However, none of the prior art, taken singly or in combination, teach “a sixth control terminal configured to receive a signal at an intermediate node of the second circuit, and wherein the first binary signal corresponds to a voltage at the junction node between the fifth transistor and the sixth transistor”.
Regarding claim 5, Qaiyum and Luzzi disclose the electronic circuit according to claim 1: wherein the reference voltage circuit (Qaiyum fig 1B, BGR Circuit 160 and current mirror 110) further comprises a third circuit comprising a seventh transistor and an eighth transistor (Qaiyum fig 1B, current mirror 110 top PMOS transistor connected in series with bottom NMOS transistor), wherein the seventh transistor comprises a seventh control terminal (Qaiyum fig 1B, current mirror 110 top PMOS transistor gate) configured to receive a third control signal (Qaiyum fig 1B, PTAT1), and wherein the eighth transistor comprises an eighth control terminal (Qaiyum fig 1B, current mirror 110 bottom NMOS transistor gate) configured to receive a fourth control signal; and wherein the start check circuit further comprises at least one second elementary test circuit (Qaiyum fig 1B, second verification sub-circuit 130) configured to deliver a second binary signal (Qaiyum fig 1B, OK2).
However, none of the prior art, taken singly or in combination, teach “second elementary test circuit comprising a fourth circuit comprising a ninth transistor and a tenth transistor, wherein the ninth transistor is of a same type as the seventh transistor and comprises a ninth control terminal configured to receive the third control signal, and wherein the tenth transistor is of a same type as the eighth transistor and comprises a tenth control terminal configured to receive the fourth control signal”.
Regarding claims 6-11 they are allowable for their dependency on allowed claim 5.
Regarding claim 14, Qaiyum and Luzzi disclose the electronic circuit of claim 13: wherein the reference voltage circuit further includes a third circuit comprising transistors (Qaiyum fig 1B, current mirror 110 top PMOS transistor connected in series with bottom NMOS transistor).
However, none of the prior art, taken singly or in combination, teach “wherein the start check circuit configured to check starting operation further comprises a fourth circuit comprising transistors; wherein the fourth circuit is a replica of the third circuit; wherein one or more signals input to the third circuit transistors are also input to the fourth circuit; and wherein an output of the fourth circuit provides a second test signal”.
Regarding claim 15, it is allowable for its dependency on allowed claim 14.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren A Shaw whose telephone number is (571)272-3074. The examiner can normally be reached Mon-Fri 7-5 EST.
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/LAUREN ASHLEY SHAW/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838