Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 5, 9-12, 14, 15, 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US 20180182757 A1) hereafter referred to as Xie.
In regard to claim 1 Xie teaches [see Fig. 16C “FIGS. 16A-16C are different cross-section diagrams illustrating a completed IC structure”] a semiconductor device comprising:
a dielectric pillar [“plug cut trenches 381 can be formed (e.g., lithographically patterned and etched) and filled with yet another dielectric layer 382 (see FIGS. 16A-16C)”] located in contact cut region that is positioned between a first source/drain region [“a first epitaxial semiconductor layer can be deposited into the first source/drain trenches 615 on the first top surface of the first semiconductor fin 311 at the first recessed source/drain regions 314′ in order to form first epitaxial source/drain regions 315”] of a first transistor and a second source/drain region [“A second epitaxial semiconductor layer can then be deposited into the second source/drain trenches 625 on the second top surface of the second semiconductor fin 321 at the second recessed source/drain regions 324′ to form second epitaxial source/drain regions 325”] of a second transistor;
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a first source/drain (S/D) contact structure [The Examiner notes that the claim does not differentiate the material of “first source/drain (S/D) contact structure” and “second S/D contact structure” from the material of “metal conductive liner”, thus under broadest reasonable interpretation the 318 and 328 can be divided into an upper portion in contact with a lower portion and thus the upper portion of “first wrap-around metal plugs 318” is the “first source/drain (S/D) contact structure”. The Examiner notes that the portion of 318 and 328 immediately above 395 exactly matches the 22A and 22B of the instant Application Fig. 10, thus for the purpose of amendment the Examiner suggests that the Applicant clarify the claim by specifying a material difference rather than a limitation based on shape ] located on a first side of the dielectric pillar and electrically connected [see Fig. 16C it is the contact for the source/drain] to the first source/drain region;
a second S/D contact structure [see above, and similarly, the upper portion of “second wrap-around plugs 328” is “second S/D contact structure”] located on a second side of the dielectric pillar and electrically connected [see Fig. 16C it is the contact for the source/drain] to the second source/drain region;
a first metal semiconductor alloy liner [“a metal silicide layer 395 can be formed on exposed semiconductor surfaces (i.e., on the exposed top and side surfaces of the first epitaxial source/drain regions 315 and on the exposed top and side surfaces of the second epitaxial source/drain surfaces 325)”] continuously wrapping around the first source/drain region;
a second metal semiconductor alloy liner [see above “metal silicide layer 395”] continuously wrapping around the second source/drain region; and
a metal conductive liner [ i.e. the lower portion of “first wrap-around metal plugs 318” and the lower portion of “second wrap-around plugs 328” see “process of forming the plug cut trenches 381 can specifically be performed so as to cut the metal plug layer 394 into discrete first wrap-around metal plugs 318 adjacent to the first source/drain surfaces (i.e., the top and side surfaces of the first epitaxial source/drain regions 315) and discrete second wrap-around plugs 328 adjacent to the second source/drain surfaces (i.e., the top and side surfaces of the second epitaxial source/drain regions 325), as shown in FIG. 16C”] located on the first side of the dielectric pillar and on the second side of the dielectric pillar, wherein the metal conductive liner located on the first side of the dielectric pillar forms an interface [see Fig. 16C] with the first S/D contact structure and the first metal semiconductor alloy liner, and the metal conductive liner located on the second side of the dielectric pillar forms an interface [see Fig. 16C] with the second S/D contact structure and the second metal semiconductor alloy liner.
In regard to claim 4 Xie teaches wherein the first metal semiconductor alloy liner [see Fig. 16C, see “a metal silicide layer 395” is symmetric] and the second metal semiconductor alloy liner are both symmetric liners.
In regard to claim 5 Xie teaches wherein the first source/drain region [see Fig. 16C, see “first epitaxial source/drain regions 315” and “second epitaxial source/drain regions 325” are symmetric with no tips] and the second source/drain region are both symmetrically shaped source/drain regions having no tips on either side of the first source/drain region and the second source/drain region.
In regard to claim 9 Xie teaches wherein the dielectric pillar extends down to a shallow trench isolation structure [see Fig. 16C see paragraph 0038 see that “dielectric layer 382” extends to “isolation region 305 (H.sub.STI)” “a silicon oxide layer can be deposited over the semiconductor fins 311, 321 and recessed to form such an isolation region 305” ] that separates a first active area containing the first transistor from a second active area containing the second transistor.
In regard to claim 10 Xie teaches [see claim 1 there is no way to differentiate “S/D contact structure” from the “metal conductive liner” the Examiner notes that the portion of 318 and 328 immediately above 395 exactly matches the 22A and 22B of the instant Application Fig. 10, thus until the Applicant clarifies the claim 1 to differentiate the material of “S/D contact structure” from the “metal conductive liner”, see Fig. 16C satisfies the claim limitation of coplanar. The Examiner notes that even for the sake of compact prosecution, the Examiner cannot create limitations for the claim 1 and then examine it.] wherein the dielectric pillar has a topmost surface that is coplanar with a topmost surface of each of the first S/D contact structure, the second S/D contact structure and the metal conductive liner.
In regard to claim 11 Xie teaches wherein the dielectric pillar extends directly beneath a bottommost surface of [see Fig. 16C see paragraph 0038 see that “dielectric layer 382” extends to “isolation region 305 (H.sub.STI)” “a silicon oxide layer can be deposited over the semiconductor fins 311, 321 and recessed to form such an isolation region 305” “dielectric layer 382 can be a layer of interlayer dielectric (ILD) material. The ILD material can be, for example, silicon oxide or any other suitable ILD material”, thus 382 and 305 together can be the dielectric pillar, satisfying the claim limitations] each of the first metal semiconductor alloy liner, the second metal semiconductor alloy liner and the metal conductive liner.
In regard to claim 12 Xie teaches wherein the first metal semiconductor alloy liner [see claim 1 “a metal silicide layer 395”] and the second metal semiconductor alloy liner are both composed of a metal silicide.
In regard to claim 14 Xie teaches further comprising a middle-of-the-line (MOL) dielectric layer [see Fig. 11A see blanket layer, “blanket dielectric layer 398 can be a silicon oxide layer or other suitable blanket dielectric layer”] adjacent to the first source/drain region and the second source/drain region.
In regard to claim 15 Xie teaches wherein the MOL dielectric layer embeds [see Fig. 11A see blanket layer, “blanket dielectric layer 398 can be a silicon oxide layer or other suitable blanket dielectric layer”] the first metal semiconductor alloy liner, the first S/D contact structure, the second metal semiconductor alloy liner and the second S/D contact structure.
In regard to claim 18 Xie teaches wherein [see Fig. 16C, see paragraph 0035 “one or more single-fin FINFETs (e.g., a pair of parallel semiconductor fins, including a first semiconductor fin 311 for a first FINFET 310, such as an N-type FINFET, and a second semiconductor fin 321 for a second FINFET 320, such as a P-type FINFET) can be formed on the semiconductor wafer 302 (202, see FIGS. 3A-3C)”] the first transistor and the second transistor are both finFETs.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 3, 6, 8, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 20180182757 A1) hereafter referred to as Xie in view of Lee et al. (US 20180337176 A1) hereafter referred to as Lee
In regard to claim 2 Xie does not teach wherein the first metal semiconductor alloy liner and the second metal semiconductor alloy liner are both asymmetric liners having a length in the contact cut region that is larger than a length that is present on a side of the first source/drain region and the second source/drain region that is opposite the contact cut region.
However see Lee Fig. 21A-D see the shape of the epitaxial source/drain is like a diamond before etching, “the cross section of the S/D structure 120 has a diamond shape, a pillar shape or a bar shape” see paragraph 0131 “In FIG. 21B, only one of the side portions of the epitaxial layer of the first conductivity type S/D structures 220 has an etched surface, while both sides of the epitaxial layer of the second conductivity type S/D structures 221 have etched surfaces. Accordingly, the first conductivity type S/D structures 220 has an asymmetric cross section with respect to the fin structure 204 along the Y direction”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Xie to include wherein the first metal semiconductor alloy liner and the second metal semiconductor alloy liner are both asymmetric liners having a length in the contact cut region that is larger than a length that is present on a side of the first source/drain region and the second source/drain region that is opposite the contact cut region.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is ease of manufacture of high density since epitaxial growth naturally gives the diamond shape and then dividing the transistors gives asymmetry based on number of source drains included in each trasistor due to design needs.
In regard to claim 3 Xie and Lee as combined teaches wherein the first source/drain region and the second source/drain region are both asymmetrically shaped source/drain regions having a tip [see this is the tip due to a diamond shape epitaxial growth] located on a side opposite the contact cut region and a sidewall in the contact cut region that is substantially perpendicular [see this is due to dividing the source drain regions into two transistors] to a horizontal surface of a semiconductor substrate that is located beneath the first transistor and the second transistor.
In regard to claim 6 Xie and Lee as combined teaches further comprising an additional metal conductive liner [see combination Lee this is to create high density by dividing the diamond shaped source/drains to form plurality of transistors ] and an additional dielectric pillar located on a side of the first source/drain region and the second source/drain region that is opposite the contact cut region.
In regard to claim 8 Xie does not specifically teach further comprising a first metal line electrically connected to the first S/D contact structure by a first metal via, and a second metal line electrically connected to the second S/D contact structure by a second metal via.
However vias and interconnects are common in the art, see Lee paragraph 0129 “After forming the contacts 250, further CMOS processes are performed to form various features such as additional interlayer dielectric layers, contacts/vias, interconnect metal layers, and passivation layers, etc”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Xie to include further comprising a first metal line electrically connected to the first S/D contact structure by a first metal via, and a second metal line electrically connected to the second S/D contact structure by a second metal via.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to make dense and complex circuits using multilayer interconnect structures connected to the devices using vias.
In regard to claim 13 Xie teaches [“a metal silicide layer 395”], thus Xie does not teach wherein the first metal semiconductor alloy liner and the second metal semiconductor alloy liner are both composed of a metal germanide.
See Lee teaches see paragraph 0038 “substrate 101 having one or more fin structures” “substrate 101 may be made of a suitable elemental semiconductor, such as silicon, diamond or germanium; a suitable alloy or compound semiconductor, such as Group-IV compound semiconductors (silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), Group III-V compound semiconductors (e.g., gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium arsenide (InAs), indium phosphide (InP), indium antimonide (InSb), gallium arsenic phosphide (GaAsP), or gallium indium phosphide (GaInP)), or the like”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Xie to include wherein the first metal semiconductor alloy liner and the second metal semiconductor alloy liner are both composed of a metal germanide.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is control of the bandgap of the fin and resulting control of the transistor performance by using semiconductor choice including germanium or SiGe compound semiconductors.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 20180182757 A1) hereafter referred to as Xie in view of Frougier et al. (US 20200119180 A1) hereafter referred to as Frougier
In regard to claim 7 Xie does not teach further comprising a void at a bottom of the dielectric pillar that is located between in the contact cut region.
Frougier teaches see paragraph 0033 “dielectric liner conformally deposited to form dielectric pillar 801 can be Si.sub.3N.sub.4 or low-k dielectric materials such as SiCBN, SiOC, SiCON or any other material with similar functional properties. The pinch-off mechanism of the trench 503 by the conformal dielectric liner can trigger the encapsulation of an air-gap or void 803 in the negatively tapered region of the source-drain epitaxy contacts 109 depending on the geometry of the source-drain epitaxy contacts 109 and sacrificial cap layer 301 relative to the trench 503. The air-gap or void 803 encapsulated at the bottom of the dielectric pillar 801 provides additional reduction of the parasitic capacitance between adjacent source-drain regions and improves the electrical performance of the device”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Xie to include further comprising a void at a bottom of the dielectric pillar that is located between in the contact cut region.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to use source-drain geometry to create an air gap or void to obtain the benefit of reduction of the parasitic capacitance.
Claim(s) 16, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 20180182757 A1) hereafter referred to as Xie in view of Ghosh et al. (US 20240112916 A1) hereafter referred to as Ghosh
In regard to claim 16 Xie does not teach wherein the first transistor and the second transistor are both nanosheet field effect transistors (FETs).
See Ghosh Fig. 1A see paragraph 0021, 0034 “Each of semiconductor devices 101 and 103 may be non-planar metal oxide semiconductor (MOS) transistors, such as tri-gate (e.g., finFET) or gate-all-around (GAA) transistors, although other transistor topologies and types could also benefit from the techniques provided herein. The illustrated embodiments herein use the GAA structure” “semiconductor region can be, for example, a fin of semiconductor material that extends from a source region to a drain region, or one or more nanowires or nanoribbons or nanosheets of semiconductor material that extend from a source region to a drain region” “term nanoribbon may also encompass other similar shapes such as nanowires or nanosheets”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Xie to include wherein the first transistor and the second transistor are both nanosheet field effect transistors (FETs).
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that nanosheet transistors are known to give excellent gate control and excellent current and performance.
In regard to claim 17 Xie and Ghosh as combined teaches wherein the first transistor comprises a plurality [see combination Ghosh, see Ghosh Fig. 1 see “Nanoribbons 104”] of vertically stacked first semiconductor channel material nanosheets and the second transistor comprising a plurality of vertically stacked second semiconductor channel material nanosheets.
Claim(s) 19, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ghosh et al. (US 20240112916 A1) hereafter referred to as Ghosh in view of Chiu et al. (US 20210313424 A1) hereafter referred to as Chiu
In regard to claim 19 Ghosh teaches a method of forming [see Fig. 10B] a semiconductor device, the method comprising:
forming a semiconductor structure comprising a first source/drain region [see “source or drain region 502”on the left of “gate cut recess 1102” in Fig. 11B] of a first transistor located in a first active area [see on the left of “gate cut recess 1102” in Fig. 11B], a second source/drain region [see “source or drain region 502” on the right of “gate cut recess 1102” in Fig. 11B] of a second transistor located in a second active area [see on the right of “gate cut recess 1102” in Fig. 11B] and a MOL dielectric layer [see in Fig. 7B that 506 is above 502, “another dielectric fill 506 is provided along the source/drain trench. Dielectric fill 506 may extend between adjacent ones of the source or drain regions 502 along the second direction and also may extend up and over each of the source or drain regions 502, according to some embodiments”, see that in Fig. 10B there is a portion of 506 extending above the space in between 502 thus under broadest reasonable interpretation is “above and adjacent to”, see “FIGS. 8A and 8B depict the cross-section views of the structure shown in FIGS. 7A and 7B, respectively, following the formation of contact recesses 802 through dielectric fill 506, according to some embodiments. Contact recesses 802 may be formed in locations where conductive contacts are to be later formed. In some embodiments, a contact recess 802 is formed over only one source or drain region 502. In some embodiments, a contact recess 802 may be formed across more than one source or drain region 502, such as the central illustrated contact recess 802. According to some embodiments, contact recesses 802 are etched using an isotropic etching process that selectively etches the material of dielectric fill 506 as opposed to the material of source or drain regions 502. Contact recesses 802 may be etched deep enough to expose at least a top surface of source or drain regions 502, and in some cases are etched deeper to expose side surfaces of source or drain regions 502” see for example the instant Application says “MOL dielectric layer 18 located above and adjacent to the first source/drain region 16 and the second source/drain region 16. The step is illustrated in FIG. 2 of the present application” and see it is removed above the source/drain in Fig. 3 “Referring now to FIG. 3, there is illustrated the exemplary semiconductor structure shown in FIG. 2 after forming a S/D trench metal contact structure including a metal semiconductor alloy layer located on each of the first source/drain region 16 and the second source/drain region 17 and a shared contact conductor metal 22”, thus what the Applicant means is that to the side of the source/drain, the MOL dielectric layer extends higher than the source/drain and this is the broadest reasonable interpretation of “above and adjacent to”] located above and adjacent to the first source/drain region and the second source/drain region;
forming a source/drain (S/D) trench metal contact structure [see “liner structure 902 may include a first conductive layer that includes a titanium-based material, such as titanium nitride, titanium silicide, or titanium germano-silicide, and a second conductive layer that includes a combination of tungsten, carbon, and nitrogen” “Conductive contacts 1002 may be formed directly on liner structure 902 such that a conductive pathway exists between a given conductive contact 1002 and its respective source or drain region 502 via liner structure 902. Conductive contacts 118 may be any suitably conductive material such as tungsten (W). Other conductive materials may include copper (Cu), ruthenium (Ru), cobalt (Co), titanium (Ti), molybdenum (Mo), or any alloys thereof”] including a metal semiconductor alloy layer [902] located on each of the first source/drain region and the second source/drain region and a shared contact [1002] conductor metal;
cutting the S/D trench metal contact structure to form [see Fig. 11B] a contact cut region, wherein the cutting removes the metal semiconductor alloy layer from both the first source/drain region and the second source/drain region in the contact cut region and cuts the shared contact [see Fig. 11B] conductive metal into individual S/D contact structures;
filling a remaining volume of the contact cut region [“Gate cut 1202 may include only silicon oxide or silicon nitride or silicon carbide. In some examples, gate cut 1202 includes a first dielectric layer deposited first and a second dielectric layer or dielectric fill formed on the first dielectric layer”] with a contact cut dielectric material.
but does not teach forming additional metal semiconductor alloy layer on physically exposed surfaces of the first source/drain region and the second source/drain region in the contact cut region; selectively depositing a conductive material liner in the contact cut region.
However it is simply a question of conductivity, see Chiu see paragraph 0022, 0031 “In some embodiments, a silicide layer is formed over an epitaxial source/drain feature, and a seed metal layer is formed over the silicide layer. The silicide layer and the seed metal layer are formed before a gate replacement process in some embodiments, and formed after a gate replacement process in other embodiments. A contact metal layer is then selectively formed such that it grows on a conductive surface (e.g., the seed metal layer) but not on dielectric surfaces. A fill metal layer may be formed over the contact metal layer to facilitate a subsequent CMP process. In some embodiments, the contact metal layer is formed directly on the silicide layer (without the intervening seed metal layer)” “Still referring to FIG. 3A, in step 76 of the method 70 (FIG. 2), a seed metal layer 142 is formed on the silicide layer 140 in the opening 136” “In some embodiments, the seed metal layer 142 is selectively formed such that it grows only on a conductive surface (e.g., the silicide layer 140) but not on dielectric surfaces (e.g., the dummy gate stacks 130 and the gate spacers 132). This helps with the trench filling performance, as well as avoiding any potential bottle necks in the opening 136. The selective formation of the seed metal layer 142 may be realized by controlling process conditions including the pressure and/or the flow rate of a precursor used to form the seed metal layer 142”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Ghosh to surface the source/drain semiconductor with metal prior to filling the cut trench with dielectric i.e. to modify Ghosh to include forming additional metal semiconductor alloy layer on physically exposed surfaces of the first source/drain region and the second source/drain region in the contact cut region; selectively depositing a conductive material liner in the contact cut region.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to reduce resistance to improve conduction and performance.
In regard to claim 20 Ghosh and Chiu as combined teaches further comprising forming [see Ghosh Fig. 10B see “conductive contacts 1002” above “dielectric fill 506” see Fig. 13 see paragraph 0074 “Package substrate 1306 may be any standard or proprietary package substrate, but in some cases includes a dielectric material having conductive pathways (e.g., including conductive vias and lines) extending through the dielectric material between the faces of package substrate 1306, or between different locations on each face” “One or more dies 1302 may include at least one integrated circuit having semiconductor devices, such as any of the semiconductor devices disclosed herein”] metal vias and metal lines above the MOL dielectric layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893