DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This final office action is responsive to Applicants' application filed on 04/01/2026. Claims 1-27 are presented for examination and are pending for the reasons indicated herein below.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant's arguments filed 04/01/26 have been fully considered but they are not persuasive.
Applicant argues:
Rejection of Claim 20 under 35 U.S.C. § 101
The office action rejects claim 20 as being patent ineligible. Applicants respectfully disagree. Claim 20 recites computer readable storage hardware which would never be confused with a wireless computer readable medium. Accordingly, claim 20 is patent eligible.
Examiner respectively disagrees: “Hardware” is not limited to a computer-readable media in the art. “Hardware” is unclear and could encompass enclosures, connectors, or other physical components that are not readable and the sense require for storing executable instructions. The wording fails to clearly recite the statutory article of manufacture, creating §101 subject matter eligibility issues, because “hardware” is vague and does not explicitly exclude transitory signals. This ambiguity makes it unclear was structures are included.
Applicant argues:
Applicants respectfully submit that the claimed invention includes limitations over the cited prior art and that the combination of references does not render the claimed invention as being obvious.
To reject claim 1, the office action cites Nakanishi at FIG. 6, which appears as follows:
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Nakanishi at corresponding paragraphs paragraph 134, which reads as follows:
[0056] As shown in FIG. 6 , the controller 20 receives output voltage Vout of the LLC converter 10 and calculates a deviation err between target voltage Vref and the output voltage Vout, and the deviation err is inputted to the control unit 22. The control unit 22 performs control calculation through PI (Proportional-Integral) control so that the inputted deviation err comes close to zero, and outputs a value Za of a manipulated variable Z.
[0057] The controller 20 includes a function 23, i.e., F(Z)=(θ, f), which uniquely associates the manipulated variable Z with a combination (θ, f) of the phase shift amount θ and the frequency f. Then, on the basis of the included function 23 (F(Z)), a combination (θ, f) of the phase shift amount θ and the frequency f corresponding to the calculated value Za of the manipulated variable Z is acquired. The acquired combination (θ, f) is inputted to a gate signal generation circuit 24. The gate signal generation circuit 24 generates the gate signals 21 for the semiconductor switches Q of the inverter circuit 1 on the basis of the inputted phase shift amount θ and frequency f, and the gate signals 21 are outputted from the controller 20. (emphasis added)
Nakanishi indicates to implement the function F(z) to convert the input signal Za into a phase shift signal and corresponding frequency. In contrast to the cited prior, the claimed invention recites a controller operative to: derive a control period setting from an error voltage, the error voltage generated based on a comparison of the output voltage feedback signal to a setpoint reference voltage, a magnitude of the control period setting derived via an inversion function disposed in a feedback control loop receiving the error voltage.
To further reject claim 1 the office action cites Wang at FIGS. 2 A and 2 B, which appears as follows:
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Additionally, the office action cites paragraph 35 in Wang, which reads as follows:
[0035] Controller 110 may be configured to determine the gradient of lines 210A and 210B based on Equation (1) shown below. In Equation (1), K.sub.Vcs offset represents the gradient of line 210A and the inverse of the gradient of line 210B. Vcs.sub.offset.sub._.sub.LowV in Equation (1) is maximum value 220 of the offset value Vcs.sub.offset. Vzcd.sub.LowV is value 230 of the first signal that is associated with the maximum value of the offset value. Vzcd.sub.zero.sub._.sub.point is value 232 of the first signal that is associated with a zero value of the offset value.
k.sub.Vcs.sub.offset=(Vcs.sub.offset.sub.LowV/(Vzcd.sub.LowV−Vzcd.sub.zero point)) (1) (emphasis added)
Applicants respectfully submit that Wang indicates to determine an offset voltage value associated with a zero crossing detection voltage and a Vcs offset voltage. This has nothing to do with deriving a control period setting from an error voltage, especially not in which a magnitude of the control period setting is derived based at least in part on an inverse function disposed in a feedback control loop receiving the error voltage.
Examiner respectively disagrees: The error signal generated by the difference between the voltage reference and the feedback signal is configured to dynamically influence the output characteristics of the gate signal generation circuit which produces the controlled period setting. Thus, having the control period setting based on the output comparison (error signal) of the output voltage and the reference voltage. Wang also generates a gate drive signal (control period setting), for the same analysis as above. Fig 3, 300 outputs an error signal that dynamically influences the output of 380.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. The claimed invention is directed to non-statutory subject matter. Claim 20 does/do not fall within at least one of the four categories of patent eligible subject matter because a computer readable medium has not been specifically defined in the specification to exclude signals, examiner recommends amending to "A non-transitory computer readable medium."
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9, 16-17, 20 rejected under 35 U.S.C. 103 as being unpatentable over NAKANISHI et al. (US 20240235403 A1 and hereinafter as Nak) in view of Wang et al. (US 20200112241 A1)
Regarding claim 1. Nak teaches an apparatus [fig 1] comprising: a controller [20] operative to: receive an output voltage feedback signal outputted from a resonant power converter [see 10 and 8], the output voltage feedback signal tracking a magnitude of an output voltage outputted from the resonant power converter to power a load [12];
derive a control period setting from an error voltage [fig 6, err], the error voltage generated based on a comparison [i.e. err is generated by citing that Vref is different from Vout] of the output voltage feedback signal to a setpoint reference voltage [Vref];
and control switching [output of 24] of switches in the resonant power converter in accordance with the derived control period setting. However, Nak does not explicitly mention magnitude of the control period setting derived based at least in part on an inverse function disposed in a feedback control loop receiving the error voltage.
Wang teaches a circuit comprising: magnitude of the control period setting derived based at least in part on an inverse function [¶35] disposed in a feedback control loop [loop of fig3] receiving the error voltage [output of 300].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include the description of producing a control period based on an inverse function use by a PID controller from Wang because one of ordinary skill in the art would recognize that the feature is necessary to make the system of Nak regulate the output voltage while reducing steady state errors.
Regarding claim 2. Nak as modified teaches the apparatus as in claim 1, wherein the controlled switching of the switches in the resonant power converter in accordance with the derived control period setting is operative to provide non-linear frequency gain [Nak’s invention follows this limitation, since a based on the feedback the PID controller ¶69-¶71] of regulating a magnitude of the output voltage with respect to changes in the error voltage [i.e. function of err signal].
Regarding claim 3. Nak as modified teaches the apparatus as in claim 2, wherein the non-linear frequency gain of regulating the magnitude of the output voltage based on the error voltage is operative to provide lower control loop gain for below-resonance operation of the resonant power converter and higher control loop gain for above-resonance operation of the resonant power converter [Nak’s invention follows this limitation, since a based on the feedback the PID controller when operating below resonance the gain is typically lower as the controller adjust to ensure stability and when above resonance the gain increases to counteract the drop in phase margin, this results in nonlinear across the frequency].
Regarding claim 4. Nak as modified teaches the apparatus as in claim 1, wherein a conversion of the error voltage into the derived control period setting is operative to provide a non-linear frequency response of controlling the switches in the resonant power converter [function of PID controller, see rejection to claim 3].
Regarding claim 9. Nak teaches the apparatus as in claim 1, wherein the controller is further operative to: receive a nominal switching frequency value [Vout is indicative of the nominal switching frequency value]; and adjust a magnitude of the nominal switching frequency value to produce the derived control period setting [i.e. err] based on a received adjustment signal Y derived at least in part from the error voltage.
Regarding claim 20. Computer-readable storage hardware [i.e. controller, fig 6] having instructions stored thereon [implicit being a PID controller], the instructions, when carried out by computer processor hardware, cause the computer processor hardware to:
receive an output voltage feedback signal [i.e. Vout in fig 6] outputted from a resonant power converter [10], the output voltage feedback signal tracking a magnitude of an output voltage outputted from the resonant power converter to power a load [implicit from Vout]; derive a control period setting from an error voltage [err], the error voltage generated based on a comparison [i.e. err is generated by citing that Vref is different from Vout] of the output voltage feedback signal to a setpoint reference voltage [Vref]; and control switching [output 24] of switches in the resonant power converter in accordance with the derived control period setting.
However, Nak does not explicitly mention a magnitude of the control period setting derived at least in part on an inverse function disposed in a feedback control loop receiving the error voltage.
Wang teaches a circuit comprising: magnitude of the control period setting derived at least in part on an inverse function [¶35] disposed in a feedback control loop [loop of fig3] receiving the error voltage [output of 300].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include the description of producing a control period based on an inverse function use by a PID controller from Wang because one of ordinary skill in the art would recognize that the feature is necessary to make the system of Nak regulate the output voltage while reducing steady state errors.
Regarding method claims 16-17, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device "inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated.
Allowable Subject Matter
Claims 6-7, 10-15, 18, 22-27 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the claim objections stated above were overcome.
Examiner Note
The examiner cites particular columns and lines numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bryan Perez whose telephone number is (571)272-8837. The examiner can normally be reached on Mon.-Fri. (7:30 – 5:00).
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Crystal Hammond, can be reached on (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R PEREZ/Examiner, Art Unit 2838
Prosecution Insights