DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 12 and 17 are objected to because of the following informalities:
Regarding claim 12, “the supporting layer” in line 2 should be changed to “the support layer”.
Regarding claim 17, “A semiconductor device” in line 1 should be changed to “The semiconductor device”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 15 recites the limitation "the third direction" in lines 2 and 5 and “the supporting pattern” in line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. (US 2022/0173118 A1; hereinafter “Kang”).
Regarding claim 1, referring to at least Figs. 41-44 and related text, Kang teaches a semiconductor device comprising: a lower circuit pattern (a lower circuit pattern including first and second transistors) disposed on a substrate (100) (paragraphs 59-65); a common source plate (CSP) (240) disposed on the lower circuit pattern (paragraphs 66-67); a channel connection pattern (510) disposed on the CSP (paragraphs 128-129); a sacrificial layer structure (290) disposed on the CSP, wherein the sacrificial layer structure is spaced apart from the channel connection pattern (paragraph 68); a support layer (300) disposed on the channel connection pattern and the sacrificial layer structure (paragraph 70); first and second gate electrode structures each including gate electrodes (first and second gate electrode structures at least including 752, 754, and 756 in I and II) sequentially stacked on the support layer and spaced apart from each other in a first direction (D1) substantially perpendicular to an upper surface of the substrate (an upper surface of 100), wherein each of the gate electrodes extends in a second direction (D2/D3) substantially parallel to the upper surface of the substrate (paragraphs 154-155); a first channel (462) disposed on the CSP, wherein the first channel extends through the first gate electrode structure, the support layer and the channel connection pattern (paragraphs 109-110); and a contact plug (660) extending through the second gate electrode structure, the support layer, the sacrificial layer structure and the CSP, wherein the contact plug is electrically connected to the lower circuit pattern (paragraphs 161-162).
Regarding claim 2, Kang teaches further comprising a division pattern (620/625) separating the first and second gate electrode structures, wherein the division pattern extends in the second direction and contacts sidewalls of the gate electrodes included in the first and second gate electrode structures (Figs. 42-43 and paragraphs 156-157).
Regarding claim 3, Kang teaches wherein the division pattern extends through the support layer and the channel connection pattern, and contacts an upper surface of the CSP (Figs. 42-43).
Regarding claim 4, Kang teaches further comprising a support pattern (305) disposed between the channel connection pattern and the sacrificial layer structure, wherein the support pattern contacts an upper surface of the CSP and includes substantially a same material as that of the support layer (Fig. 41 and paragraph 70).
Regarding claim 5, Kang teaches wherein the support pattern overlaps the second gate electrode structure in the first direction (Fig. 41).
Regarding claim 6, Kang teaches further comprising: a support structure (646 or another 620) extending through the second gate electrode structure and the support pattern, and contacting the upper surface of the CSP (Fig. 42 and paragraphs 109 and 156-157).
Regarding claim 7, Kang teaches wherein the support structure includes a protrusion portion (lateral protruded portion of 620) extending from a sidewall of the support structure, wherein the sidewall of the support structure faces each of sidewalls of the gate electrodes included in the second gate electrode structure in a horizontal direction substantially parallel to the upper surface of the substrate (Fig. 42 and paragraphs 156-157).
Regarding claim 8, Kang teaches further comprising an insulation pattern (600) disposed between a sidewall of each of the gate electrodes included in the second gate electrode structure and a portion of a sidewall of the contact plug facing the sidewall of each of the gate electrodes in a horizontal direction that is substantially parallel to the upper surface of the substrate (Fig. 41 and paragraphs 147-148).
Regarding claim 9, Kang teaches wherein the sacrificial layer structure includes first to third sacrificial layers (260, 270, and 280) sequentially stacked on each other in the first direction, and wherein each of the first and third sacrificial layers includes an oxide, and the second sacrificial layer includes a nitride (paragraph 68).
Regarding claim 10, Kang teaches further comprising an insulation pattern (620) disposed between a sidewall of the second sacrificial layer and a portion of a sidewall of the contact plug facing the sidewall of the second sacrificial layer in a horizontal direction substantially parallel to the upper surface of the substrate, wherein the insulation pattern includes an oxide (Fig. 44 and paragraphs 156-157).
Regarding claim 11, Kang teaches further comprising a second channel (690) disposed on and electrically connected to the first channel (Fig. 41 and paragraph 166).
Regarding claim 12, Kang teaches wherein each of the channel connection pattern and the supporting layer includes polysilicon doped with impurities (paragraphs 70 and 129), and the sacrificial layer structure includes an insulating material (paragraph 68).
Regarding claim 13, referring to at least Figs. 41-44 and related text, Kang teaches a semiconductor device comprising: a lower circuit pattern (a lower circuit pattern including first and second transistors) disposed on a substrate (100) (paragraphs 59-65); a common source plate (CSP) (240) disposed on the lower circuit pattern (paragraphs 66-67); a channel connection pattern (510) disposed on the CSP (paragraphs 128-129); a sacrificial layer structure (290) disposed on the CSP, wherein the sacrificial layer structure is spaced apart from the channel connection pattern (paragraph 68); a support pattern (305) disposed on the CSP, wherein the support pattern is interposed between the channel connection pattern and the sacrificial layer structure (paragraph 70); a support layer (300) disposed on the channel connection pattern and the sacrificial layer structure, wherein the support layer includes substantially a same material as that of the support pattern and is connected to the support pattern (paragraph 70); first and second gate electrode structures each including gate electrodes (first and second gate electrode structures at least including 752, 754, and 756 in I and II) sequentially stacked on the support layer and spaced apart from each other in a first direction (D1) substantially perpendicular to an upper surface of the substrate (an upper surface of 100), wherein each of the gate electrodes extends in a second direction (D2/D3) substantially parallel to the upper surface of the substrate (paragraphs 154-155); a channel (462) disposed on the CSP, wherein the channel extends through the first gate electrode structure, the support layer and the channel connection pattern (paragraphs 109-110); and a contact plug (660) extends through the second gate electrode structure, the support layer, the sacrificial layer structure and the CSP, wherein the contact plug is electrically connected to the lower circuit pattern (paragraphs 161-162), wherein the support pattern overlaps the second gate electrode structure in the first direction (Fig. 41).
Regarding claim 14, Kang teaches wherein the substrate includes a cell array region (I), in which memory cells are disposed, and an extension region (II) at least partially surrounding the cell array region, and wherein the support pattern extends in the second direction on the cell array region of the substrate (Fig. 41 and paragraph 53).
Regarding claim 15, Kang teaches wherein the first gate electrode structure is disposed at each of opposite sides of the second gate electrode structure in the third direction (“the third direction” is considered as D2 in Kang’s reference), and wherein the supporting pattern (“the supporting pattern” is considered as the claimed support pattern) is disposed on a portion of the CSP that is adjacent to the first gate electrode structures and extends in the third direction (Fig. 41).
Regarding claim 16, Kang teaches further comprising a division pattern (620/625) separating the first and second gate electrode structures, wherein the division pattern extends in the second direction and contacts sidewalls of the gate electrodes included in the first and second gate electrode structures (Figs. 42-43 and paragraphs 156-157).
Regarding claim 17, Kang teaches wherein the division pattern extends through the support layer and the channel connection pattern, and contacts an upper surface of the CSP (Figs. 42-43).
Regarding claim 18, referring to at least Figs. 41-44 and related text, Kang teaches a semiconductor device comprising: a lower circuit pattern (a lower circuit pattern including first and second transistors) disposed on a substrate (100) (paragraphs 59-65); a common source plate (CSP) (240) disposed on the lower circuit pattern (paragraphs 66-67); a channel connection pattern (510) disposed on the CSP (paragraphs 128-129); a sacrificial layer structure (290) disposed on the CSP, wherein the sacrificial layer structure is spaced apart from the channel connection pattern (paragraph 68); a support pattern (305) disposed on the CSP, wherein the support pattern is interposed between the channel connection pattern and the sacrificial layer structure (paragraph 70); a support layer (300) disposed on the channel connection pattern and the sacrificial layer structure, wherein the support layer includes substantially a same material as that of the support pattern, and is connected to the support pattern (paragraph 70); first and second gate electrode structures each including gate electrodes (first and second gate electrode structures at least including 752, 754, and 756 in I and II) sequentially stacked on the support layer and spaced apart from each other in a first direction (D1) substantially perpendicular to an upper surface of the substrate (an upper surface of 100), wherein each of the gate electrodes extends in a second direction (D2/D3) substantially parallel to the upper surface of the substrate (paragraphs 154-155); a division pattern (620/625) extending in the second direction on the CSP through the support layer and the channel connection pattern, wherein the division pattern separates the first and second gate electrode structures from each other (paragraphs 156-157); a first memory channel structure (462) disposed on the CSP, wherein the first memory channel structure extends through the first gate electrode structure and the support layer and is connected to the channel connection pattern (paragraphs 109-110); a second memory channel structure (690) disposed on the first memory channel structure (paragraph 166); a support structure (464) extending through the second gate electrode structure and the support pattern, and contacting an upper surface of the CSP (paragraph 109); and a contact plug (660) extending through the second gate electrode structure, the support layer, the sacrificial layer structure and the CSP, and is electrically connected to the lower circuit pattern (paragraphs 161-162).
Regarding claim 19, Kang teaches wherein the support pattern overlaps the second gate electrode structure in the first direction (Fig. 41).
Regarding claim 20, Kang teaches wherein an upper surface of the first memory channel structure, an upper surface of the support structure and an upper surface of an isolation pattern (one of 620) are substantially coplanar with each other (Figs. 41-43).
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Lee et al. (US 2023/0307353 A1; hereinafter “Lee”).
Regarding claim 1, referring to at least Figs. 29-30 and related text, Lee teaches a semiconductor device comprising: a lower circuit pattern (a lower circuit pattern including first and second transistors) disposed on a substrate (100) (paragraphs 32-38); a common source plate (CSP) (240) disposed on the lower circuit pattern (paragraphs 39-40); a channel connection pattern (510) disposed on the CSP (paragraphs 75-77); a sacrificial layer structure (290) disposed on the CSP, wherein the sacrificial layer structure is spaced apart from the channel connection pattern (paragraphs 43-44); a support layer (300) disposed on the channel connection pattern and the sacrificial layer structure (paragraph 46); first and second gate electrode structures each including gate electrodes (first and second gate electrode structures at least including 752, 754, and 756 in I and II) sequentially stacked on the support layer and spaced apart from each other in a first direction (D1) substantially perpendicular to an upper surface of the substrate (an upper surface of 100), wherein each of the gate electrodes extends in a second direction (D2/D3) substantially parallel to the upper surface of the substrate (paragraphs 102-103); a first channel (462) disposed on the CSP, wherein the first channel extends through the first gate electrode structure, the support layer and the channel connection pattern (paragraph 60); and a contact plug (644/646) extending through the second gate electrode structure, the support layer, the sacrificial layer structure and the CSP, wherein the contact plug is electrically connected to the lower circuit pattern (paragraph 106).
Regarding claim 2, Lee teaches further comprising a division pattern (620) separating the first and second gate electrode structures, wherein the division pattern extends in the second direction and contacts sidewalls of the gate electrodes included in the first and second gate electrode structures (Fig. 30 and paragraphs 104-105).
Regarding claim 3, Lee teaches wherein the division pattern extends through the support layer and the channel connection pattern, and contacts an upper surface of the CSP (Fig. 30).
Regarding claim 4, Lee teaches further comprising a support pattern (305) disposed between the channel connection pattern and the sacrificial layer structure, wherein the support pattern contacts an upper surface of the CSP and includes substantially a same material as that of the support layer (Fig. 29 and paragraph 46).
Regarding claim 5, Lee teaches wherein the support pattern overlaps the second gate electrode structure in the first direction (Fig. 29).
Regarding claim 6, Lee teaches further comprising: a support structure (620) extending through the second gate electrode structure and the support pattern, and contacting the upper surface of the CSP (Fig. 30 and paragraph 104-105).
Regarding claim 7, Lee teaches wherein the support structure includes a protrusion portion (lateral protruded portion of 620) extending from a sidewall of the support structure, wherein the sidewall of the support structure faces each of sidewalls of the gate electrodes included in the second gate electrode structure in a horizontal direction substantially parallel to the upper surface of the substrate (Fig. 30 and paragraphs 104-105).
Regarding claim 8, Lee teaches further comprising an insulation pattern (600) disposed between a sidewall of each of the gate electrodes included in the second gate electrode structure and a portion of a sidewall of the contact plug facing the sidewall of each of the gate electrodes in a horizontal direction that is substantially parallel to the upper surface of the substrate (Fig. 29 and paragraphs 94-95).
Regarding claim 9, Lee teaches wherein the sacrificial layer structure includes first to third sacrificial layers (260, 270, and 280) sequentially stacked on each other in the first direction, and wherein each of the first and third sacrificial layers includes an oxide, and the second sacrificial layer includes a nitride (paragraph 44).
Regarding claim 10, Lee teaches further comprising an insulation pattern disposed between a sidewall of the second sacrificial layer and a portion of a sidewall of the contact plug facing the sidewall of the second sacrificial layer in a horizontal direction substantially parallel to the upper surface of the substrate, wherein the insulation pattern includes an oxide (Fig. 30 and paragraphs 104-105).
Regarding claim 11, Lee teaches further comprising a second channel (668) disposed on and electrically connected to the first channel (Fig. 32 and paragraph 114).
Regarding claim 12, Lee teaches wherein each of the channel connection pattern and the supporting layer includes polysilicon doped with impurities (paragraphs 46 and 76), and the sacrificial layer structure includes an insulating material (paragraph 44).
Regarding claim 13, referring to at least Figs. 29-30 and related text, Lee teaches a semiconductor device comprising: a lower circuit pattern (a lower circuit pattern including first and second transistors) disposed on a substrate (100) (paragraphs 32-38); a common source plate (CSP) (240) disposed on the lower circuit pattern (paragraphs 39-40); a channel connection pattern (510) disposed on the CSP (paragraphs 75-77); a sacrificial layer structure (290) disposed on the CSP, wherein the sacrificial layer structure is spaced apart from the channel connection pattern (paragraphs 43-44); a support pattern (305) disposed on the CSP, wherein the support pattern is interposed between the channel connection pattern and the sacrificial layer structure (paragraph 46); a support layer (300) disposed on the channel connection pattern and the sacrificial layer structure, wherein the support layer includes substantially a same material as that of the support pattern and is connected to the support pattern (paragraph 46); first and second gate electrode structures each including gate electrodes (first and second gate electrode structures at least including 752, 754, and 756 in I and II) sequentially stacked on the support layer and spaced apart from each other in a first direction (D1) substantially perpendicular to an upper surface of the substrate (an upper surface of 100), wherein each of the gate electrodes extends in a second direction (D2/D3) substantially parallel to the upper surface of the substrate (paragraphs 102-103); a channel (462) disposed on the CSP, wherein the channel extends through the first gate electrode structure, the support layer and the channel connection pattern (paragraph 60); and a contact plug (644/646) extends through the second gate electrode structure, the support layer, the sacrificial layer structure and the CSP, wherein the contact plug is electrically connected to the lower circuit pattern (paragraph 106), wherein the support pattern overlaps the second gate electrode structure in the first direction (Fig. 29).
Regarding claim 14, Lee teaches wherein the substrate includes a cell array region (I), in which memory cells are disposed, and an extension region (II) at least partially surrounding the cell array region, and wherein the support pattern extends in the second direction on the cell array region of the substrate (Fig. 29 and paragraphs 25-26).
Regarding claim 15, Lee teaches wherein the first gate electrode structure is disposed at each of opposite sides of the second gate electrode structure in the third direction (“the third direction” is considered as D2 in Lee’s reference), and wherein the supporting pattern (“the supporting pattern” is considered as the claimed support pattern) is disposed on a portion of the CSP that is adjacent to the first gate electrode structures and extends in the third direction (Fig. 29).
Regarding claim 16, Lee teaches further comprising a division pattern (620) separating the first and second gate electrode structures, wherein the division pattern extends in the second direction and contacts sidewalls of the gate electrodes included in the first and second gate electrode structures (Fig. 30 and paragraphs 104-105).
Regarding claim 17, Lee teaches wherein the division pattern extends through the support layer and the channel connection pattern, and contacts an upper surface of the CSP (Fig. 30).
Regarding claim 18, referring to at least Figs. 29-30 and related text, Lee teaches a semiconductor device comprising: a lower circuit pattern (a lower circuit pattern including first and second transistors) disposed on a substrate (100) (paragraphs 32-38); a common source plate (CSP) (240) disposed on the lower circuit pattern (paragraphs 39-40); a channel connection pattern (510) disposed on the CSP (paragraphs 75-77); a sacrificial layer structure (290) disposed on the CSP, wherein the sacrificial layer structure is spaced apart from the channel connection pattern (paragraphs 43-44); a support pattern (305) disposed on the CSP, wherein the support pattern is interposed between the channel connection pattern and the sacrificial layer structure (paragraph 46); a support layer (300) disposed on the channel connection pattern and the sacrificial layer structure, wherein the support layer includes substantially a same material as that of the support pattern, and is connected to the support pattern (paragraph 46); first and second gate electrode structures each including gate electrodes (first and second gate electrode structures at least including 752, 754, and 756 in I and II) sequentially stacked on the support layer and spaced apart from each other in a first direction (D1) substantially perpendicular to an upper surface of the substrate (an upper surface of 100), wherein each of the gate electrodes extends in a second direction (D2/D3) substantially parallel to the upper surface of the substrate (paragraphs 102-103); a division pattern (620) extending in the second direction on the CSP through the support layer and the channel connection pattern, wherein the division pattern separates the first and second gate electrode structures from each other (paragraphs 104-105); a first memory channel structure (462) disposed on the CSP, wherein the first memory channel structure extends through the first gate electrode structure and the support layer and is connected to the channel connection pattern (paragraph 60); a second memory channel structure (688) disposed on the first memory channel structure (Fig. 32 and paragraph 114); a support structure (another 620) extending through the second gate electrode structure and the support pattern, and contacting an upper surface of the CSP (Fig. 30 and paragraph 104-105); and a contact plug (644/646) extending through the second gate electrode structure, the support layer, the sacrificial layer structure and the CSP, and is electrically connected to the lower circuit pattern (paragraph 106).
Regarding claim 19, Lee teaches wherein the support pattern overlaps the second gate electrode structure in the first direction (Fig. 29).
Regarding claim 20, Lee teaches wherein an upper surface of the first memory channel structure, an upper surface of the support structure and an upper surface of an isolation pattern (one of 620) are substantially coplanar with each other (Figs. 29-30).
Conclusion
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893