DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on October 13, 2023 and January 28, 2025 have been considered by the examiner. Examiner notes that the application file includes the international search report for PCT/JP2021/018321 submitted on October 13, 2023. However, this document was not included in the IDS submitted on October 13, 2023. Examiner notes that should applicant desire the PCT/JP2021/018321 international search report to be recorded as considered by the examiner, an additional IDS including the document should be provided.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "the synthesis by the synthesis circuit" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “a synthesis by the synthesis circuit” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Flemming et al. (Patent Publication Number US 2020/0212864 A1), as cited by applicant, hereafter referred to as Flemming, in view of Shinjo et al. (Patent Publication Number US 2019/0028062 A1), as cited by applicant, hereafter referred to as Shinjo.
Regarding claim 1, Flemming discloses:
A Doherty amplifier (Flemming, Fig. 9) comprising: a carrier amplifier (Fig. 9, see “Class AB Carrier Amplifier”) to amplify a first signal (Fig. 9, consider signal through “Class AB Carrier Amplifier”); a peak amplifier (Fig. 9, “Class C Peaking Amplifier”) to amplify a second signal (Fig. 9, consider signal through “Class C Peaking Amplifier”); and a synthesis circuit (Fig. 9, see “Impedance Inverter and 90 Deg Delay” and “Harmonic Rejection (Output Tank Circuit)”) to synthesize the first signal amplified by the carrier amplifier (Fig. 9, see connection between “Class AB Carrier Amplifier” and “Impedance Inverter and 90 Deg Delay”) and the second signal amplified by the peak amplifier (Fig. 9, see connection between “Class C Peaking Amplifier” and “Impedance Inverter and 90 Deg Delay”), wherein the synthesis circuit includes a bandpass filter circuit (Paragraph 48, lines 3-7) but fails to disclose [the synthesis circuit] that includes, as a capacitor, a parasitic capacitance at an output side of each of the carrier amplifier and the peak amplifier.
However, Shinjo teaches [the synthesis circuit] that includes, as a capacitor (Shinjo, Fig. 2, see capacitors), a parasitic capacitance at an output side of each of the carrier amplifier (Fig. 2, see capacitor of 1a) and the peak amplifier (Fig. 2, see capacitor of 2a).
Flemming and Shinjo are both considered to be analogous to the claimed invention because they are in the same field of improving Doherty amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art to modify Flemming to incorporate the teachings of Shinjo to include the parasitic capacitances of Shinjo in the circuit of Flemming, which would have the effect of improving the efficiency of the amplifier of Flemming (Paragraph 48, lines 17-24).
Regarding claim 2, Flemming further discloses:
further comprising a phase adjustment circuit (Flemming, Fig. 9, see “Quadrature Generator”) to delay a phase of the second signal and output the second signal after phase adjustment to the peak amplifier (Fig. 9, consider quadrature-phase output of “Quadrature Generator”), wherein the phase adjustment circuit includes a bandpass filter circuit (Paragraph 48, lines 3-12), and has a same pass phase characteristic as a pass phase characteristic of the synthesis circuit in an operating frequency band of the Doherty amplifier (Fig. 9, consider that a quadrature-phase signal has a 90 degree phase difference from the in-phase signal, and that the synthesis circuit provides a 90 degree phase delay).
Regarding claim 3, Flemming further discloses:
further comprising an output matching circuit (Flemming, Fig. 9, see “L-Match Impedance Transformer) to match an impedance of a signal after the synthesis by the synthesis circuit with an impedance of a load (Fig. 9, consider connection between “L-Match Impedance Transformer” and “Impedance Inverter and 90 Deg Delay”).
Regarding claim 4, Flemming further discloses:
further comprising: a distributor (Flemming, Fig. 9, see “Quadrature Generator”) to distribute electric power of an amplification target signal to two signals (Fig. 9, see connection between “Quadrature Generator” and “Class AB Carrier Amplifier” and “Class C Peaking Amplifier”), output one of the two signals after the power distribution as the first signal (Fig. 9, see connection between “Quadrature Generator” and “Class AB Carrier Amplifier”), and output the other one of the two signals after the power distribution as the second signal (Fig. 9, see connection between “Quadrature Generator” and “Class C Peaking Amplifier”); but fails to disclose a first input matching circuit to match an impedance of an input end of the carrier amplifier with an impedance at an input side of the distributor, the first input matching circuit being connected between the distributor and the carrier amplifier; and a second input matching circuit to match an impedance of an input end of the peak amplifier with the impedance at the input side of the distributor, the second input matching circuit being connected between the distributor and the peak amplifier.
However, Shinjo further teaches a first input matching circuit (Shinjo, Fig. 1, 1b) to match an impedance of an input end of the carrier amplifier with an impedance at an input side of the distributor (Paragraph 44, lines 1-5), the first input matching circuit being connected between the distributor and the carrier amplifier (Fig. 1, see connection between 3a and 1a via 1b); and a second input matching circuit (Shinjo, Fig. 1, 2b) to match an impedance of an input end of the peak amplifier with the impedance at the input side of the distributor (Paragraph 45, lines 1-5), the second input matching circuit being connected between the distributor and the peak amplifier (Fig. 1, see connection between 3a and 2a via 2b).
Flemming and Shinjo are both considered to be analogous to the claimed invention because they are in the same field of improving Doherty amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art to modify Flemming to incorporate the teachings of Shinjo to include the input matching circuits of Shinjo in the amplifier of Flemming, which would have the effect of providing appropriate impedance matching for the amplifier of Flemming (Shinjo, Paragraphs 44-45).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chan et al. (Patent Number US 11,043,920 B2) discloses (Fig. 7) a Doherty amplifier circuit including a bandpass filter.
Lv et al. (Patent Publication Number CN 111,586,896 A) discloses (Fig. 2C) an inductor-capacitor network for a Doherty amplifier.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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