Prosecution Insights
Last updated: July 17, 2026
Application No. 18/380,003

FAULT DETECTION METHOD AND FAULT SYMPTOM DIAGNOSIS SYSTEM AND METHOD FOR SOLENOID ACTUATORS

Non-Final OA §102§112
Filed
Oct 13, 2023
Priority
Apr 11, 2023 — RE 10-2023-0047218
Examiner
DESTA, ELIAS
Art Unit
2857
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
HL Mando Corporation
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
895 granted / 1066 resolved
+16.0% vs TC avg
Moderate +10% lift
Without
With
+9.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
29 currently pending
Career history
1100
Total Applications
across all art units

Statute-Specific Performance

§101
26.1%
-13.9% vs TC avg
§103
41.0%
+1.0% vs TC avg
§102
16.2%
-23.8% vs TC avg
§112
11.5%
-28.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1066 resolved cases

Office Action

§102 §112
Detailed Action Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Restriction/Election Applicant’s election without traverse of Group I, claims 1-8 in the reply filed on March 25, 2026 is acknowledged. Claims 9-14 (system) and claims 15-20 (method) are withdrawn from consideration. Claims 1-8 are pending in the application. Examination of Application IDS The information disclosure statement (IDS) submitted on November 12, 2024 is being considered by the Examiner. Drawing The drawing filed on October 13, 2023 is accepted by the Examiner. Specification The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim rejection – 35 U.S.C. 112 Claims 2-7 are rejected under 35 U.S.C. §112(b) or 35 U.S.C. §112 (pre-AIA ), second paragraph, as being indefinite: with regard to claims 2 and 3; the term B+ needs to be defined what it represents; with regard to claims 4-7, the term HSD either should be described as High-Side Driver or it should be included in the description in claim 1 as “High-side driver (HSD)” so that no need to have inconsistency throughout the instant claims. Claims 4-7 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The prior art considered in the prosecution of the instant application do not teach or disclose a method for “detecting, by the main controller, a second short monitoring measurement value of the short monitoring unit and a second high-side driver current measurement value of the high-side driver in a state where the high-side driver is turned on and the low-side driver is turned off; and comparing, by the main controller, the second short monitoring measurement value with a pre-stored short monitoring threshold value and comparing, by the main controller, the second high-side driver current measurement value with pre-stored high side driver current threshold value.” Claim rejection – 35 U.S.C. §102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3 and 8 are rejected under 35 U.S.C. §102(a)(2) as being anticipated by Lee et al. (U.S. Patent No. 11,183,835, hereon Lee). In reference to claim 1: Lee discloses a fault detection method for a solenoid actuator (see Lee, Fig. 1, control actuator, note that actuator or solenoid or electromagnet or coil are interchangeable) in a drive circuit (see Lee, Fig. 3A) of the solenoid actuator comprising a main controller (MCU, Microcontroller Unit), a high-side driver, a low-side driver (see Lee, Fig. 3A, high-side, and low-side driver, 11 and 12) and a short monitoring unit (see Lee, Fig. 3B, a schematic diagram of a short circuit detection circuit to be coupled to a gate driver circuit), the method comprising: detecting, by the main controller (MCU), a first short monitoring measurement value of the short monitoring unit in a state where at least one of the high-side driver and the low-side driver is turned off (see Lee, column 9, Table 1; input signal “High” means that the respective switching device 11 or 12 is turned on, while input signal “Low” means that the switching device 11 or 12 is turned off. This logic only considers the “turn on” status of the relevant switching devices and input control signals, as will be described in further detail. In addition, a blanking time may be inserted between the beginning of the turn-on control signal (i.e., high LIN and high HIN) and the point at which desaturation detection is activated at a logic analysis unit in order to avoid false detection); comparing, by the main controller, the first short monitoring measurement value with a pre-stored short monitoring threshold value (see Lee, column 11, lines 36-45); and determining, by the main controller, a fault of the solenoid actuator based on the comparison result (see Lee, column 11, lines 36-45, towards the end, “when Vout1 is lower than Vref1, the output comparator 43 is 1(i.e., logic high) which indicates possible fault (i.e., a possible short circuit event at high side of transistor switch 12”). With regard to claim 2: Lee further discloses that the determining, by the main controller (MCU), a fault of the solenoid actuator based on the comparison result comprises determining that there is a short fault between the solenoid actuator and a B+ line (see Lee, Fig. 3A, B+ line (terminal 36)) when the first short monitoring measurement value is higher than the short monitoring threshold value in a state where both the high-side driver and the low-side driver are turned off (low voltage state) (see Lee, column 9, lines 27-39). With regard to claim 3: Lee further discloses that the method comprising the steps of preventing, by the main controller, the solenoid actuator from being driven when it is determined that there is a short fault between the solenoid actuator and the B+ line (see Lee, column 10, lines 41-45). With regard to claim 8: Lee further discloses that the method comprising the steps of executing, by the main controller (MCU), a driving solenoid actuator or actuator fault detection logic in a state where both high-side driver and low-side driver are turned on because these states can be detected using a single function as noted in table I, including the high-side and the low-side being switched at high (turned on) to indicate abnormal or fault detection (see Lee, Table I). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Soriano (U.S. PAP 2023/0182752) discloses a method of diagnosing for fault conditions in an external device using an ECU. The method may include connecting the ECU to the abovementioned interface circuit, connecting the external device to the first connection circuit of the interface circuit, connecting the diagnostic sub-circuit of the interface circuit to a reference voltage, and setting the control signal to logic low to disconnect the external device from the power supply. Tomimbang et al. (U.S. Patent No. 9,978,553) discloses an apparatus, system and method for detection and interruption of a multitude of electrical faults and is hereinafter referred to as TPCI, which integrates multiple electrical circuit faults protection into one, utilizing common elements to have a unified circuit, apparatus or system performing all the different functions of otherwise a multitude of elements, circuit, systems and apparatus. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS DESTA whose telephone number is (571)272-2214. The examiner can normally be reached M-F: 8:30 to 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew M Schechter can be reached at 571-272-2302. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ELIAS DESTA/ Primary Examiner, Art Unit 2857
Read full office action

Prosecution Timeline

Oct 13, 2023
Application Filed
Apr 17, 2026
Non-Final Rejection mailed — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
94%
With Interview (+9.8%)
2y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1066 resolved cases by this examiner. Grant probability derived from career allowance rate.

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