DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election of claim(s) 1-10 in the reply filed on 1/19/2026 is acknowledged. Claim(s) 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method claim(s), there being no allowable generic or linking claim. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-6 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US publication 2022/0173108 A1), hereinafter referred to as Lee108.
Regarding claim 1, Lee108 teaches a memory device (fig. 7-8 and related text), comprising: a substrate (100, [0029]); a bit line contact opening (opening for 146/150 (151/152), [0090-0092], fig. 7), wherein the bit line contact opening is at least partially disposed in the substrate (fig. 7), and the bit line contact opening comprises: a first portion (opening for 152); a second portion (opening for 151) located under the first portion and connected with the first portion; and a third portion (opening for 146) located under the second portion and connected with the second portion (fig. 7); a bit line contact structure (146/150) disposed in the first portion, the second portion, and the third portion of the bit line contact opening (fig. 7); and a first spacer (152, [0092]) disposed in the first portion of the bit line contact opening and surrounding the bit line contact structure (fig. 7).
Regarding claim 2, Lee108 teaches wherein a width of the second portion is less than a width of the first portion (fig. 7).
Regarding claim 3, Lee108 teaches wherein a width of the third portion is less than a width of the first portion and/or a width of the second portion (fig. 7).
Regarding claim 4, Lee108 teaches further comprising: a word line (112, [0055], fig. 8) structure disposed in the substrate, wherein a part of the substrate is sandwiched between the bit line contact structure and the word line structure in a horizontal direction (fig. 8).
Regarding claim 5, Lee108 teaches wherein the first portion, the second portion, and the third portion of the bit line contact opening comprise a ladder-shaped structure at an inner wall of the bit line contact opening (fig. 7).
Regarding claim 6, Lee108 teaches further comprising: a second spacer (151) disposed in the bit line contact opening and surrounding the bit line contact structure, wherein the second spacer is partly disposed on the first spacer, at least a part of the second spacer is disposed in the second portion of the bit line contact opening, and a bottom surface of the second spacer is higher than a bottom surface of the third portion (fig. 7).
Regarding claim 10, Lee108 teaches wherein the bit line contact structure comprises a ladder-shaped structure (fig. 7).
Claim 1 and 7-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. (US publication 2021/0066304 A1), hereinafter referred to as Kang304.
Regarding claim 1, Kang304 teaches a memory device (fig. 2a and related text), comprising: a substrate (10, [0018]); a bit line contact opening (opening for 31/41/42/44 in S area, [0022-0025], fig. 2a), wherein the bit line contact opening is at least partially disposed in the substrate (fig. 2a), and the bit line contact opening comprises: a first portion (opening for 44); a second portion (opening for 40) located under the first portion and connected with the first portion; and a third portion (opening for 31) located under the second portion and connected with the second portion (fig. 2a); a bit line contact structure (31/41/42/44) disposed in the first portion, the second portion, and the third portion of the bit line contact opening (fig. 2a); and a first spacer (44, [0024]) disposed in the first portion of the bit line contact opening and surrounding the bit line contact structure (fig. 2a).
Regarding claim 7, Kang304 teaches wherein the bit line contact opening further comprises: a fourth portion (opening for 41) located under the third portion and connected with the third portion, wherein the bit line contact structure is further disposed in the fourth portion of the bit line contact opening (fig. 2a).
Regarding claim 8, Kang304 teaches wherein a width of the fourth portion is less than a width of the first portion, a width of the second portion, and/or a width of the third portion, and the first portion, the second portion, the third portion, and the fourth portion of the bit line contact opening comprise a ladder-shaped structure at an inner wall of the bit lint contact opening (fig. 2a).
Regarding claim 9, Kang304 teaches further comprising: a third spacer (40) disposed in the bit line contact opening and surrounding the bit line contact structure, wherein the third spacer is partly disposed on the first spacer, at least a part of the third spacer is disposed in the third portion of the bit line contact opening, and a bottom surface of the third spacer is higher than a bottom surface of the fourth portion (fig. 2a).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammed R Alam whose telephone number is 469-295-9205 and can normally be reached between 8:00am-6:00pm (M-F) or by e-mail via Mohammed.Alam1@uspto.gov.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED R ALAM/Primary Examiner, Art Unit 2897