FINAL OFFICE ACTION
Status of the Claims
Claims 1-20 are rejected under 35 U.S.C. 103
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 7-10, 12-15, 17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shelter, JR. et al (U.S. Publication No. 2003/0048006 A1), hereinafter referred to as Shelter, in view of Chellappan et al. (U.S. Publication No. 2017/0070381 A1), hereinafter referred to as Chellappan.
Regarding Claim 1, Shelter teaches:
A high-speed communication system for communicating one or more conditions between two or more controllers comprising:
a first controller including a first communications interface having a first physical layer interface circuit, the first controller configured to detect a condition and, in response to detecting the condition, to generate a link reset at the first physical layer interface circuit; ([0086]; regarding, “An event log is kept by the Comms DSP and is stored in nonvolatile memory. A copy of this log may be transferred to the Micro Monitor user interface for review and analysis.”; [0087]; regarding, “The history log also includes parameters collected for development purposes. Its data represents conditions before, during, and after a fault condition occurs”; [0085]; regarding, “The Comms DSP also services system level hardware watchdog timer. If the Comms DSP fails to update this watchdog timer within a specified period, the hardware watchdog timer will reset the control board and signal the bypass static switch control board”);
and the second controller operatively coupled to the first controller and including a second communications interface having a second physical layer interface circuit, the second controller configured to detect the link reset at the second physical layer interface circuit and, in response to detecting the link reset, output a signal indicating the detected condition. ([0025]; regarding, “The network interface 270 is implemented using any type of well-known network interface standard including, but not limited to, an Ethernet interface…”; [0080]; regarding, “Control board 15… interfaces with static switch driver 18 to control bypass switch 5.”; [0081]; regarding, “Control board 15 includes three digital signal processors ("DSPs") that perform all control computations for the UPS.”; [0075]; regarding, “The UPS system can automatically turn on the bypass switch if any abnormal conditions are detected”; [0094]; regarding, “The control board provides the necessary control signals…”).
Shelter fails to explicitly disclose but Chellappan teaches:
wherein the link reset resets a communications link between the first controller and a second controller; (Figs. 4-5, [0040]; regarding, “if physical layer state sensor 452, link-layer state sensor 462, or both detect a link error or another reason to deviate from normal operation, override controller 450 reconfigures physical layer input selector 457 to bypass link-layer component output 459, instead passing override controller output 469 to physical layer 406.”; [0111]; regarding, “…if the rmmi_reset value is one (Signal 839), as in a timed-out override, the override controller bypasses IDLE state 802 and restarts the interrupted override.”);
…in response to detecting the link reset, output a signal indicating the detected condition. ([0037]; regarding, “any suitable override activation stimulus, e.g., a signal going out of an acceptable range of amplitude, frequency, stability, or other measurable characteristic sensitive to link errors may be used to trigger the override process.”);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Shelter with the teachings of Chellappan. Doing so could provide early detection and quick recovery from errors on serial communication links (Chellappan, [0018]).
Regarding Claim 2, Shelter in view of Chellappan teaches the system of claim 1 as referenced above. Shelter in view of Chellappan further teaches:
wherein the second controller is further configured to confirm the link reset after a confirmation period and to take a corrective action in response to confirming the link reset. (Shelter, [0132]; regarding, “After a short actuation delay, the Cornms DSP checks the bypass contactor status signal…If the contactors did not close, a failure is indicated, a signal is sent to reopen the contactors… If the contactors successfully closed, a short delay is initiated, allowing the Comms DSP to test for abnormal bypass operation.”).
Regarding Claim 4, Shelter in view of Chellappan teaches the system of claim 1 as referenced above. Shelter in view of Chellappan further teaches:
wherein the first controller includes watchdog logic configured to detect the condition by reaching a timeout threshold. (Shelter, [0082]; regarding, “The Comms DSP also controls high level system functions, including monitoring, and communications. The Comms DSP also performs all metering functions and controls status and alarm signals.”; [0085]; regarding, “The Comms DSP also services system level hardware watchdog timer. If the Comms DSP fails to update this watchdog timer within a specified period, the hardware watchdog timer will reset the control board and signal the bypass static switch control board to transfer the load to bypass, thereby preventing critical load interruption.”).
Regarding Claim 7, Shelter in view of Chellappan teaches the system of claim 1 as referenced above. Shelter in view of Chellappan further teaches:
further comprising a bypass switch, wherein the bypass switch is controlled responsive to the signal indicating the detected condition. (Shelter, [0085]; regarding, “…If the Comms DSP fails to update this watchdog timer within a specified period, the hardware watchdog timer will reset the control board and signal the bypass static switch control board to transfer the load to bypass, thereby preventing critical load interruption.”).
Regarding Claim 8, Shelter in view of Chellappan teaches the system of claim 2 as referenced above. Shelter in view of Chellappan further teaches:
wherein the second controller is further configured to control a bypass switch to take the corrective action. (Shelter, [0080]; regarding, “Control board 15… interfaces with static switch driver 18 to control bypass switch 5.”; [0075]; regarding, “The UPS system can automatically turn on the bypass switch if any abnormal conditions are detected…The bypass switch can also be turned on and paralleled with the inverter to supplement power to the load in the event of a large transient overload. Furthermore, the bypass switch provides a means to connect an alternate source (bypass source) to the load thus allowing the inverter source to be isolated and disabled for servicing.”).
Claims 9-10 and 19-20 are rejected under 35 U.S.C. 103 under the same grounds of rejection as claims 1-2 respectively.
Claims 12-13, and 14-15 are rejected under 35 U.S.C. 103 under the same grounds of rejection as claims 7-8 respectively.
Claim 17 is rejected under 35 U.S.C. 103 under the same grounds of rejection as claim 4.
Claims 3, 11, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Shelter, JR. et al (U.S. Publication No. 2003/0048006 A1), hereinafter referred to as Shelter, in view of Chellappan et al. (U.S. Publication No. 2017/0070381 A1), hereinafter referred to as Chellappan, in further view of Alexander et al. (U.S. Publication No. 2010/0257398 A1), hereinafter referred to as Alexander.
Regarding Claim 3, Shelter in view of Chellappan teaches the system of claim 2 as referenced above. Shelter in view of Chellappan fails to explicitly disclose but Alexander teaches:
wherein the confirmation period is about 500 microseconds or less. ([0063]; regarding, “the memory controller coupled with the PLL 410 counts down six microseconds after the enable signal 450 is asserted”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Shelter and Chellappan with the teachings of Alexander. Doing so could reduce the power consumption of the memory register. (Alexander, [0035]).
Claims 11 and 16 are rejected under 35 U.S.C. 103 under the same grounds of rejection as claim 3.
Claims 5-6, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Shelter, JR. et al (U.S. Publication No. 2003/0048006 A1), hereinafter referred to as Shelter, in view of Chellappan et al. (U.S. Publication No. 2017/0070381 A1), hereinafter referred to as Chellappan, in further view of Humphrey et al. (U.S. Publication No. 2020/0127463 A1), hereinafter referred to as Humphrey.
Regarding Claim 5, Shelter in view of Chellappan teaches the system of claim 4 as referenced above. Shelter in view of Chellappan fails to explicitly disclose while Humphrey teaches:
wherein the timeout threshold is about 500 microseconds or less. ([0048]; regarding, “the first interval of the timer 222 may be 200 microseconds”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Shelter and Chellappan with the teachings of Humphrey. Doing so could ensure sufficient power is provided to the loads (Humphrey, [0015]).
Regarding Claim 6, Shelter in view of Chellappan teaches the system of claim 1 as referenced above. Shelter in view of Chellappan fails to explicitly disclose while Humphrey teaches:
wherein the first controller includes a field programmable gate array, and wherein the first physical layer interface circuit is coupled to the field programmable gate array by a media independent interface. ([0037]; regarding, “The auxiliary controller 212 may include a communications interface 302 communicatively coupled to the other power supplies 104 and one or more processors 304 (one shown).”; [0060]; regarding, “a “processor” may include any circuitry that is capable of executing machine-readable instructions, such as…digital signal processors (DSPs), field-programmable gate arrays (FPGAs…”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Shelter and Chellappan with the teachings of Humphrey. Doing so could ensure sufficient power is provided to the loads (Humphrey, [0015]).
Claim 18 is rejected under 35 U.S.C. 103 under the same grounds of rejection as claim 5.
Response to Arguments
Applicant’s arguments filed 02/13/2026 have been fully considered.
Applicant’s arguments with respect to the previous rejection on independent Claim 1,
and similarly Claims 9 and 14, have been considered and a new grounds of rejection has been provided addressing the newly claimed matter. Please see the above detailed rejection of the newly recited subject matter.
Newly cited reference Chellappan in combination with Shelter teach wherein the link reset resets a communications link between the first controller and a second controller… output a signal indicating the detected condition
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/M.D.G./Examiner, Art Unit 2113
/BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113
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