Detailed Action
This action is in response to the application filed on 08/14/2026. Claims 1-17 and 19-21 are pending and have been fully examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-17 and 19-21 are rejected under 35 U.S.C. 103
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 7-10, 12-15, 17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (U.S. Patent No. 9,904,651 B2), hereinafter referred to as Park, in view of Shelter, JR. et al (U.S. Publication No. 2003/0048006 A1), hereinafter referred to as Shelter.
Regarding Claim 1, Park teaches:
A high-speed communication system for communicating one or more conditions between two or more controllers comprising:
a first controller including a first communications interface having a first physical layer interface circuit, (Fig. 1);
and, in response to detecting the condition, control the first physical layer interface circuit to generate a link reset at the first physical layer interface circuit, (Col. 29, lines 40-45; regarding, “The interface circuit 223 may exchange control signals CTL with the host 210. For instance, the control signals CTL may include a power signal, a clock signal, and a reset signal.”)
wherein the link reset resets a communications link between the first controller and a second controller; (Col. 29, lines 39-45; regarding, “The interface circuit 223 may operate in compliance with the interface protocol using the physical layer PL and the link layer LL…The interface circuit 223 may exchange control signals CTL with the host 210. For instance, the control signals CTL may include a power signal, a clock signal, and a reset signal.”)
and the second controller operatively coupled to the first controller and including a second communications interface having a second physical layer interface circuit, (Fig. 1);
the second controller configured to detect the link reset as a link down condition at the second physical layer interface circuit (Col. 30, lines 63-67; regarding, “restoration of the linkup state may be performed when a reconnection of the host 210 to the interface circuit 223 is sensed after the host 210 and the storage device 220 are disconnected, or when an error associated with the set linkup state is detected.”);
and, in response to detecting the link down condition, output a signal indicating the detected condition. (Col. 25, lines 56-60; regarding, “the second electronic device 120 may provide a response signal RSP corresponding to the identification code ID_CODE”).
Park fails to explicitly disclose but Shelter teaches:
the first controller configured to detect a condition (Shelter, [0086]; regarding, “An event log is kept by the Comms DSP and is stored in nonvolatile memory. A copy of this log may be transferred to the Micro Monitor user interface for review and analysis.”; [0087]; regarding, “The history log also includes parameters collected for development purposes. Its data represents conditions before, during, and after a fault condition occurs”);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Shelter with the teachings of Chellappan. Doing so could provide a reduced number of components that are subject to failure (Shelter, [0068]).
Regarding Claim 2, Park in view of Shelter teaches the system of claim 1 as referenced above. Park in view of Shelter further teaches:
wherein the second controller is further configured to confirm the link reset after a confirmation period and to take a corrective action in response to confirming the link reset. (Shelter, [0132]; regarding, “After a short actuation delay, the Cornms DSP checks the bypass contactor status signal…If the contactors did not close, a failure is indicated, a signal is sent to reopen the contactors… If the contactors successfully closed, a short delay is initiated, allowing the Comms DSP to test for abnormal bypass operation.”).
Regarding Claim 4, Park in view of Shelter teaches the system of claim 1 as referenced above. Park in view of Shelter further teaches:
wherein the first controller includes watchdog logic configured to detect the condition by reaching a timeout threshold. (Shelter, [0082]; regarding, “The Comms DSP also controls high level system functions, including monitoring, and communications. The Comms DSP also performs all metering functions and controls status and alarm signals.”; [0085]; regarding, “The Comms DSP also services system level hardware watchdog timer. If the Comms DSP fails to update this watchdog timer within a specified period, the hardware watchdog timer will reset the control board and signal the bypass static switch control board to transfer the load to bypass, thereby preventing critical load interruption.”).
Regarding Claim 7, Park in view of Shelter teaches the system of claim 1 as referenced above. Park in view of Shelter further teaches:
further comprising a bypass switch, wherein the bypass switch is controlled responsive to the signal indicating the detected condition. (Shelter, [0085]; regarding, “…If the Comms DSP fails to update this watchdog timer within a specified period, the hardware watchdog timer will reset the control board and signal the bypass static switch control board to transfer the load to bypass, thereby preventing critical load interruption.”).
Regarding Claim 8, Park in view of Shelter teaches the system of claim 2 as referenced above. Park in view of Shelter further teaches:
wherein the second controller is further configured to control a bypass switch to take the corrective action. (Shelter, [0080]; regarding, “Control board 15… interfaces with static switch driver 18 to control bypass switch 5.”; [0075]; regarding, “The UPS system can automatically turn on the bypass switch if any abnormal conditions are detected…The bypass switch can also be turned on and paralleled with the inverter to supplement power to the load in the event of a large transient overload. Furthermore, the bypass switch provides a means to connect an alternate source (bypass source) to the load thus allowing the inverter source to be isolated and disabled for servicing.”).
Claims 9-10 and 19-20 are rejected under 35 U.S.C. 103 under the same grounds of rejection as claims 1-2 respectively.
Claims 12-13, and 14-15 are rejected under 35 U.S.C. 103 under the same grounds of rejection as claims 7-8 respectively.
Claim 17 is rejected under 35 U.S.C. 103 under the same grounds of rejection as claim 4.
Claims 3, 11, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (U.S. Patent No. 9,904,651 B2), hereinafter referred to as Park, in view of Shelter, JR. et al (U.S. Publication No. 2003/0048006 A1), hereinafter referred to as Shelter, in further view of Alexander et al. (U.S. Publication No. 2010/0257398 A1), hereinafter referred to as Alexander.
Regarding Claim 3, Park in view of Shelter teaches the system of claim 2 as referenced above. Park in view of Shelter fails to explicitly disclose but Alexander teaches:
wherein the confirmation period is about 500 microseconds or less. ([0063]; regarding, “the memory controller coupled with the PLL 410 counts down six microseconds after the enable signal 450 is asserted”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Park and Shelter with the teachings of Alexander. Doing so could reduce the power consumption of the memory register. (Alexander, [0035]).
Claims 11 and 16 are rejected under 35 U.S.C. 103 under the same grounds of rejection as claim 3.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (U.S. Patent No. 9,904,651 B2), hereinafter referred to as Park, in view of Shelter, JR. et al (U.S. Publication No. 2003/0048006 A1), hereinafter referred to as Shelter, in further view of Humphrey et al. (U.S. Publication No. 2020/0127463 A1), hereinafter referred to as Humphrey.
Regarding Claim 5, Park in view of Shelter teaches the system of claim 4 as referenced above. Park in view of Shelter fails to explicitly disclose while Humphrey teaches:
wherein the timeout threshold is about 500 microseconds or less. ([0048]; regarding, “the first interval of the timer 222 may be 200 microseconds”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Shelter and Chellappan with the teachings of Humphrey. Doing so could ensure sufficient power is provided to the loads (Humphrey, [0015]).
Regarding Claim 6, Park in view of Shelter teaches the system of claim 1 as referenced above. Park in view of Shelter fails to explicitly disclose while Humphrey teaches:
wherein the first controller includes a field programmable gate array, and wherein the first physical layer interface circuit is coupled to the field programmable gate array by a media independent interface. ([0037]; regarding, “The auxiliary controller 212 may include a communications interface 302 communicatively coupled to the other power supplies 104 and one or more processors 304 (one shown).”; [0060]; regarding, “a “processor” may include any circuitry that is capable of executing machine-readable instructions, such as…digital signal processors (DSPs), field-programmable gate arrays (FPGAs…”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Park and Shelter with the teachings of Humphrey. Doing so could ensure sufficient power is provided to the loads (Humphrey, [0015]).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al (U.S. Patent No. 9,904,651 B2), hereinafter referred to as Park, in view of Shelter, JR. et al (U.S. Publication No. 2003/0048006 A1), hereinafter referred to as Shelter, in further view of Aithal et al. (U.S. Patent No. 9,544,181 B1), hereinafter referred to as Aithal.
Regarding Claim 21, Park in view of Shelter teaches the system of claim 1 as referenced above. Park in view of Shelter fails to explicitly disclose while Humphrey teaches:
wherein the communications link comprises an Ethernet-based communications link and wherein the first physical layer interface circuit comprises a first Ethernet physical layer chip and wherein the second physical layer interface circuit comprises a second Ethernet physical layer chip. (Col. 6, lines 49-60; regarding, “the traffic processor 308 processes Ethernet traffic that is received over an Ethernet communication link through an Ethernet communication interface 304 for transmission over a wireless communication link through the wireless interface 312, and also processes communication traffic that is received over the wireless communication link for transmission over the Ethernet communication link.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Park and Shelter with the teachings of Aithal. Doing so could enhance the user experience (Aithal, Col. 23, lines 63-66).
Response to Arguments
Applicant’s arguments filed 08/14/2026 have been fully considered.
Applicant’s arguments with respect to the previous rejection on independent Claim 1,
and similarly Claims 9 and 14, have been considered and a new grounds of rejection has been provided addressing the newly claimed matter. Please see the above detailed rejection of the newly recited subject matter.
Park in view of Shelter teaches the claimed response when detecting a condition.
Conclusion
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/M.D.G./Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113
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