DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-10 and 20) in the reply filed on 06/11/2026 is acknowledged.
Claims 11-19 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/11/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 9, claim 9 recites “dielectric layers”. However, as “dielectric layers” is not proceeded by “the” or “a”, it is unclear whether the “dielectric layers” recited in claim 9 are the same or different structures from the “dielectric layers” recited in claim 2. Appropriate correction is required to clarify the language. For purposes of compact prosecution the Examiner interprets the dielectric layers of claim 9 to be the same structure as the dielectric layers recited in claim 2.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-6 and 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Wada et al. (US 2010/0213526) hereinafter “Wada”.
Regarding claim 1, Figs. 3 and 39 of Wada teach a semiconductor structure, comprising: a stack structure comprising a first region, a second region, and a boundary region between the first region and the second region (See Picture 1 below), wherein the stack structure comprises gate layers (Items 31) and insulation layers (Items 32) that are stacked alternately, and the gate layers include a first gate layer (Item 31d) and a plurality of second gate layers (Items 31a-31c) on a side (bottom side) of the first gate layer (Item 31d); a first contact structure (Item 55b’) in the boundary region (See Picture 1 below), extending and connected to the first gate layer (Item 31d); and a plurality of second contact structures (Items 55c’-55e’) in the second region (See Picture 1 below), extending and connected to the plurality second gate layers (Items 31a-31c) of different layers respectively, wherein a size of the first contact structure in a direction perpendicular to a stacking direction of the stack structure is different from sizes of the second contact structures in the direction perpendicular to the stacking direction.
PNG
media_image1.png
489
710
media_image1.png
Greyscale
Picture 1 (Labeled version of Wada Fig. 3)
Regarding claim 3, Fig. 39 of Wada further teaches a plurality of channel structures (Item 37) penetrating through the stack structure of the first region (See Picture 1 above); and a plurality of third contact structures (Item 54’) in the first region, extending and connected to different ones of the channel structures respectively, wherein cross-sectional shapes (trapezoid) of the first contact structure (Item 55b) and the third contact structures (Items 54’) in a plane perpendicular to the stacking direction are the same (See Examiner’s Note below).
Examiner’s Note: The Examiner notes that the claim merely requires that the shapes of the first and third contacts are the same and does not require that the size is the same.
Regarding claim 4, Figs. 5 and 39 of Wada further teaches a select gate (Item 41) on the first gate layer (Item 31d); and a fourth contact structure (Item 55a) in the first region (See Picture 1 above), extending and connected to the select gate layer (Item 41), wherein cross sectional shapes (trapezoids) of the first contact structure and the fourth contact structure in the plane perpendicular to the stacking direction are the same (See Examiner’s Note below).
Examiner’s Note: The Examiner notes that the claim merely requires that the shapes of the first and third contacts are the same and does not require that the size is the same.
Regarding claim 5, Figs. 5 and 39 of Wada further teach where a top face of the first contact structure (Item 55b’) is substantially flush with a top face of at least one of the third contact structure (Item 54’) or the fourth contact structure (Item 55a).
Regarding claim 6, Fig. 39 of Wada further teaches where the size of the first contact structure (Item 55b’) in the direction perpendicular to the stacking direction is less than the sizes of the second contact structures (Items 55c’-55e’) in the direction perpendicular to the stacking direction.
Regarding claim 20, Figs. 3 and 39 of Wada teach a memory system (Paragraph 0002), comprising: a semiconductor structure comprising: a stack structure comprising a first region, a second region, and a boundary region between the first region and the second region (See Picture 1 below), wherein the stack structure comprises gate layers (Items 31) and insulation layers (Items 32) that are stacked alternately, and the gate layers include a first gate layer (Item 31d) and a plurality of second gate layers (Items 31a-31c) on a side (bottom side) of the first gate layer (Item 31d); a first contact structure (Item 55b’) in the boundary region (See Picture 1 below), extending and connected to the first gate layer (Item 31d); and a plurality of second contact structures (Items 55c’-55e’) in the second region (See Picture 1 below), extending and connected to the plurality second gate layers (Items 31a-31c) of different layers respectively, wherein a size of the first contact structure in a direction perpendicular to a stacking direction of the stack structure is different from sizes of the second contact structures in the direction perpendicular to the stacking direction, and a controller connected with the semiconductor structure (Item 38; Paragraph 0027).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Wada et al. (US 2010/0213526) hereinafter “Wada” in view of Lu et al. (US 2019/0043879) hereinafter “Lu”.
Regarding claim 2, Wada teaches all of the elements of the claimed invention as stated above.
Wada further teaches a periphery of positions where the first contact structure (Item 55b’) is located corresponds to the gate layers (Items 31) and the insulation layers (Items 32) that are stacked alternately and a part of peripheries of positions where the second contact structures (Items 55c’-55e’) are located corresponds to the gate layers (Items 31) and the insulation layers (Items 32) that are stacked alternately.
Wada does not explicitly teach dielectric layers are further disposed on planes where corresponding gate layers of the stack structure of the second region are located and the other part corresponds to the dielectric layers and the insulation layers that are stacked alternately.
Fig. 5 of Lu teaches a memory structure having a section where contacts are present over a stack structure (Combination of Items 580A and 580B) and where other parts correspond to sections where dielectric layers (Item 560A), further disposed on planes where corresponding gate layers (Items 580A) of the stack structure are located, are alternated with the insulation layers (Items 580B).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have dielectric layers are further disposed on planes where corresponding gate layers of the stack structure of the second region are located and the other part corresponds to the dielectric layers and the insulation layers that are stacked alternately because the insulation/dielectric alternating stack electrically isolates structures carrying electrical signals through the device from other electrical structures in the device (Lu Paragraph 0118).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Wada et al. (US 2010/0213526) hereinafter “Wada” in view of Lu et al. (US 2019/0043879) hereinafter “Lu” and in further view of Kang et al. (US 2024/0324205) hereinafter “Kang”.
Regarding claim 7, the combination of Wada and Lu teaches all of the elements of the claimed invention as stated above.
Wada does not teach where a plurality of first gate line slit structures and a second gate line slit structure between two adjacent ones of the first gate line slit structures, the first gate line slit structures extending from the first region to the second region, and the second gate line slit structure extending from the first region to the boundary region, wherein the first contact structure is located on an extension line of a straight line where the second gate line slit structure is located, and wherein the first contact structure is located at proximate to an end of the second gate line slit structure.
Fig. 5 of Kang teaches where a plurality of first gate line slit structures (Left and right Items WDS) and a second gate line slit structure (Middle Item WDS) between two adjacent ones of the first gate line slit structures (Left and right Items WDS), the first gate line slit structures extending from the first region to the second region (Where ITEM WDS extends along the entire structure and traverses all of the regions), and the second gate line slit structure (Middle Item WDS) extending from the first region to a boundary region, wherein a first contact structure (Item BC over Item MCS) is located on an extension line of a straight line where the second gate line slit structure (Middle Item WDS) is located, and wherein the first contact structure (Item BC over Item MCS) is located at proximate (See Picture 2 below) to an end of the second gate line slit structure.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a plurality of first gate line slit structures and a second gate line slit structure between two adjacent ones of the first gate line slit structures, the first gate line slit structures extending from the first region to the second region, and the second gate line slit structure extending from the first region to the boundary region, wherein the first contact structure is located on an extension line of a straight line where the second gate line slit structure is located, and wherein the first contact structure is located at proximate to an end of the second gate line slit structure because this forms structures that separate and electrically isolate portions of the device from other portions of the device (Kang Paragraph 0066).
PNG
media_image2.png
403
699
media_image2.png
Greyscale
Picture 2 (Labeled version of Kang Fig. 5)
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Wada et al. (US 2010/0213526) hereinafter “Wada” in view of Lu et al. (US 2019/0043879) hereinafter “Lu” and Kang et al. (US 2024/0324205) hereinafter “Kang” and in further view of “Tsutsumi et al. (US 2025/0024676) hereinafter “Tsutsumi”.
Regarding claim 8, the combination of Wada, Lu, and Kang teaches all of the elements of the claimed invention as stated above except where the corresponding dielectric layer of the stack structure in the second region is located between two adjacent ones of the first gate line slit structures, and the corresponding gate layers of the stack structure in the second region are each located between the dielectric layer and a respective first gate line slit structure, the second contact structure is located between the extension line of the straight line where the second gate line slit is located and two of the first gate line slit structures, part of the second contact structure between the extension line and one of the first gate line slit structures and the other part of the second contact structure between the extension line and the other one of the first gate line slit structures are in juxtaposition and in a staggered arrangement, and a side of the second contact structure close to the first gate line slit structure is connected with the respective second gate layer.
Figs. 19A and 19B of Tsutsumi teach where contacts (Items 96) are connected with respective gate lines (Items 46) and contacts (Items 96) are in juxtaposition and in a staggered arrangement.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have part of the second contact structure in juxtaposition and in a staggered arrangement, and a side of the second contact structure be connected with the respective second gate layer because this allows the respective gate layers in the stacks to be electrically connected to bit line level gate lines which supply power to the gates (Tsutsumi Paragraph 0144).
When the structure of Kang which includes the first and second gate line slit structures and the structure of Lu which includes the stacked dielectric/insulation layers are incorporated into the structure taught by the combination of Wada and Tsutsumi the corresponding dielectric layer of the stack structure in the second region will be located between two adjacent ones of the first gate line slit structures, and the corresponding gate layers of the stack structure in the second region are each located between the dielectric layer and a respective first gate line slit structure, the second contact structure is located between the extension line of the straight line where the second gate line slit is located and two of the first gate line slit structures, part of the second contact structure between the extension line and one of the first gate line slit structures and the other part of the second contact structure between the extension line and the other one of the first gate line slit structures are in juxtaposition and in a staggered arrangement, and a side of the second contact structure close to the first gate line slit structure will be connected with the respective second gate layer.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Wada et al. (US 2010/0213526) hereinafter “Wada” in view of Lu et al. (US 2019/0043879) hereinafter “Lu”, Kang et al. (US 2024/0324205) hereinafter “Kang” and Tsutsumi et al. (US 2025/0024676) hereinafter “Tsutsumi” and in further view of Hong et al. (US 2024/0260270) hereinafter “Hong”.
Regarding claim 9, the combination of Wada, Lu, Kang and Tsutsumi teaches all of the elements of the claimed invention as stated above.
Wada does not teach dielectric layers are further disposed on planes where the corresponding gate layers of the stack structure of the boundary region are located, and the gate layer and the dielectric layer located between the first gate line slit structure and the second gate line slit structure in the boundary region have an interface, and the interface is located between the first contact structure and the second region.
Fig. 5 of Lu teaches a memory structure where dielectric layers (Item 560A) are further disposed on planes where corresponding gate layers (Items 580A) of the stack structure of a boundary region are located.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have dielectric layers are further disposed on planes where corresponding gate layers of the stack structure of the second region are located and the other part corresponds to the dielectric layers and the insulation layers that are stacked alternately because the insulation/dielectric alternating stack electrically isolates structures carrying electrical signals through the device from other electrical structures in the device (Lu Paragraph 0118).
When the features of Lu, Kang and Tsutsumi are incorporated into the structure of Wada as stated above, the gate layer and the dielectric layer will be located between the first gate line slit structure and the second gate line slit structure in the boundary region which will have an interface, and the interface will be located between the first contact structure and the second region.
Wada does not teach where the semiconductor structure further comprises at least one dummy channel structure.
Fig. 3A of Hong teaches where a dummy channel is present between respective channel structures (Paragraph 0073).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a dummy channel because the at least one dummy channel helps to isolate or separate the active channel structures from each other (Hong Paragraph 0076).
Wada does not teach where the dummy channel structure is located on the extension line of the straight line along which the second gate line slit extends and is located on at least one side of the first contact structure.
However, when the structure of Kang, having the first contact proximate to an end of the second gate line slit is incorporated into Wada, and the teaching in Hong is applied, the dummy channel structure will be located on the extension line of the straight line along which the second gate line slit extends and will be located on at least one side of the first contact structure.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wada et al. (US 2010/0213526) hereinafter “Wada” in view of Kang et al. (US 2024/0324205) hereinafter “Kang”.
Regarding claim 10, Wada teaches all of the elements of the claimed invention as stated above.
Wada further teaches the first contact structure (Item 55b’) extends to the first gate layer (Item 31d) along the stacking direction of the stack structure.
Wada does not teach where each of the second contact structures comprises a lead-out portion and a connection portion, wherein the lead-out portion extends in a direction parallel to the stacking direction of the stack structure, and one end of the lead-out portion is connected with part of a top face of the connection portion, and the connection portion extends along a direction perpendicular to the stacking direction and is connected to a corresponding second gate layer.
Figs. 6 and 7 of Kang teaches where each of the contact structures (Item 331) comprises a lead-out portion (Item 331_P) and a connection portion (Item 331_E), wherein the lead-out portion extends in a direction parallel to the stacking direction of the stack structure, and one end of the lead-out portion is connected with part of a top face of the connection portion, and the connection portion extends along a direction perpendicular to the stacking direction and is connected to a corresponding gate layer (Item SEL).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have each of the second contact structures comprises a lead-out portion and a connection portion, wherein the lead-out portion extends in a direction parallel to the stacking direction of the stack structure, and one end of the lead-out portion is connected with part of a top face of the connection portion, and the connection portion extends along a direction perpendicular to the stacking direction and is connected to a corresponding second gate layer because this allows for good contact between the second contact structure and the second gate layer (Kang Paragraph 0081).
Examiner’s Note: The Examiner notes that the claim language does not require that the lead-out portion directly contact a side surface, that is between the top and bottom surfaces, of the gate layer. As such, the lead-out portion contacting the top surface of the gate layer is sufficient to read on the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891
Prosecution Insights