DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Sharma et al. (US 2020/0091156) hereinafter “Sharma”.
Regarding claim 1, Fig. 4B of Sharma teaches A semiconductor device, comprising: a stack structure comprising conductor layers (Items M6 and M9) and dielectric layers (Items 452) stacked alternately along a first direction (Left to right); and at least one semiconductor structure penetrating through the stack structure, wherein the semiconductor structure comprising: a capacitor structure (Item 232), a first transistor structure (Item 220), and a second transistor structure (Item 210) extending in the stack structure along the first direction, wherein: the second transistor structure, the first transistor structure, and the capacitor structure in a same semiconductor structure are arranged and connected sequentially (See Examiner’s Note) along the first direction; and a terminal of the second transistor structure (Item 210) is in direct contact with the first transistor structure (Item 220), and another terminal of the second transistor structure (Item 210) is connected with a bit line (Item WBL1).
Examiner’s Note: The Examiner notes that the claim does not require that the sequence of the first transistor, the second transistor and the capacitor be in any particular order, just that they are sequential in a stacked direction.
Regarding claim 18, Fig. 4B of Sharma teaches a method of fabricating a semiconductor device, comprising: forming a stack structure comprising conductor layers (Items M4 and M9) and dielectric layers (Items 452) stacked alternately; and forming at least one semiconductor structure penetrating through the stack structure, wherein the semiconductor structure comprises a capacitor structure (Item 232), a first transistor structure (Item 220), and a second transistor structure (Item 220) that extend in the stack structure along a first direction (Left to right across the page), and a terminal of the second transistor structure (Item 210) is in direct contact with the first transistor structure (Item 220), wherein the second transistor structure (Item 210), the first transistor structure (Item 220), and the capacitor structure (Item 232) in a same semiconductor structure are arranged and connected sequentially (See Examiner’s Note below) along the first direction.
Examiner’s Note: The Examiner notes that the claim does not require that the sequence of the first transistor, the second transistor and the capacitor be in any particular order, just that they are sequential in a stacked direction.
Regarding claim 20, Fig. 4B of Sharma teaches a memory system, comprising: a three dimensional memory, comprising: a stack structure comprising conductor layers (Items M6 and M9) and dielectric layers (Items 452) stacked alternately along a first direction (Left to right); and at least one semiconductor structure penetrating through the stack structure, wherein the semiconductor structure comprising: a capacitor structure (Item 232), a first transistor structure (Item 220), and a second transistor structure (Item 210) extending in the stack structure along the first direction, wherein: the second transistor structure, the first transistor structure, and the capacitor structure in a same semiconductor structure are arranged and connected sequentially (See Examiner’s Note) along the first direction; and a terminal of the second transistor structure (Item 210) is in direct contact with the first transistor structure (Item 220), and another terminal of the second transistor structure (Item 210) is connected with a bit line (Item WBL1); and a controller (Paragraph 0028) coupled to the three dimensional memory and configured to control the three dimensional memory to store data.
Examiner’s Note: The Examiner notes that the claim does not require that the sequence of the first transistor, the second transistor and the capacitor be in any particular order, just that they are sequential in a stacked direction.
Allowable Subject Matter
Claims 2-17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the prior art does teach, suggest or motivate one having ordinary skill in the art to have the capacitor structure comprise a plurality of memory capacitors that are arranged spaced apart along the first direction. along with claim 1 from which claim 2 depends.
Claims 3-17 are also indicated as including allowable subject matter as they depend from and include all of the limitations of claim 2.
Regarding claim 19, the prior art does teach, suggest or motivate one having ordinary skill in the art to have forming the at least one semiconductor structure penetrating through the stack structure comprises: forming the capacitor structure extending along the first direction in the stack structure; forming the first transistor structure extending along the first direction and in contact and connected with a first face of the capacitor structure along the first direction in the stack structure; and forming the second transistor structure extending along the first direction and in contact and connected with a face of the first transistor structure away from the capacitor structure along the first direction in the stack structure along with claim 18 from which claim 19 depends.
Response to Arguments
Applicant’s arguments, see Applicant’s Remarks, filed 02/26/2026, with respect to the rejection(s) of claim(s) 1, 18 and 20 under 35 USC 102(a)(1) and 102(a)(2) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Sharma.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891
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