DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over [Schindler (Fig. 1); 5,208,547] in view of [Bakalski et al (Fig. 5a); 2014/0011461].
Regarding claim 1, Schindler discloses an amplifier circuit comprising a MOS transistor (FET1), and a feedback (16a) connected between input (gate terminal of FET1) and output (drain terminal of FET1) of the MOS transistor (FET1). As described above, Schindler discloses all the limitations in claim 1 except for that the feedback being a T reactance network and the amplifier core has two gain peaks spaced apart from each other. Bakalski et al discloses an amplifier circuit comprising a T reactance network (Fig. 5a) and the amplifier core has two gain peaks (gain peak of left capacitor C1, gain peak of right capacitor C1) spaced apart from each other. Therefore, it would have been obvious to substitute Bakalski et al’s T network (Fig. 5a of Bakalski et al) in place of Schindler’s feedback (16a in Fig. 1 of Schindler) since Schindler discloses a generic feedback thereby suggesting that any equivalent feedback T network would have been usable in Schindler’s reference.
Regarding claims 2 and 8, wherein a two port network is formed a gate (gate terminal of FET1) of the MOS transistor (FET1) and a source (source terminal of FET1) of the MOS transistor (FET1) respectively are ports on a primary side, and a drain (drain terminal of FET1) of the MOS transistor (FET1) and a source (source terminal of FET1) of the MOS transistor (FET1) respectively are ports on a secondary side.
Regarding claims 3 and 9, wherein the T reactance network comprises a first capacitor (left C1 in Fig. 5a of Bakalski et al) having a first electrode (left terminal of left capacitor C1) connected to the input (gate terminal of FET1) of the MOS transistor (FET1) and have a second electrode (right terminal of left capacitor C1) connected to a central node (the node between the elements left C1 and L1), a second capacitor (right capacitor C1) having a first electrode (right terminal of right capacitor C1) connected to the output (drain terminal of FET1) of the MOS transistor (FET1) and having a second electrode (left terminal of left capacitor C1) connected to the central node (the node between the elements left C1 and L1), and an inductor (L1) having a first electrode (upper terminal of L1) connected to the central node (the node between the elements left C1 and L1) and having a second electrode (lower terminal of L1) connected to a reference voltage (ground).
Regarding claim 4, wherein the MOS transistor (FET1) is an NMOS transistor.
Regarding claim 5, wherein the amplifier core (FET1, T network) has wideband gain characteristics between the two gain peaks (gain peak of left capacitor C1, gain peak of right capacitor C1).
Regarding claim 6, wherein the amplifier core (FET1, T network) operates losslessly, linearly and reciprocally.
Regarding claim 7, Schindler discloses an amplifier circuit comprising a MOS transistor (FET1), a feedback (16a) connected between input (gate terminal of FET1) and output (drain terminal of FET1) of the MOS transistor (FET1), unit amplifiers (FET1, 16a, FET2, 16b, FET3, 16c), and an impedance matching circuit (14) which is configured to connect the unit amplifiers (FET1, 16a, FET2, 16b, FET3, 16c) to each other. As described above, Schindler discloses all the limitations in claim 7 except for that the feedback being a T reactance network and the amplifier core has two gain peaks spaced apart from each other. Bakalski et al discloses an amplifier circuit comprising a T reactance network (Fig. 5a) and the amplifier core has two gain peaks (gain peak of left capacitor C1, gain peak of right capacitor C1) spaced apart from each other. Therefore, it would have been obvious to substitute Bakalski et al’s T network (Fig. 5a of Bakalski et al) in place of Schindler’s feedbacks (16a and 16b and 16c in Fig. 1 of Schindler) since Schindler discloses generic feedbacks thereby suggesting that any equivalent feedback T network would have been usable in Schindler’s reference.
Regarding claim 11, wherein each of the unit amplifier (FET1, 16a) has wideband gain characteristics, and the amplifier (Fig. 1 of Schindler) has wideband gain characteristics in a band comprising bands (bands of FET1, 16a) of the unit amplifiers (FET1, 16a, FET2, 16b, FET3, 16c).
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over [Schindler (Fig. 1); 5,208,547] in view of [Bakalski et al (Fig. 5a); 2014/0011461] in further view of [Groiss (Fig. 7); 7,375,576].
Schindler in view of Bakalski et al discloses all the limitations in claim 10 except for that each of the unit amplifier and two amplifier cores form a differential pair. Groiss discloses a differential amplifier circuit comprising a unit amplifier (414, 416, 420) and two amplifier cores (TD1, TD2) form a differential pair. It would have been obvious to substitute Groiss’s two amplifier core (TD1 and TD2 in Fig. 7 of Groiss) in place of Schindler’s MOS transistors (FET1 and FET2 and FET3 Fig. 1 of Schindler) such as taught by Groiss (Fig. 7), since Schindler discloses generic MOS transistors thereby suggesting that any equivalent MOS tansistorsr would have been usable in Schindler’s reference.
Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over [Schindler (Fig. 1); 5,208,547] in view of [Bakalski et al (Fig. 5a); 2014/0011461] in further view of [Yates et al (Fig. 3); 10,159,524].
Schindler in view of Bakalski et al discloses all the limitations in claim 12 except for that the impedance matching circuit comprises a transformer and an inductor connected in series to a primary side of the transformer, and an inductor connected in series to a secondary side of the transformer. Yates et al discloses an amplifier circuit comprising a transformer (815) and an inductor (812) connected in series to a primary side (814) of the transformer (815), and an inductor (L2) connected in series to a secondary side (816) of the transformer (815). It would have been obvious to substitute Yates et al’s impedance matching circuit in place of Schindler’s impedance circuit, such as taught by Yates et al (Fig. 3) since Schindler discloses a generic impedance matching circuit thereby suggesting that any equivalent impedance matching circuit would have been usable in Schindler’s reference.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Choe whose telephone number is (571)272-1760. The examiner can normally be reached Mon-Fri 6:00 AM- 6:00 PM EST. Examiner interviews are available via telephone, in person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interview practice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea J Lindgren Baltzell can be reached on (571)272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HENRY CHOE/ Primary Examiner, Art Unit 2843
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