DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections – 35 USC§ 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-5, 7, 9, 10, 12-14, 16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Eker et al (US 2023/167616 A1) in view of Chaouat et al(US 12461582 B1).
Regarding claims 1, 10 and 19, Eker ‘616 teaches, a system (page 17 lines 12-17 and Fig. 13, commuting device 400) comprising: one or more processors (page 17 lines 12-27 and Fig. 13, commuting device 400 comprising CPU 420); and one or more storage devices coupled to the one or more processors and storing instructions that(page 17 lines 12-27 and Fig. 13, computing device 400 comprising memory 450), when executed by the one or more processors, cause the one or more processors to perform operations for managing one or more local processing units in a server computing device of a distributed cloud platform, the operations comprising(page 3 lines 19-29, Page 5 lines 21-29, and Figs. 1-3, a computing system for a cloud RAN where CPU resource are managed within a cloud infrastructure. The system manages processing units (CPUs) within servers): receiving one or more metrics associated with respective states of the one or more local processing units for performing a workload(page 3 lines 11-18, page 10 lines 1-10, receiving information indicative of a transmission pattern and numerology of radio data(workload)to be processed, Chaouat ‘582 also teaches, col 11 lines 10-30 power monitor circuitry configured to generate activity information(metrics) bases on the activity of different portions of the processor circuitry), deploying a machine learning model on one or more local accelerators in the server computing device containing the one or more local processing units to generate one or more predictions for the states of the one or more local processing units( page 8 lines 3-9, page 11 lines 5-12, page 12 lines 9-11 and Figs. 3, 11, 13, a CPU offloading heavy computations to a local accelerator (GPU, GPGA or ASIC) associated with the CPU, Eker ‘616 further teaches using a machine learning techniques to estimate/predict execution times).
Eker ‘616 does not explicitly teach, a machine learning model to predict the respective states, receiving the one or more predictions from the one or more local accelerators; and adjusting the respective states of the one or more local processing units based on the predictions.
Chaouat ‘582 teaches, a machine learning model to predict the respective states (abstract, column 11 lines 35-60 and Figs. 2-6, machine learning circuitry predicting future power state of the processor circuit), receiving the one or more predictions from the one or more local accelerators(column 11 lines 35-60 and Figs. 2-6, receiving from computing device(e.g. machine learning circuitry) prediction on the future power state of the processor circuit) ; and adjusting the respective states of the one or more local processing units based on the predictions(column 11 lines 62-column 12 line 21, circuitry 230 that receives predictions, controls the clock circuitry to reduce the frequency of the clock signal(adjust state) provided to the processor).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the communication system of Eker ‘616, by incorporating the teaching of Chaouat ‘582, since such modification would enable a control circuitry that is configured to, in response to the machine learning circuitry predicting a power state of the processor that falls within a set of one or more target predicted power states, control the clock circuitry to reduce the frequency of the clock signal provided to the processor circuitry, as suggested by Chaouat ‘582(abstract).
Regarding claims 3 and 12, the combination of Eker ‘616 and Chaouat ‘582 teaches all of the claim limitations, Eker ‘616 further teaches, wherein the one or more local processing units comprise at least one of central processing units (CPUs), graphic processing units (GPUs), or field-programmable gate arrays (FPGAs) (page 8 lines 3-9. page 16 lines 23-27 and Figs. 3, 13, computing device 400 comprising local CPU 420, GPU and FPGA).
Regarding claims 4 and 13, the combination of Eker ‘616 and Chaouat ‘582 teaches all of the claim limitations, Eker ‘616 further teaches, wherein the one or more accelerators comprises application-specific integrated circuits (ASICs)(page 2 lines 10-17, table 2, page 11 lines 4-12 and fig. 11, an accelerator could also be ASIC).
Regarding claims 5, 14 and 20, the combination of Eker ‘616 and Chaouat ‘582 teaches all of the claim limitations, Chaouat ‘582 further teaches, training, by the one or more processors, the machine learning model locally in the same server computing device as the one or more local processing units based on the one or more metrics (column 10 lines 1-15 and Fig. 5, training system (510) that can be used to train the machine learning model in the field. It uses counter values(metrics) from the processor itself as training inputs).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the communication system of Eker ‘616, by incorporating the teaching of Chaouat ‘582, since such modification would enable a control circuitry that is configured to, in response to the machine learning circuitry predicting a power state of the processor that falls within a set of one or more target predicted power states, control the clock circuitry to reduce the frequency of the clock signal provided to the processor circuitry, as suggested by Chaouat ‘582(abstract).
Regarding claims 7 and 16, the combination of Eker ‘616 and Chaouat ‘582 teaches all of the claim limitations, Chaouat ‘582 further teaches, wherein adjusting the respective states comprises adjusting at least one of frequency, voltage, power, C-states, P-states, or sleep states of the one or more local processing units(column 13 lines 1-25 and Fig. 8, the processor may adjust both supply voltage and clock frequency based on a predicted future power state, notice the clam limitation is written in alternative form thus examiner is required to show only one of the alternative claim limitations).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the communication system of Eker ‘616, by incorporating the teaching of Chaouat ‘582, since such modification would enable a control circuitry that is configured to, in response to the machine learning circuitry predicting a power state of the processor that falls within a set of one or more target predicted power states, control the clock circuitry to reduce the frequency of the clock signal provided to the processor circuitry, as suggested by Chaouat ‘582(abstract).
Regarding claims 9 and 18, the combination of Eker ‘616 and Chaouat ‘582 teaches all of the claim limitations, Eker ‘616 further teaches, wherein the workload comprises at least one of radio access network (RAN) functions, access and mobility management functions (AMF), user plane functions (UPF), or session management functions (SMF)(page 6 lines 16-27, page 8 lines 3-20 and Fig. 3, workload comprises RAN functions, notice the clam limitation is written in alternative form thus examiner is required to show only one of the alternative claim limitations).
Claims 2 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Eker ‘616 and Chaouat ‘582 as applied to claims above, and further in view of Vijayaraghavan et al(US 2021/0406085 A1) hereinafter referred as Vijaya ‘085.
Regarding claims 2 and 11, the combination of Eker ‘616 and Chaouat ‘582 teaches all of the claim limitations except, wherein the one or more metrics comprise at least one of power utilization per processing unit core, power consumption per application running on a processing unit core, number of processing unit core C-states enabled, number of processing unit core P-states enabled, or number of instructions per cycle a processing unit is processing.
Vijaya ‘085 teaches, wherein the one or more metrics comprise at least one of power utilization per processing unit core, power consumption per application running on a processing unit core, number of processing unit core C-states enabled, number of processing unit core P-states enabled, or number of instructions per cycle a processing unit is processing.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the combined communication system of Eker ‘616 and Chaouat ‘582, by incorporating the teaching of Vijaya ‘085, since such modification provides allocating a workload to an accelerator using machine learning as suggested by Vijaya ‘085(abstract).
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Eker ‘616 and Chaouat ‘582 as applied to claims above, and further in view of Gad et al(US 2024/0378486 A1).
Regarding claims 6 and 15, the combination of Eker ‘616 and Chaouat ‘582 teaches all claim limitations except, receiving, by the one or more processors, the machine learning model, the machine learning model being pretrained externally on a disaggregated service management and orchestration (SMO) platform.
Gad ‘486 teaches, receiving, by the one or more processors, the machine learning model, the machine learning model being pretrained externally on a disaggregated service management and orchestration (SMO) platform ([0037] and claim 11, SMO sharing pretrained ML model with another processor).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the communication system of Eker ‘616 and Chaouat ‘582, by incorporating the teaching of Gad ‘486, since such modification would enable to customize a network through xApps by optimizing xApps using ML, as suggested by Gad ‘486([0001]).
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Eker ‘616 and Chaouat ‘582 as applied to claims above, and further in view of Lee et al(US 2017/0205863 A1).
Regarding claims 8 and 17, the combination of Eker ‘616 and Chaouat ‘582 teaches all claim limitations except, wherein adjusting the respective states comprises adjusting the one or more states of a group of the one or more local processing units.
Lee ‘863 further teaches, wherein adjusting the one or more states comprises adjusting the one or more states of a group of the one or more local processing units([0162], [0178] and Fig. 18-19, thread scheduling and multi-core group power-state adjusting (adjusting multiple cores).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the communication system of V Eker ‘616 and Chaouat ‘582, by incorporating the teaching of Lee ‘863, since such modification would provide efficient power management of a multicore processor, as suggested by Lee ‘863([0003]).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AWET HAILE/ Primary Examiner, Art Unit 2474