Prosecution Insights
Last updated: April 19, 2026
Application No. 18/381,614

SELF-CONFIGURING BASEBOARD MANAGEMENT CONTROLLER (BMC)

Non-Final OA §103
Filed
Oct 18, 2023
Examiner
NAM, HYUN
Art Unit
2183
Tech Center
2100 — Computer Architecture & Software
Assignee
Samsung Electronics Co., Ltd.
OA Round
3 (Non-Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
2y 7m
To Grant
86%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
750 granted / 867 resolved
+31.5% vs TC avg
Minimal -1% lift
Without
With
+-0.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
20 currently pending
Career history
887
Total Applications
across all art units

Statute-Specific Performance

§101
10.4%
-29.6% vs TC avg
§103
38.5%
-1.5% vs TC avg
§102
16.1%
-23.9% vs TC avg
§112
19.2%
-20.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 867 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/10/2026 has been entered. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-12 and 14-21 are rejected under 35 U.S.C. 103 as being unpatentable over Ackaret et al. (U.S. Publication 2013/0117601), hereinafter Ackaret in view of Colgrove et al. (U.S. Publication 2017/0315752), hereinafter Colgrove. Referring to claim 1, Colgrove teaches, as claimed, a device (MIDPLANE, see Fig. 1B, Fig. 4., and Fig. 5), comprising: an access logic (read from the personality card, see Paragraph 9) to determine a configuration (configuration and informational data associated with a particular set of hardware and software, see Paragraph 29) of a system (chassis computer system, see Paragraph 29) from a component (EEPOM – Personality Card 102, see Paragraph 29) included in the system, the component separate from the device (see Fig. 5, MIDPLANE 106 and Personality Card 102 (A or B); Note, the Card 102 (A or B) is separate from MIDPLANE); and a logic to configure (details of hardware configuration, see Paragraph 29) the device based at least in part on the configuration of the system, wherein the device is configured to select (see Fig. 1B, Switch 112) a configuration from a first configuration (see Fig. 1B, Personality Card A 130) and a second configuration (see Fig. 1B, Personality Card B 130) based at least in part on the configuration read from the component (read from the personality card, see Paragraph 9). Ackaret does not disclose expressly the first configuration including a first driver and the second configuration including a second driver. Colgrove does disclose the first configuration (receiving information, see Paragraph 55) including a first driver (drivers that enable the storage devices, see Paragraph 55) and the second configuration including a second driver (drivers, see Paragraph 55; and Fig. 1, Storage Array 102 and/or Storage Array 104). At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate storage system of Colgrove (see Colgrove Paragraph 3) into storage (see Ackaret Paragraph 40) of Ackaret. The suggestion/motivation for doing so would have been to upgrade the storage devices (find it desirable to upgrade the storage devices, see Colgrove Paragraph 2). As to claim 2, the modification teaches the device according to claim 1, wherein using the second driver enables the device to determine the configuration of at least one other device (see Colgrove Fig. 2, Storage Devices 216; Note, the modification of Ackaret/Colgrove allows for multiple ‘other’ storages) included in the system. As to claim 3, the modification teaches the device according to claim 1, wherein the access logic includes a Vital Product Data (VPD) (VPD, see Ackaret Paragraph 6) reading logic to read the configuration of the system from a VPD. As to claim 4, the modification teaches the device according to claim 1, wherein the access logic includes a pin reading logic (see Colgrove Fig. 1B, Switch 112; Note, reading of a switch position logic) to determine the configuration of the system from a signal (Note, signals are on the lines shown in Colgrove Fig. 1B) on at least one pin on the device. As to claim 5, the modification teaches the device according to claim 1, wherein the logic includes a driver loader (initialize drivers, see Colgrove Paragraph 55; Note, a driver loader is interpreted as a driver starter) to load the first driver or the second driver based at least in part on the configuration (receiving information, see Colgrove Paragraph 55: Note, information has configuration information) of the system. As to claim 6, the modification teaches the device according to claim 1, wherein the access logic is configured to determine whether the configuration of the system includes a High Availability (HA) chassis (high availability designing the blade chassis, enhanced availability personality card for a chassis computer system and high availability of the personality card is ensured, see Ackaret Paragraphs 4, 6 and 14). As to claim 7, the modification teaches the device according to claim 6. The modification of Ackaret/Colgrove does not expressly disclose wherein the logic is configured to load an HA driver. Colgrove discloses providing/initiating drivers for storage devices. It is common sense to include a driver for HA when the chassis includes specific storage devices and wherein the storage device becomes part of HA. As to claim 8, the modification teaches the device according to claim 7, wherein the logic is configured to load the HA driver independent (redundant path, see Paragraph 7; Note, a redundant path is provided so the loading of driver is independent of a failed path) of whether a pairing partner is available (pair of chassis management, see Ackaret Paragraph 7) . As to claim 21, the modification teaches the device according to claim 1, wherein the system includes the device (see Ackaret Fig. 5, 102 is part of system 500). As to claims 9-12, 14, and 18-20 they are directed to a method/program to implement the device as set forth in claims 1-8. Therefore, they are rejected on the same basis as set forth hereinabove. As to claim 15, the modification teaches the method according to claim 14, further comprising reporting an error (failure, see Ackaret Paragraph 7; Note, it is implicit failure is noted or reported) if the HA driver is not available (Note, the modification allows for HA driver being part of personality card components). As to claim 16, the modification teaches the method according to claim 14, further comprising attempting (redundant bidirectional bus, see Ackaret Paragraph 7; Note, including bus is attempting at communicating) to communicate with a pairing partner (pair of chassis, see Ackaret Paragraph 7) for the device. As to claim 17, the modification teaches the method according to claim 16, further comprising reporting an error (failure, see Ackaret Paragraph 7; Note, it is implicit failure is noted or reported) if the device is not configured to communicate with the pairing partner (Note, a configuration that fails communicating is just another components not communicating to the system). Response to Arguments Applicant's arguments filed 3/10/2026 have been fully considered but they are moot in view of new grounds of rejections. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hyun Nam whose telephone number is (571) 270-1725 and fax number is (571) 270-2725. The examiner can normally be reached on Monday through Friday 8:30 AM to 5:00 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HYUN NAM/Primary Examiner, Art Unit 2183
Read full office action

Prosecution Timeline

Oct 18, 2023
Application Filed
May 31, 2025
Non-Final Rejection — §103
Jul 10, 2025
Applicant Interview (Telephonic)
Jul 12, 2025
Examiner Interview Summary
Aug 08, 2025
Response Filed
Nov 14, 2025
Final Rejection — §103
Mar 10, 2026
Request for Continued Examination
Mar 17, 2026
Response after Non-Final Action
Apr 04, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

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Patent 12579083
EFFICIENT QUEUE ACCESS FOR USER-SPACE PACKET PROCESSING
2y 5m to grant Granted Mar 17, 2026
Patent 12566718
CONFIGURING PCI EXPRESS MODULE USING HARDWARE IN A MEMORY SUB-SYSTEM
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Patent 12554660
HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE
2y 5m to grant Granted Feb 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
86%
With Interview (-0.7%)
2y 7m
Median Time to Grant
High
PTA Risk
Based on 867 resolved cases by this examiner. Grant probability derived from career allow rate.

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