DETAILED ACTION
This office action is in response to Application No. 18/381,643, filed on 19 October 2023. Claims 1-9 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang (US 2022/0012392).
Regarding claim 1, Huang discloses a method for configuring a plurality of memory units and a plurality of logic units in an integrated circuit (Fig. 5), comprising: providing a plurality of predefined parameters of the plurality of memory units; parsing the plurality of predefined parameters to generate a plurality of parsed parameters (¶17);
compiling the plurality of memory units and the plurality of logic units at the same stage to generate a plurality of candidates of mapping results according to the plurality of parsed parameters (Fig. 5; ¶¶18, 21, 22);
selecting a candidate of the mapping results from the plurality of candidates of the mapping results; and disposing the plurality of memory units and the plurality of logic units onto the integrated circuit according to the candidate of the mapping results (Figs. 3 and 4; ¶¶23-25).
Regarding claim 8, Huang discloses that compiling the plurality of memory units and the plurality of logic units at the same stage is a mixed compiler compiling the plurality of memory units and the plurality of logic units at the same stage (Fig. 5; ¶¶18, 21, 22).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 3, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Sharma (US 2023/0267078).
Regarding claim 2, Huang discloses that the plurality of memory units are contained by a plurality of unified memory structure models (¶21). Applicant does not define or otherwise limit what constitutes a ‘unified memory structure model’, and it also does not appear to be a term of art in memory compilation. Huang’s memory structure models appear to be identical to those disclosed in Applicant’s Specification, though the specification is not limiting. Nevertheless, if Huang is found to be unclear regarding these limitations, Sharma also discloses unified memory structure models (¶41). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Huang and Sharma, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of implementing memory in unified memory models. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Huang discloses SRAM memory units contained by a plurality of unified memory structure models. Sharma further explicitly teaches that SRAMs should be contained by unified memory structure models. The teachings of Sharma are directly applicable to Huang in the same way, so that Huang’s SRAMs would similarly be contained by unified memory structure models to improve memory management.
Regarding claim 3, Huang discloses that the plurality of predefined parameters comprises model names, ports, functions and configure files of the plurality of unified memory structure models (Fig. 4, CPU-IP, GPU-IP, etc. and config files; Fig. 5, CPU IP modules with behavior RAMs of various sizes, etc.; ¶21).
Regarding claim 9, Huang discloses that compiling the plurality of memory units and the plurality of logic units at the same stage is a unified memory structure compiler compiling the plurality of memory units and a logic compiler compiling the plurality of logic units at the same stage (¶21). As discussed above with regard to claim 2, if Huang is found to be unclear regarding unified memory structures, Sharma discloses the same (¶41). Motivation to combine remains consistent with claim 2.
Claim(s) 4 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Bunandar (US 2022/0405450).
Regarding claim 4, Huang discloses that selecting the candidate of the mapping results from the plurality of candidates of the mapping results is selecting the candidate of the mapping results from the plurality of candidates of the mapping results with predetermined criteria (¶¶23, 25), but does not appear to explicitly disclose using a reinforcement learning model. Bunandar discloses selecting the candidate of the mapping results from the plurality of candidates of the mapping results using a reinforcement learning model with predetermined criteria (¶¶62, 67). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Huang and Bunandar, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of using reinforcement learning to improve candidate selection. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Huang discloses selecting candidates based on predetermined criteria. Bunandar teaches that component selection should be performed using a reinforcement learning model. The teachings of Bunandar are directly applicable to Huang in the same way, so that Huang would similarly use a reinforcement learning model to improve candidate selection.
Regarding claim 5, Huang discloses that the predetermined criteria comprise power consumption, performance and area of the plurality of memory units and the plurality of logic units (¶23). Bunandar also discloses the same (¶62). Motivation to combine remains consistent with claim 4.
Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Nath (US 2022/0229960).
Regarding claim 6, Huang discloses that disposing the plurality of memory units and the plurality of logic units onto the integrated circuit according to the candidate of the mapping results is disposing the plurality of memory units and the plurality of logic units onto the integrated circuit according to the candidate of the mapping results with predetermined criteria (Figs. 3 and 4; ¶25), but does not appear to explicitly disclose using a reinforcement learning model. Nath discloses disposing the plurality of memory units and the plurality of logic units onto the integrated circuit according to the candidate of the mapping results using a reinforcement learning model with predetermined criteria (¶33). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Huang and Nath, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of using reinforcement learning to improve design implementation. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Huang discloses implementing design elements based on predetermined criteria. Nath teaches that design implementation should be performed using a reinforcement learning model. The teachings of Nath are directly applicable to Huang in the same way, so that Huang would similarly use a reinforcement learning model to improve design implementation.
Regarding claim 7, Huang discloses that the predetermined criteria comprise power consumption, performance and area of the plurality of memory units and the plurality of logic units (¶23). Nath also discloses the same (¶¶33, 34). Motivation to combine remains consistent with claim 6.
Conclusion
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23 June 2026
/ARIC LIN/ Examiner, Art Unit 2851
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