Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 11-16 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
See amendments, see Applicant arguments filed 5/14/2026.
Claim 2, 4, 5, 7-10, 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (US 20230369263 A1) hereafter referred to as Chuang in view of Lin et al. (US 20150303159 A1) hereafter referred to as Lin
In regard to claim 1 Chuang teaches a [see “FIG. 1 to FIG. 11 illustrate partial cross sectional views of intermediate stages in the manufacturing of a semiconductor package according to some embodiments”] semiconductor package comprising:
a base substrate [i.e. the portion of “package 200” below 112, 130];
an interposer substrate [see including “backside redistribution structure, e.g., protective layer 104” “openings 1041, 1042 are formed through the protective layer 104 to reveal the functional pads 106 and a part of the dummy pad portions 107 of the redistribution circuit layer” “the redistribution circuit layer 106, 107 is formed over the protective layer 104. As an example to form redistribution circuit layer, a seed layer (not shown) is formed over the protective layer 104”] including a plurality of interposer redistribution structures sequentially stacked in a vertical direction and an interposer insulation layer, the plurality of interposer redistribution structures including a plurality of conductive [see 106 is connected to vias 112, see “As illustrated, the backside redistribution structure 110 includes the two dielectric layers 104 and 108 and one redistribution circuit layer 106, 107. In other embodiments, the back-side redistribution structure 110 can include any number of dielectric layers, redistribution circuit layers, and vias”] interposer patterns and a plurality of conductive interposer vias;
a semiconductor chip [“a plurality of integrated circuit dies 114 are adhered to the dielectric layer 108 by an adhesive 116”] disposed between the base substrate and the interposer substrate in the vertical direction and [see the connections on 114 are below] attached on the base substrate; and
a plurality of conductive connection pads [106, 107] respectively disposed on a plurality of uppermost conductive interposer patterns [see Fig. 11, see 106 is on a via portion connected to 112 see “As illustrated, the backside redistribution structure 110 includes the two dielectric layers 104 and 108 and one redistribution circuit layer 106, 107. In other embodiments, the back-side redistribution structure 110 can include any number of dielectric layers, redistribution circuit layers, and vias”] of an uppermost interposer redistribution structure of the plurality of interposer redistribution structures,
wherein the interposer insulation layer comprises a plurality of [“openings 1041, 1042 are formed through the protective layer 104 to reveal the functional pads 106 and a part of the dummy pad portions 107 of the redistribution circuit layer” ] pad holes, each pad hole of the plurality of pad holes exposing [see Fig. 11] at least a portion of each of an upper surface of a corresponding conductive connection pad [see Fig. 11] of the plurality of conductive connection pads, and
a side surface of each of the plurality of conductive connection pads [see Fig. 11] is vertical to an upper surface of the interposer insulation layer, a side surface of each of the plurality of uppermost conductive interposer patterns is vertical [see Fig. 11] to the upper surface of the interposer insulation layer, and an inner sidewall of each of the plurality of pad holes is inclined [see Fig. 11, see side of 104 in the openings] with respect to the upper surface of the interposer insulation layer
but does not teach that “each pad hole of the plurality of pad holes exposing both at least a portion of each of an upper surface of a corresponding conductive connection pad of the plurality of conductive connection pads and an upper surface of a corresponding uppermost conductive interposer pattern of the plurality of uppermost conductive interposer patterns” .
See that in Chuang the redistribution circuit layer 106, 107 is part of “structure 110 can include any number of dielectric layers, redistribution circuit layers, and vias” so a portion of the upper surface is used as pad, and see that Chuang uses seed layers see paragraph 0018 “As an example to form redistribution circuit layer, a seed layer (not shown) is formed over the protective layer 104. In some embodiments, the seed layer is a metal layer, which .... remaining portions of the seed layer and conductive material form the redistribution circuit layer 106, 107”.
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See Lin Fig. 7 see “chip 300 having a plurality of pads 301 formed thereon is provided, and a passivation layer 303 is formed on a surface of the chip 300, wherein the passivation layer 303 has a plurality of openings 305 exposing a portion of surfaces of the pads 301” “Referring to FIG. 6, a plurality of bumps 307 are formed on the surfaces of the pads 301 in the openings 305, wherein the size of the bumps 307 is smaller than that of the openings 305” “Referring to FIG. 7, a plurality of solder balls 311 are formed covering surfaces of the bumps 307 and the surfaces of the pads 301 exposed by the openings 305”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Chuang to include a bump on 106, 107 thus the bump is now called the “pad” and 106, 107 are the plurality of uppermost conductive interposer patterns i.e. to modify Chuang to include that “each pad hole of the plurality of pad holes exposing both at least a portion of each of an upper surface of a corresponding conductive connection pad of the plurality of conductive connection pads and an upper surface of a corresponding uppermost conductive interposer pattern of the plurality of uppermost conductive interposer patterns” .
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is the obtain maximum contact for good conduction.
In regard to claim 3 Chuang and Lin as combined teaches wherein a width of the plurality of conductive connection pads [see combination, see Lin Fig. 7 see modify Chuang to include a bump on 106, 107 thus the bump is now called the “pad” and 106, 107 are the plurality of uppermost conductive interposer patterns] in a first horizontal direction is less than a width of the plurality of uppermost conductive interposer patterns in the first horizontal direction.
In regard to claim 6 Chuang and Lin as combined teaches wherein the plurality of uppermost conductive interposer patterns comprise a conductive line pattern [see that 106, 107 extends in a horizontal direction] extending in a horizontal direction and a conductive pad [see combination, see Lin Fig. 7 see modify Chuang to include a bump on 106, 107 thus the bump is now called the “pad” and 106, 107 are the plurality of uppermost conductive interposer patterns] pattern having an independent island shape, in a plan view.
Claim(s) 17, 19, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (US 20230369263 A1) hereafter referred to as Chuang in view of Shigihara et al. (JP 2008016514 A) hereafter referred to as Shigihara
In regard to claim 17 Chuang teaches a [see “FIG. 1 to FIG. 11 illustrate partial cross sectional views of intermediate stages in the manufacturing of a semiconductor package according to some embodiments”] semiconductor package comprising:
a first base substrate [i.e. the portion of “package 200” below 112, 130];
a first semiconductor chip [“a plurality of integrated circuit dies 114 are adhered to the dielectric layer 108 by an adhesive 116”” “connectors 126 of the die 114”] attached on the first base substrate;
a plurality of conductive posts [see Fig. 11, “Referring now to FIG. 5, an encapsulating material 130 is formed over the dielectric layer 108 to at least laterally encapsulate the die 114 and the through vias 112 (and dummy through vias 113, if applicable)”] disposed around the first semiconductor chip, on the first base substrate;
an interposer substrate [see including “backside redistribution structure, e.g., protective layer 104” “openings 1041, 1042 are formed through the protective layer 104 to reveal the functional pads 106 and a part of the dummy pad portions 107 of the redistribution circuit layer” “the redistribution circuit layer 106, 107 is formed over the protective layer 104. As an example to form redistribution circuit layer, a seed layer (not shown) is formed over the protective layer 104”] including an interposer redistribution structure [see Fig. 11, see connected to 314, and to 112] having a conductive interposer pattern, [see “As illustrated, the backside redistribution structure 110 includes the two dielectric layers 104 and 108 and one redistribution circuit layer 106, 107. In other embodiments, the back-side redistribution structure 110 can include any number of dielectric layers, redistribution circuit layers, and vias”] a conductive interposer via and an interposer insulation layer, the interposer insulation layer having an upper surface including a pad hole [“openings 1041, 1042 are formed through the protective layer 104 to reveal the functional pads 106 and a part of the dummy pad portions 107 of the redistribution circuit layer” ] exposing the conductive interposer pattern, the interposer substrate is electrically connected with [see Fig. 11] the first base substrate through the plurality of conductive posts;
a second base substrate [see paragraph 0045 “referring to FIG. 10 and FIG. 11, a substrate 300 may be mounted on the first package 100 through a plurality of connectors 314, 316 to form a semiconductor package 500 shown in FIG. 11”] on the interposer substrate;
a second semiconductor chip [“In some embodiments, the substrate 300 may include an interposer, a redistribution structures, or other mounting surface, with one or more dies disposed thereon”] attached on the second base substrate;
a conductive connection pad [see Fig. 11 see that 314 is connected to pad 106, 107 see “openings 1041, 1042 are formed through the protective layer 104 to reveal the functional pads 106 and a part of the dummy pad portions 107 of the redistribution circuit layer” ] disposed on the conductive interposer pattern [see Fig. 11, see 106 is on a via portion connected to 112 see “As illustrated, the backside redistribution structure 110 includes the two dielectric layers 104 and 108 and one redistribution circuit layer 106, 107. In other embodiments, the back-side redistribution structure 110 can include any number of dielectric layers, redistribution circuit layers, and vias”], in the pad hole; and
an external connection terminal [“In some embodiments, the connectors includes a plurality of functional connectors 314 and a plurality of dummy connectors 316 electrically disconnected from the functional connectors 314”] disposed on the conductive connection pad, the external connection terminal electrically connecting [“substrate 300 is in electrical communication with the functional pads 106 through the functional connectors 314. The connectors 314, 316 may include, for example, solder balls, conductive bumps, pillars, studs, or another conductive structure”] the interposer substrate with the second base substrate, wherein an inner sidewall of the pad hole is inclined [see Fig. 11, see side of 104 in the openings] with respect to an upper surface of the interposer insulation layer,
but does not teach the inner sidewall of the pad hole is spaced apart from the conductive connection pad and the conductive interposer pattern in a first horizontal direction.
See that in Chuang the redistribution circuit layer 106, 107 is part of “structure 110 can include any number of dielectric layers, redistribution circuit layers, and vias” so a portion of the upper surface is used as pad, and see that Chuang uses seed layers see paragraph 0018 “As an example to form redistribution circuit layer, a seed layer (not shown) is formed over the protective layer 104. In some embodiments, the seed layer is a metal layer, which .... remaining portions of the seed layer and conductive material form the redistribution circuit layer 106, 107”.
See Shigihara Fig. 5, Figs. 13-15, Fig. 19 see “first metal film 15 connected to the bonding pad part M6a through the first opening C1 is formed on the semiconductor substrate 1” “as shown in FIG. 5, the solder bump electrode 20 is formed on the upper surface of the UBM 17 through the second opening C2. The solder bump electrode 20 is an external connection electrode, and for example, lead-free solder is used. The solder bump electrode 20 can be formed by, for example, a printing method, a plating method, or a ball method. In the printing method, the solder paste is mask-printed on the UBM 17 via the Au seed layer 18, and then the solder paste is formed into a spherical shape by reflow processing and connected to the UBM 17” “Au seed layer 18 is selectively formed on the surface (upper surface and side surface) of the second metal film 16 constituting the upper layer of the UBM 17 by electroless plating. Au is easy to grow on the second metal film (representative material, for example, Ni film) 16, but Au on the first metal film (representative material, for example, Cu film) 15” see that a space is left around the pad.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Chuang to include that the inner sidewall of the pad hole is spaced apart from the conductive connection pad and the conductive interposer pattern in a first horizontal direction.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to make a good connection by increasing contact area.
In regard to claim 19 Chuang and Shigihara as combined teaches further comprising: a conductive barrier layer [see combination, see the layer structure in Shigihara see Au 18 on Ni 16 on Cu 15 on the bonding pad part M6a ] disposed between the conductive interposer pattern and the conductive connection pad, the conductive barrier layer covering an upper surface of the conductive interposer pattern; and the external connection terminal covers an upper surface of the conductive barrier layer.
In regard to claim 20 Chuang and Shigihara as combined teaches wherein an upper surface of the interposer insulation layer is disposed at a height from the interposer substrate in a vertical direction that is greater [this is true, see Chuang Fig. 11, see combination see Shigihara Fig. 5, Fig. 19] than or equal to a height of an upper surface of the conductive connection pad from the interposer substrate in the vertical direction.
Response to Arguments
Applicant's arguments filed 5/14/2026 have been fully considered but they are not persuasive.
On page 10 the Applicant argues “Chuang describes openings 1041, 1042 formed through protective layer 104 to reveal functional pads 106 and dummy pad portions 107 of redistribution circuit layer 106, 107. See Chuang, [0018], [0038]-[0041], FIGS. 9-11. Chuang further describes redistribution circuit layer 106, 107 and openings 1041, 1042 in the context of the backside redistribution structure. See Chuang, [0018], [0039]-[0041], FIGS. 9-11.
Shigihara describes a UBM 17 including first metal film 15 and second metal film 16, and describes forming an Au seed layer 18 on the upper and side surfaces of the second metal film 16. See Shigihara, [0032]-[0034], FIGS. 2-4. Shigihara further describes forming solder bump electrode 20 through second opening C2, with the solder bump electrode 20 connected to the upper and side surfaces of the second metal film 16 constituting the upper layer of UBM 17. See Shigihara, [0035]-[0036], FIG. 5.
The cited portions of Chuang and Shigihara address different structures and different openings. Chuang's cited disclosure concerns openings 1041, 1042 that reveal functional pads 106 and dummy pad portions 107 of redistribution circuit layer 106, 107. See Chuang, [0038]- [0041], FIGS. 9-11. Shigihara's cited disclosure concerns second opening C2 and a solder bump electrode connected to the upper and side surfaces of the second metal film 16 of UBM 17. See Shigihara, [0034]-[0036], FIGS. 4-5.
The rejection does not identify where Chuang or Shigihara teaches or suggests the claim 1 language requiring "each pad hole" to expose "both at least a portion of each of an upper surface of a corresponding conductive connection pad" and "an upper surface of a corresponding uppermost conductive interposer pattern." Nor does the rejection identify where Chuang or10
Shigihara teaches or suggests the claim 11 language requiring "a side surface and an upper surface of each of the plurality of uppermost conductive interposer patterns" and "a side surface and an upper surface of each of the plurality of conductive connection pads" to be "exposed by the same pad hole."
The amendment to claim 1 adds "exposing both" to clarify that the recited pad hole exposes both recited upper surfaces: "an upper surface of a corresponding conductive connection pad" and "an upper surface of a corresponding uppermost conductive interposer pattern." The amendment to claim 11 adds "the same pad hole of the plurality of pad holes" to clarify that the recited side and upper surfaces are exposed by the same pad hole.
Shigihara's FIGS. 4-5 and [0034]-[0036] describe exposure of an Au seed layer 18 on UBM 17 through second opening C2 and connection of solder bump electrode 20 to the upper and side surfaces of the second metal film 16. Those cited portions do not identify a conductive connection pad and an uppermost conductive interposer pattern exposed by the same pad hole as recited in claim 1, or the corresponding upper and side surfaces exposed by the same pad hole as recited in claim 11.
Accordingly, the rejection does not provide a sufficient factual basis showing that the combination of Chuang and Shigihara teaches or suggests the amended limitations of claims 1 and 11.”.
The Examiner responds that see rejection above
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See Lin Fig. 7 see “chip 300 having a plurality of pads 301 formed thereon is provided, and a passivation layer 303 is formed on a surface of the chip 300, wherein the passivation layer 303 has a plurality of openings 305 exposing a portion of surfaces of the pads 301” “Referring to FIG. 6, a plurality of bumps 307 are formed on the surfaces of the pads 301 in the openings 305, wherein the size of the bumps 307 is smaller than that of the openings 305” “Referring to FIG. 7, a plurality of solder balls 311 are formed covering surfaces of the bumps 307 and the surfaces of the pads 301 exposed by the openings 305”, thus , it would be obvious to modify Chuang to include a bump on 106, 107 thus the bump is now called the “pad” and 106, 107 are the plurality of uppermost conductive interposer patterns.
On page 11-13 the Applicant argues “Regarding independent claim 17, recites, in relevant part, "an interposer substrate including an interposer redistribution structure having a conductive interposer pattern, a conductive interposer via and an interposer insulation layer, the interposer insulation layer having an upper surface including a pad hole exposing the conductive interposer pattern." Claim 17 further recites "a conductive connection pad disposed on the conductive interposer pattern, in the pad hole," and "an external connection terminal disposed on the conductive connection pad, the external connection terminal electrically connecting the interposer substrate with the second base substrate." Claim 17 also recites that "an inner sidewall of the pad hole is inclined with respect to an upper surface of the interposer insulation layer" and that "the inner sidewall of the pad hole is spaced apart from the conductive connection pad and the conductive interposer pattern in a first horizontal direction."
Chuang describes openings 1041, 1042 formed through protective layer 104 to reveal functional pads 106 and dummy pad portions 107 of redistribution circuit layer 106, 107, and shows those openings in the package structure of FIGS. 9-11. See Chuang, [0038]-[0041], FIGS. 9-11. Chuang also describes connectors 314 disposed in openings 1041, 1042 and bonded with functional pads 106 and dummy pad portions 107. See Chuang, [0045]-[0046], FIG. 11.
Shigihara describes UBM 17 including first metal film 15 and second metal film 16, an Au seed layer 18 formed on upper and side surfaces of second metal film 16, and solder bump electrode 20 formed through second opening C2. See Shigihara, [0032]-[0036], FIGS. 2-5. Shigihara also describes, in another embodiment, UBM 21 as a redistribution layer and a second opening C2 formed to expose a region of UBM 21, with a gap L between UBM 21 and resin film 22. See Shigihara, [0040]-[0042], FIGS. 6-8.
The rejection does not identify where Chuang teaches or suggests that the "inner sidewall of the pad hole is spaced apart from the conductive connection pad and the conductive interposer pattern in a first horizontal direction" as claimed in claim 17. Chuang's openings 1041, 1042 are described as revealing functional pads 106 and dummy pad portions 107, and Chuang's connectors 314 are described as being disposed in the openings and bonded with the functional pads 106 and dummy pad portions 107. See Chuang, [0038]-[0041], [0045]-[0046], FIGS. 9-11. The rejection does not identify, in Chuang, a pad hole having an inner sidewall that is spaced apart from both a "conductive connection pad" and a "conductive interposer pattern" as recited in claim 17.
The cited portions of Shigihara likewise do not provide the recited arrangement of claim 17. Shigihara's FIGS. 2-5 and [0032]-[0036] describe UBM 17 and solder bump electrode 20, where solder bump electrode 20 is connected to the upper and side surfaces of the second metal film 16 of UBM 17 through second opening C2. Shigihara's FIGS. 6-8 and [0040]-[0042] describe UBM 21 as a redistribution layer and a second opening C2 exposing a region of UBM 21. These cited portions address a UBM/solder bump structure on a semiconductor substrate. The rejection does not identify, in Shigihara, an "interposer substrate" including "an interposer redistribution structure having a conductive interposer pattern, a conductive interposer via and an interposer insulation layer," together with "a conductive connection pad disposed on the conductive interposer pattern, in the pad hole," and an "external connection terminal disposed on the conductive connection pad" as recited in claim 17.
Nor does the rejection explain how the cited portions of Shigihara are applied to Chuang so that the same pad hole includes the spatial relationship required by claim 17: "the inner sidewall12
of the pad hole is spaced apart from the conductive connection pad and the conductive interposer pattern in a first horizontal direction." Shigihara describes spacing in the context of UBM 21 and resin film 22, including a gap L in FIG. 7, but that disclosure is tied to exposing a side surface of UBM 21 for subsequent formation of Au seed layer 18. See Shigihara, [0041]-[0042], FIGS. 7-8. The rejection does not identify where this disclosure provides the claim 17 arrangement in which the pad-hole sidewall is spaced apart from both the "conductive connection pad" and the "conductive interposer pattern."
Accordingly, the cited portions of Chuang and Shigihara do not provide a sufficient factual basis for the limitation that "the inner sidewall of the pad hole is spaced apart from the conductive connection pad and the conductive interposer pattern in a first horizontal direction," as recited in claim 17.
The Examiner responds that this was discussed during the interview conducted on 30th March 2026 an the Examiner explained that see that rejection cites see Shigihara Fig. 5, Figs. 13-15, Fig. 19 and it can be clearly seen in Fig. 14, Fig. 15, Fig. 19 that inner sidewall of the pad hole is away from side of 16 in Fig. 19 so that solder 28 is in the pad hole and touching the top and side of pad 16 , similarly solder 25 is in the pad hole and touching the top and side of 16 in Fig. 15 and similarly the solder 24 is in the pad hole and touching the top and side of 16 in Fig. 14, thus Shigihara gives 3 examples of pad holes wherein the the inner sidewall of the pad hole is spaced apart from the conductive connection pad and the conductive interposer pattern in a first horizontal direction, see in Fig. 14, Fig. 15, Fig. 19 the conductive interposer pattern is 15 and see that inner sidewall of pad hole in 27 is very far away from the sidewall of 15, similarly in both Fig. 14, and Fig. 15 the inner sidewall of pad hole in 19 bulges outward and is much bigger than the sidewall in 15 and 16 and that is why solder is able to enter the pad hole to touch the side of 16.
Regarding whether Chuang and Shigihara teach similar art, the Examiner notes that in both Chuang and Shigihara the subject matter is a solder ball making contact to a pad and that is why they are similar because they are both teaching how a solder ball can be placed to make a connection later to another deevice or substrate or electrode, thus Chuang and Shigihara teach similar art, and the motivation is good and the rejection is valid.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt D Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
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