Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 3, 16, 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 4-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (US 20230369263 A1) hereafter referred to as Chuang in view of Shigihara et al. (JP 2008016514 A) hereafter referred to as Shigihara
In regard to claim 1 Chuang teaches a [see “FIG. 1 to FIG. 11 illustrate partial cross sectional views of intermediate stages in the manufacturing of a semiconductor package according to some embodiments”] semiconductor package comprising:
a base substrate [i.e. the portion of “package 200” below 112, 130];
an interposer substrate [see including “backside redistribution structure, e.g., protective layer 104” “openings 1041, 1042 are formed through the protective layer 104 to reveal the functional pads 106 and a part of the dummy pad portions 107 of the redistribution circuit layer” “the redistribution circuit layer 106, 107 is formed over the protective layer 104. As an example to form redistribution circuit layer, a seed layer (not shown) is formed over the protective layer 104”] including a plurality of interposer redistribution structures sequentially stacked in a vertical direction and an interposer insulation layer, the plurality of interposer redistribution structures including a plurality of conductive [see 106 is connected to vias 112, see “As illustrated, the backside redistribution structure 110 includes the two dielectric layers 104 and 108 and one redistribution circuit layer 106, 107. In other embodiments, the back-side redistribution structure 110 can include any number of dielectric layers, redistribution circuit layers, and vias”] interposer patterns and a plurality of conductive interposer vias;
a semiconductor chip [“a plurality of integrated circuit dies 114 are adhered to the dielectric layer 108 by an adhesive 116”] disposed between the base substrate and the interposer substrate in the vertical direction and [see the connections on 114 are below] attached on the base substrate; and
a plurality of conductive connection pads [106, 107] respectively disposed on a plurality of uppermost conductive interposer patterns [see Fig. 11, see 106 is on a via portion connected to 112 see “As illustrated, the backside redistribution structure 110 includes the two dielectric layers 104 and 108 and one redistribution circuit layer 106, 107. In other embodiments, the back-side redistribution structure 110 can include any number of dielectric layers, redistribution circuit layers, and vias”] of an uppermost interposer redistribution structure of the plurality of interposer redistribution structures,
wherein the interposer insulation layer comprises a plurality of [“openings 1041, 1042 are formed through the protective layer 104 to reveal the functional pads 106 and a part of the dummy pad portions 107 of the redistribution circuit layer” ] pad holes, each pad hole of the plurality of pad holes exposing [see Fig. 11] at least a portion of each of an upper surface of a corresponding conductive connection pad [see Fig. 11] of the plurality of conductive connection pads, and
a side surface of each of the plurality of conductive connection pads [see Fig. 11] is vertical to an upper surface of the interposer insulation layer, a side surface of each of the plurality of uppermost conductive interposer patterns is vertical [see Fig. 11] to the upper surface of the interposer insulation layer, and an inner sidewall of each of the plurality of pad holes is inclined [see Fig. 11, see side of 104 in the openings] with respect to the upper surface of the interposer insulation layer
but does not teach that each pad hole of the plurality of pad holes exposing “and an upper surface of a corresponding uppermost conductive interposer pattern of the plurality of uppermost conductive interposer patterns”.
See that in Chuang the redistribution circuit layer 106, 107 is part of “structure 110 can include any number of dielectric layers, redistribution circuit layers, and vias” so a portion of the upper surface is used as pad, and see that Chuang uses seed layers see paragraph 0018 “As an example to form redistribution circuit layer, a seed layer (not shown) is formed over the protective layer 104. In some embodiments, the seed layer is a metal layer, which .... remaining portions of the seed layer and conductive material form the redistribution circuit layer 106, 107”.
See Shigihara Fig. 5, Figs. 13-15, Fig. 19 see “first metal film 15 connected to the bonding pad part M6a through the first opening C1 is formed on the semiconductor substrate 1” “as shown in FIG. 5, the solder bump electrode 20 is formed on the upper surface of the UBM 17 through the second opening C2. The solder bump electrode 20 is an external connection electrode, and for example, lead-free solder is used. The solder bump electrode 20 can be formed by, for example, a printing method, a plating method, or a ball method. In the printing method, the solder paste is mask-printed on the UBM 17 via the Au seed layer 18, and then the solder paste is formed into a spherical shape by reflow processing and connected to the UBM 17” “Au seed layer 18 is selectively formed on the surface (upper surface and side surface) of the second metal film 16 constituting the upper layer of the UBM 17 by electroless plating. Au is easy to grow on the second metal film (representative material, for example, Ni film) 16, but Au on the first metal film (representative material, for example, Cu film) 15” see that a space is left around the pad.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Chuang to include an adhesion layer and additional UBM layers i.e. to modify Chuang to include that each pad hole of the plurality of pad holes exposing “and an upper surface of a corresponding uppermost conductive interposer pattern of the plurality of uppermost conductive interposer patterns”.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is the obtain maximum contact for good conduction.
In regard to claim 2 Chuang and Shigihara as combined does not specifically teach wherein the inner sidewalls of the plurality of pad holes are respectively spaced apart from the side surfaces of the plurality of uppermost conductive interposer patterns.
However see combination Shigihara see Fig. 5, Figs. 13-15, Fig. 19 see that 20 is shown to be able to attach to the sides of at least 16 and also on 18 shown as coating 16 in Fig. 4 and to do this, the insulation leaves room around the pad, thus the claim can be satisfied by designating 16 as “uppermost conductive interposer patterns” and 18 as the pad itself.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Chuang to include wherein the inner sidewalls of the plurality of pad holes are respectively spaced apart from the side surfaces of the plurality of uppermost conductive interposer patterns.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is the obtain maximum contact for good conduction.
In regard to claim 4 Chuang and Shigihara as combined teaches wherein a width of the plurality of pad holes in a first horizontal direction [see combination claim 2, the claim can be satisfied by designating 16 as “uppermost conductive interposer patterns” and 18 as the pad itself] is greater than a width of the plurality of uppermost conductive interposer patterns in the first horizontal direction.
In regard to claim 5 Chuang and Shigihara as combined teaches wherein an uppermost surface of the interposer insulation layer is disposed at a height from an upper surface of the base substrate in the vertical direction that is greater [this is true, see Chuang Fig. 11, see combination see Shigihara Fig. 5, Fig. 19] than or equal to a height of the upper surfaces of the plurality of conductive connection pads from the upper surface of the base substrate in the vertical direction.
In regard to claim 6 Chuang and Shigihara as combined teaches wherein the plurality of uppermost conductive interposer patterns comprise a conductive line pattern extending [see combination, see that 106 extends in a horizontal direction] in a horizontal direction and a conductive pad pattern [see combination, see Shigihara the layers of Cu, Ni, Au are islands] having an independent island shape, in a plan view.
In regard to claim 7 Chuang and Shigihara as combined teaches further comprising a plurality of conductive pad seed layers disposed between [see Chuang uses seed layers see paragraph 0018 “As an example to form redistribution circuit layer, a seed layer (not shown) is formed over the protective layer 104. In some embodiments, the seed layer is a metal layer, which .... remaining portions of the seed layer and conductive material form the redistribution circuit layer 106, 107”, see combination see Shigihara the layers of Cu, Ni, Au] the plurality of uppermost conductive interposer patterns and the plurality of conductive connection pads, the plurality of conductive pad seed layers respectively covering lower surfaces of the plurality of conductive connection pads.
In regard to claim 8 Chuang and Shigihara as combined teaches further comprising a plurality of conductive barrier layers disposed between [see combination see Shigihara the layers of Cu, Ni, Au, see also Chuang uses seed layers see paragraph 0018 “As an example to form redistribution circuit layer, a seed layer (not shown) is formed over the protective layer 104. In some embodiments, the seed layer is a metal layer, which .... remaining portions of the seed layer and conductive material form the redistribution circuit layer 106, 107” ] the plurality of uppermost conductive interposer patterns and the plurality of conductive connection pads, the plurality of conductive barrier layers respectively covering the upper surfaces of the plurality of uppermost conductive interposer patterns and respectively exposed through the plurality of pad holes.
In regard to claim 9 Chuang and Shigihara as combined does not specifically teach wherein: the plurality of conductive barrier layers have a first thickness in the vertical direction; the plurality of uppermost conductive interposer patterns have a second thickness in the vertical direction; and a ratio of the first thickness to the second thickness is in a range of about 1:1 to about 1:6.
However see sample thicknesses, see Shigihara “The thickness of the wiring M6 is, for example, 1 μm” “thickness of the Au seed layer 18 is, for example, 0.08 μm” “thickness of the first metal film 15 is 3 μm, for example, and the thickness of the second metal film 16 is 3 μm”.
The Examiner notes that a person of ordinary skill in the art is aware that cross sectional area of a conductor affects resistance.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein: the plurality of conductive barrier layers have a first thickness in the vertical direction; the plurality of uppermost conductive interposer patterns have a second thickness in the vertical direction; and a ratio of the first thickness to the second thickness is in a range of about 1:1 to about 1:6 ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 10 Chuang and Shigihara as combined teaches wherein the plurality of interposer redistribution structures further comprise a plurality of interposer seed layers [see Chuang uses seed layers see paragraph 0018 “As an example to form redistribution circuit layer, a seed layer (not shown) is formed over the protective layer 104. In some embodiments, the seed layer is a metal layer, which .... remaining portions of the seed layer and conductive material form the redistribution circuit layer 106, 107” ], each of the plurality of interposer seed layers covering a portion of a corresponding conductive interposer pattern [see Chuang Figs 1-11] of the plurality of conductive interposer patterns but does not state and a side surface and a lower surface of a corresponding conductive interposer via of the plurality of conductive interposer vias.
However see the redistribution of Chuang uses vias, see “structure 110 can include any number of dielectric layers, redistribution circuit layers, and vias” thus the seed layers are part of this redistribution.
See Shigihara also uses “wirings M2 to M5 are formed by a duel damascene method using, for example, Cu as a main conductor”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Chuang to include and a side surface and a lower surface of a corresponding conductive interposer via of the plurality of conductive interposer vias.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that the method of Chuang in Figs. 1-11 would naturally result in the seed forming between the layers and around the vias.
Claim(s) 11-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (US 20230369263 A1) hereafter referred to as Chuang in view of Shigihara et al. (JP 2008016514 A) hereafter referred to as Shigihara
In regard to claim 11 Chuang teaches a [see “FIG. 1 to FIG. 11 illustrate partial cross sectional views of intermediate stages in the manufacturing of a semiconductor package according to some embodiments”] semiconductor package comprising:
a base substrate [i.e. the portion of “package 200” below 112, 130] including a plurality of base redistribution [see connected to the 166 in Fig. 11, see Fig. 7] structures sequentially stacked in a vertical direction and a base insulation layer [see Fig. 7 “As illustrated in FIG. 7, the front side redistribution structure 160 includes dielectric layers 132, 140, 148, and 156 and metallization patterns 138, 146, and 154”], the plurality of base redistribution structures including a plurality of conductive base patterns and a plurality of [see the small vias in Fig. 7, Fig. 11] conductive base vias;
a semiconductor chip [“a plurality of integrated circuit dies 114 are adhered to the dielectric layer 108 by an adhesive 116”” “connectors 126 of the die 114”] attached on the base substrate by a plurality of chip connection members;
an interposer substrate [see including “backside redistribution structure, e.g., protective layer 104” “openings 1041, 1042 are formed through the protective layer 104 to reveal the functional pads 106 and a part of the dummy pad portions 107 of the redistribution circuit layer” “the redistribution circuit layer 106, 107 is formed over the protective layer 104. As an example to form redistribution circuit layer, a seed layer (not shown) is formed over the protective layer 104”] including a plurality of interposer redistribution structures [see Fig. 11, see connected to 314, and to 112] sequentially stacked in the vertical direction and an interposer insulation layer having an upper surface that includes a plurality of [“openings 1041, 1042 are formed through the protective layer 104 to reveal the functional pads 106 and a part of the dummy pad portions 107 of the redistribution circuit layer” ] pad holes, the interposer substrate is disposed on the semiconductor chip, the plurality of interposer redistribution structures including [see “As illustrated, the backside redistribution structure 110 includes the two dielectric layers 104 and 108 and one redistribution circuit layer 106, 107. In other embodiments, the back-side redistribution structure 110 can include any number of dielectric layers, redistribution circuit layers, and vias”] a plurality of conductive interposer patterns and a plurality of conductive interposer vias;
a plurality of conductive posts disposed around the semiconductor chip [see Fig. 11, “Referring now to FIG. 5, an encapsulating material 130 is formed over the dielectric layer 108 to at least laterally encapsulate the die 114 and the through vias 112 (and dummy through vias 113, if applicable)”] to extend in the vertical direction, the plurality of conductive posts connecting [see Fig. 11] the base substrate with the interposer substrate;
a molding layer [“encapsulating material 130”] disposed between the base substrate and the interposer substrate, the molding layer surrounding [see Fig. 11] the semiconductor chip and the plurality of conductive posts;
a plurality of conductive connection pads [106, 107] respectively disposed on a plurality of uppermost conductive interposer patterns [see Fig. 11, see 106 is on a via portion connected to 112 see “As illustrated, the backside redistribution structure 110 includes the two dielectric layers 104 and 108 and one redistribution circuit layer 106, 107. In other embodiments, the back-side redistribution structure 110 can include any number of dielectric layers, redistribution circuit layers, and vias”] of an uppermost interposer redistribution structure of the plurality of interposer redistribution structures and respectively disposed [see Fig. 11] in the plurality of pad holes; and
but does not state in Fig. 11 that: a plurality of conductive pad seed layers, each of the plurality of conductive pad seed layers is disposed between a corresponding uppermost conductive interposer pattern of the plurality of uppermost conductive interposer patterns and a corresponding conductive connection pad of the plurality of conductive connection pads, the plurality of conductive pad seed layers respectively covering lower surfaces of the plurality of conductive connection pads,wherein a side surface and an upper surface of each of the plurality of uppermost conductive interposer patterns and a side surface and an upper surface of each of the plurality of conductive connection pads are exposed by the interposer insulation layer.
See that in Chuang the redistribution circuit layer 106, 107 is part of “structure 110 can include any number of dielectric layers, redistribution circuit layers, and vias” so a portion of the upper surface is used as pad, and see that Chuang uses seed layers see paragraph 0018 “As an example to form redistribution circuit layer, a seed layer (not shown) is formed over the protective layer 104. In some embodiments, the seed layer is a metal layer, which .... remaining portions of the seed layer and conductive material form the redistribution circuit layer 106, 107”.
See Shigihara Fig. 5, Figs. 13-15, Fig. 19 see “first metal film 15 connected to the bonding pad part M6a through the first opening C1 is formed on the semiconductor substrate 1” “as shown in FIG. 5, the solder bump electrode 20 is formed on the upper surface of the UBM 17 through the second opening C2. The solder bump electrode 20 is an external connection electrode, and for example, lead-free solder is used. The solder bump electrode 20 can be formed by, for example, a printing method, a plating method, or a ball method. In the printing method, the solder paste is mask-printed on the UBM 17 via the Au seed layer 18, and then the solder paste is formed into a spherical shape by reflow processing and connected to the UBM 17” “Au seed layer 18 is selectively formed on the surface (upper surface and side surface) of the second metal film 16 constituting the upper layer of the UBM 17 by electroless plating. Au is easy to grow on the second metal film (representative material, for example, Ni film) 16, but Au on the first metal film (representative material, for example, Cu film) 15” see that a space is left around the pad.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Chuang to include an adhesion layer and additional UBM layers i.e. to modify Chuang to include that: a plurality of conductive pad seed layers, each of the plurality of conductive pad seed layers is disposed between a corresponding uppermost conductive interposer pattern of the plurality of uppermost conductive interposer patterns and a corresponding conductive connection pad of the plurality of conductive connection pads, the plurality of conductive pad seed layers respectively covering lower surfaces of the plurality of conductive connection pads,wherein a side surface and an upper surface of each of the plurality of uppermost conductive interposer patterns and a side surface and an upper surface of each of the plurality of conductive connection pads are exposed by the interposer insulation layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is the obtain maximum contact for good conduction.
In regard to claim 12 Chuang and Shigihara as combined teaches wherein: each of the plurality of pad holes has a tapered [see Chuang Fig. 11 see side of 104, see combination] shape, wherein a horizontal cross- sectional area of each of the plurality of pad holes narrows progressively [see Chuang Fig. 11 see side of 104, see combination] towards a bottom surface of each of the plurality of pad holes from an inlet of each of the plurality of pad holes; and the plurality of uppermost conductive interposer patterns are respectively disposed [see Chuang Fig. 11 , see combination] on the bottom surfaces of the plurality of pad holes.
In regard to claim 13 Chuang and Shigihara as combined teaches wherein a plurality of uppermost conductive base patterns of an uppermost base redistribution structure of the plurality of base redistribution structures are disposed on an upper surface [see Chuang Fig. 11 see “connectors 126 of the die 114” see redistribution connected to 114, see “encapsulating material 130”] of the base insulation layer and are surrounded by the molding layer.
In regard to claim 14 Chuang and Shigihara as combined teaches further comprising a plurality of conductive barrier layers [see combination see Shigihara the layers of Cu, Ni, Au, see also Chuang uses seed layers see paragraph 0018 “As an example to form redistribution circuit layer, a seed layer (not shown) is formed over the protective layer 104. In some embodiments, the seed layer is a metal layer, which .... remaining portions of the seed layer and conductive material form the redistribution circuit layer 106, 107” ], each of the plurality of conductive barrier layers is disposed between a corresponding conductive pad seed layer of the plurality of conductive pad seed layers and a corresponding uppermost conductive interposer pattern of the plurality of uppermost conductive interposer patterns, the plurality of conductive barrier layers respectively covering the upper surfaces of the plurality of uppermost conductive interposer patterns.
In regard to claim 15 Chuang and Shigihara as combined teaches wherein the upper surface of the interposer insulation layer is disposed at a height from an upper surface of the base substrate in the vertical direction that is greater than [this is true, see Chuang Fig. 11, see combination see Shigihara Fig. 5, Fig. 19] or equal to a height of the upper surfaces of the plurality of conductive connection pads from the upper surface of the base substrate in the vertical direction.
Claim(s) 17, 19, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (US 20230369263 A1) hereafter referred to as Chuang in view of Shigihara et al. (JP 2008016514 A) hereafter referred to as Shigihara
In regard to claim 17 Chuang teaches a [see “FIG. 1 to FIG. 11 illustrate partial cross sectional views of intermediate stages in the manufacturing of a semiconductor package according to some embodiments”] semiconductor package comprising:
a first base substrate [i.e. the portion of “package 200” below 112, 130];
a first semiconductor chip [“a plurality of integrated circuit dies 114 are adhered to the dielectric layer 108 by an adhesive 116”” “connectors 126 of the die 114”] attached on the first base substrate;
a plurality of conductive posts [see Fig. 11, “Referring now to FIG. 5, an encapsulating material 130 is formed over the dielectric layer 108 to at least laterally encapsulate the die 114 and the through vias 112 (and dummy through vias 113, if applicable)”] disposed around the first semiconductor chip, on the first base substrate;
an interposer substrate [see including “backside redistribution structure, e.g., protective layer 104” “openings 1041, 1042 are formed through the protective layer 104 to reveal the functional pads 106 and a part of the dummy pad portions 107 of the redistribution circuit layer” “the redistribution circuit layer 106, 107 is formed over the protective layer 104. As an example to form redistribution circuit layer, a seed layer (not shown) is formed over the protective layer 104”] including an interposer redistribution structure [see Fig. 11, see connected to 314, and to 112] having a conductive interposer pattern, [see “As illustrated, the backside redistribution structure 110 includes the two dielectric layers 104 and 108 and one redistribution circuit layer 106, 107. In other embodiments, the back-side redistribution structure 110 can include any number of dielectric layers, redistribution circuit layers, and vias”] a conductive interposer via and an interposer insulation layer, the interposer insulation layer having an upper surface including a pad hole [“openings 1041, 1042 are formed through the protective layer 104 to reveal the functional pads 106 and a part of the dummy pad portions 107 of the redistribution circuit layer” ] exposing the conductive interposer pattern, the interposer substrate is electrically connected with [see Fig. 11] the first base substrate through the plurality of conductive posts;
a second base substrate [see paragraph 0045 “referring to FIG. 10 and FIG. 11, a substrate 300 may be mounted on the first package 100 through a plurality of connectors 314, 316 to form a semiconductor package 500 shown in FIG. 11”] on the interposer substrate;
a second semiconductor chip [“In some embodiments, the substrate 300 may include an interposer, a redistribution structures, or other mounting surface, with one or more dies disposed thereon”] attached on the second base substrate;
a conductive connection pad [see Fig. 11 see that 314 is connected to pad 106, 107 see “openings 1041, 1042 are formed through the protective layer 104 to reveal the functional pads 106 and a part of the dummy pad portions 107 of the redistribution circuit layer” ] disposed on the conductive interposer pattern [see Fig. 11, see 106 is on a via portion connected to 112 see “As illustrated, the backside redistribution structure 110 includes the two dielectric layers 104 and 108 and one redistribution circuit layer 106, 107. In other embodiments, the back-side redistribution structure 110 can include any number of dielectric layers, redistribution circuit layers, and vias”], in the pad hole; and
an external connection terminal [“In some embodiments, the connectors includes a plurality of functional connectors 314 and a plurality of dummy connectors 316 electrically disconnected from the functional connectors 314”] disposed on the conductive connection pad, the external connection terminal electrically connecting [“substrate 300 is in electrical communication with the functional pads 106 through the functional connectors 314. The connectors 314, 316 may include, for example, solder balls, conductive bumps, pillars, studs, or another conductive structure”] the interposer substrate with the second base substrate, wherein an inner sidewall of the pad hole is inclined [see Fig. 11, see side of 104 in the openings] with respect to an upper surface of the interposer insulation layer,
but does not teach the inner sidewall of the pad hole is spaced apart from the conductive connection pad and the conductive interposer pattern in a first horizontal direction.
See that in Chuang the redistribution circuit layer 106, 107 is part of “structure 110 can include any number of dielectric layers, redistribution circuit layers, and vias” so a portion of the upper surface is used as pad, and see that Chuang uses seed layers see paragraph 0018 “As an example to form redistribution circuit layer, a seed layer (not shown) is formed over the protective layer 104. In some embodiments, the seed layer is a metal layer, which .... remaining portions of the seed layer and conductive material form the redistribution circuit layer 106, 107”.
See Shigihara Fig. 5, Figs. 13-15, Fig. 19 see “first metal film 15 connected to the bonding pad part M6a through the first opening C1 is formed on the semiconductor substrate 1” “as shown in FIG. 5, the solder bump electrode 20 is formed on the upper surface of the UBM 17 through the second opening C2. The solder bump electrode 20 is an external connection electrode, and for example, lead-free solder is used. The solder bump electrode 20 can be formed by, for example, a printing method, a plating method, or a ball method. In the printing method, the solder paste is mask-printed on the UBM 17 via the Au seed layer 18, and then the solder paste is formed into a spherical shape by reflow processing and connected to the UBM 17” “Au seed layer 18 is selectively formed on the surface (upper surface and side surface) of the second metal film 16 constituting the upper layer of the UBM 17 by electroless plating. Au is easy to grow on the second metal film (representative material, for example, Ni film) 16, but Au on the first metal film (representative material, for example, Cu film) 15” see that a space is left around the pad.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Chuang to include that the inner sidewall of the pad hole is spaced apart from the conductive connection pad and the conductive interposer pattern in a first horizontal direction.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to make a good connection by increasing contact area.
In regard to claim 19 Chuang and Shigihara as combined teaches further comprising: a conductive barrier layer [see combination, see the layer structure in Shigihara see Au 18 on Ni 16 on Cu 15 on the bonding pad part M6a ] disposed between the conductive interposer pattern and the conductive connection pad, the conductive barrier layer covering an upper surface of the conductive interposer pattern; and the external connection terminal covers an upper surface of the conductive barrier layer.
In regard to claim 20 Chuang and Shigihara as combined teaches wherein an upper surface of the interposer insulation layer is disposed at a height from the interposer substrate in a vertical direction that is greater [this is true, see Chuang Fig. 11, see combination see Shigihara Fig. 5, Fig. 19] than or equal to a height of an upper surface of the conductive connection pad from the interposer substrate in the vertical direction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893