DETAILED ACTION
Claims 1 – 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9-12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Laslo (US Publication 2023/0006676 A1) in view of Devineni et al (US Publication 10,084,559 B1).
The teachings of Laslo as disclosed in the previous office action are hereby
incorporated by reference to the extent applicable to the amended claims.
Applicant has amended independent claim 1 to incorporate the limitations that (1) the first clock domain being a system clock domain, the second clock domain being a physical layer clock domain, and circuitry of both the first clock domain and the second clock domain both being coupled to a port of the network device that receives a Time of Day timestamp.
Regarding limitation (1), Laslo does not disclose (1) first clock domain being a system clock domain, the second clock domain being a physical layer clock domain, and circuitry of both the first clock domain and the second clock domain both being coupled to a port of the network device that receives a Time of Day timestamp.
However, Devineni discloses (1) first clock domain being a system clock domain [Fig. 18, abstract: local clock], the second clock domain being a physical layer clock domain [abstract, figure 18: PHY clock domain], and circuitry of both the first clock domain and the second clock domain both being coupled to a port of the network device that receives a Time of Day timestamp [Col. 19 lines 18 – lines 64: Time of Day (ToD) at the port].
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Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lalso and Devineni together because they both directed to measure the clock difference between two clocks. Devineni’s teachings of the circuitry coupled to both local clock domain, PHY clock domain to receive the Time of Day timestamp would allow Lalso to adjust the second clock domain based on the received Time of Day timestamp.
Regarding claims 2 – 6, 9-11, the base claim 1 is taught by Lalso and Devineni above and the additional limitations are taught by Lalso as disclosed in the previous office action.
Regarding claim 5, Devineni discloses the method of claim 1 wherein the network device implements a Precision Time Protocol [Col. 19 lines 18 – lines 64].
Claims 12 and 16 are rejected for the same reasons as set forth in claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lalso (US Publication 2023/0006676 A1) and in view of Devineni et al (US Publication 10,084,559 B1) and in further view of Moorman et al (US Patent 5,041,798).
Regarding claim 7, Lalso and Devineni do not disclose the method of claim 6 wherein the first Time of Day counter receives a first reference clock signal having an adjustable frequency, and the second counter receives a second reference clock signal having a fixed frequency.
Moorman discloses a first counter [Fig. 4, reference counter 80] receives a first reference clock signal having an adjustable frequency [adjustable frequency from a reference oscillator 82], and the second counter [Tod counter 74] receives a second reference clock signal having a fixed frequency [fixed frequency from a clock source B].
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Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lalso, Devineni and Moorman together because they directed to use two different counters to count different clock signals. Moorman’s disclosing of using the adjustable frequency for the first counter and using the fixed frequency for the second counter would allow Lalso in view of Devineni to make it easier for adjusting the clock signal coming in to the second counter.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lalso (US Publication 2023/0006676 A1) in view of Devineni et al (US Publication 10,084,559 B1) and in further view of Ozyurt et al (US Publication 2024/0007213 A1).
Regarding claim 8, Lalso and Devineni do not disclose determining, in the first clock domain, a Time of Day timestamp from packet received from a master network device at a port of the network device [0071: the master device 200 may encode a timestamp t1 representative of a current clock time of the master device 200 using the color-based optical coding scheme (an RGB-based scheme in the shown example) and send, using optical wireless signals, in step S810, the timestamp t1 to the slave device 210].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lalso, Devineni and Ozyurt together because they directed to use two different counters to count different clock signals. Ozyurt’s disclosing of determining, in the first clock domain, a Time of Day timestamp from packet received from a master network device at a port of the network device would allow Lalso in view of Devineni to align the phases between the master and slave devices in the network.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 12, 13, 16-20 are rejected under AIA 35 U.S.C. 102(a)(2) as being anticipated by
Dror (US Publication 20230269063A1).
Regarding claim 12, Dror discloses an error measurement circuit comprising: a system input node configured to receive a first phase indicator from a first clock domain of a network device; a second input node configured to receive a second phase indicator from a physical clock domain of the network device; and an output node configured to provide an error signal indicative of a phase measurement that is based on the first phase indicator and the second phase indicator [local clock domain 176][0053: The local-domain clock 176 and the local-domain clocks 180 are free running clocks maintained at the IC chip 140 and the PHY processors 124, respective, using respective counters]; phase measurement representing a difference between a Time of Day in the physical layer clock domain and a Time of Day in the system clock domain [0053: FIG. 1, the domain-specific clocks 152 are maintained at the network device 100 using counters that are continually incremented and adjusted to maintain accurate clocks (e.g., time of day clocks) in the respective ones of the multiple synchronization domains maintained by the network device 100. The local-domain clock 176 and the local-domain clocks 180 are free running clocks maintained at the IC chip 140 and the PHY processors 124, respective, using respective counters that are utilized only for determining the internal delays in the network device 100, in an embodiment. In some embodiments, the counters utilized to maintain the domain-specific clocks 152 at the network device 100 are larger (e.g., have larger numbers of bits) as compared to the counters utilized to maintain the local-domain clock 176 and the local-domain clocks 180 at the network device 100, in an embodiment. As a more specific example, the counters utilized to maintain the domain specific clocks 152 utilize 48 bits to maintain seconds and 32 bits to maintain nanoseconds of the domain-specific clocks 152. On the other hand, the counters utilized to maintain local-domain clock 176 and the local-domain clocks 180 utilizes only 1 or 2 bits to maintain seconds and 30 bits to maintain nanoseconds of the local-domain clock] [0045] [0062-0063: determines the delay experienced by the timing message 200 based on a difference between the first timestamp generated for the timing message 200 by the PHY processor 124-1 and the current value of the local-domain clock 176 at a time] [0095-0096].
Regarding claim 13, Dror discloses the error measurement circuit of claim 12 wherein the error measurement circuit is included in an integrated circuit having a first input contact and a second input contact, the first input node being at the first input contact, and the second input node being at the second input contact [0045] [0053] [0062-0063] [0095-0096].
Regarding claim 16, Dror discloses a network device [Fig. 1] comprising:
a port for connecting with a second network device [port 104];
system clock domain circuitry operatively connected to the port, the system clock domain circuitry including a first Time of Day counter configured to receive a first reference clock [local clock domain 176] [0053: The local-domain clock 176 and the local-domain clocks 180 are free running clocks maintained at the IC chip 140 and the PHY processors 124, respective, using respective counters];
physical layer clock domain circuitry including a second counter configured to receive a second reference clock, the second reference clock having a different frequency than the first reference clock [0053: FIG. 1, the domain-specific clocks 152 are maintained at the network device 100 using counters that are continually incremented and adjusted to maintain accurate clocks (e.g., time of day clocks) in the respective ones of the multiple synchronization domains maintained by the network device 100. The local-domain clock 176 and the local-domain clocks 180 are free running clocks maintained at the IC chip 140 and the PHY processors 124, respective, using respective counters],
the physical layer clock domain circuitry configured to reduce mismatch between outputs of the first Time of Day counter and the second counter based on an error signal indicative of a phase measurement of mismatch between the outputs of the first Time of Day counter and the second counter [0053: FIG. 1, the domain-specific clocks 152 are maintained at the network device 100 using counters that are continually incremented and adjusted to maintain accurate clocks (e.g., time of day clocks) in the respective ones of the multiple synchronization domains maintained by the network device 100. The local-domain clock 176 and the local-domain clocks 180 are free running clocks maintained at the IC chip 140 and the PHY processors 124, respective, using respective counters that are utilized only for determining the internal delays in the network device 100, in an embodiment. In some embodiments, the counters utilized to maintain the domain-specific clocks 152 at the network device 100 are larger (e.g., have larger numbers of bits) as compared to the counters utilized to maintain the local-domain clock 176 and the local-domain clocks 180 at the network device 100, in an embodiment. As a more specific example, the counters utilized to maintain the domain specific clocks 152 utilize 48 bits to maintain seconds and 32 bits to maintain nanoseconds of the domain-specific clocks 152. On the other hand, the counters utilized to maintain local-domain clock 176 and the local-domain clocks 180 utilizes only 1 or 2 bits to maintain seconds and 30 bits to maintain nanoseconds of the local-domain clock]; and
an error measurement circuit in communication with the system clock domain circuitry and the physical layer clock domain circuitry, the error measurement circuit configured to generate the error signal [0045] [0053] [0062-0063: determines the delay experienced by the timing message 200 based on a difference between the first timestamp generated for the timing message 200 by the PHY processor 124-1 and the current value of the local-domain clock 176 at a time] [0095-0096].
Regarding claim 17, Dror discloses the network device of claim 16 wherein the port is an Ethernet port [0045] [0053] [0062-0063] [0095-0096].
Regarding claim 19, Dror discloses the network device of claim wherein the first Time of Day counter and the second counter have different increment values. clock domain circuitry is a system clock domain circuitry, and the second clock domain circuitry is physical layer clock domain circuitry [0045] [0053] [0062-0063] [0095-0096].
Regarding claim 20, Dror discloses the network device of claim 16 wherein the first clock domain circuitry is a system clock domain circuitry, and the second physical layer clock domain circuitry is Synchronous Ethernet clock domain circuitry [0045] [0053] [0062-0063] [0095-0096].
Claim 1 is rejected for the same reason set forth in claim 12 or claim 16.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Dror (US Publication 20230269063A1) and in view of Meninger et al (US Patent 9,698,808 B1).
Regarding claim 14, Dror does not disclose wherein the integrated circuit includes a circuit having a frequency in a range from 8 gigahertz to 12 gigahertz.
Meninger discloses wherein the integrated circuit includes a circuit having a frequency in a range from 8 gigahertz to 12 gigahertz [Col. 4 lines 55-58: the circuit can adjust the phase of high-frequency (e.g., multi-GHz) clocks with picosecond accuracy, and can accurately detect even a minimal phase difference between the clocks].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Dror and Meninger together because they both directed to determine the phase difference between clock signals. Meninger’s disclosing of the circuit 100 can measure the phase difference between two clocks in a range of multi-gigahertz would allow Dror to incorporate the measurement into the highspeed network.
Regarding claim 15, Meninger discloses wherein the error measurement circuit is configured to determine a difference between the first phase indicator and the second phase indicator to an accuracy within 100 picoseconds [Col. 4 lines 55-58: the circuit can adjust the phase of high-frequency (e.g., multi-GHz) clocks with picosecond accuracy, and can accurately detect even a minimal phase difference between the clocks].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Dror (US Publication 20230269063A1) in view of Moorman et al (US Patent 5,041,798).
Regarding claim 18, Dror does not disclose the network device of claim 16 wherein the first Time of Day counter has a fixed increment, and the second counter has an adjustable increment [Fig.4].
Moorman discloses the network device of claim 16 wherein the first Time of Day counter has a fixed increment, and the second counter has an adjustable increment [Fig.4].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Dror and Moorman together because they both directed to use two different counters to count different clock signals. Moorman’s disclosing of wherein the first Time of Day counter has a fixed increment, and the second counter has an adjustable increment would allow Dror to make it easier for adjusting the clock signal coming in to the second counter.
Response to Arguments
Applicant’s arguments filed on 07/24/2025 have been fully considered but are moot in view of new ground(s) of rejection because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Examiner's note: Examiner has cited particular paragraphs and columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner (see MPEP § 2123).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHIL K NGUYEN whose telephone number is (571)270-3356. The examiner can normally be reached 9:30 a.m - 5 p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHIL K NGUYEN/Primary Examiner, Art Unit 2176