DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:7
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 11, 15-17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, US PGPub 2023/0080284, in view of Hoshino et al., US PGPub 2024/0069723.
With respect to claim 1, Lee teaches storage controller comprising:
a host block circuit formed at a first die and configured to communicate with a host device through a first interface (pars. 58-60 and fig. 10, the front end chip 400 is the host block circuit, and the host interface 410 is the first interface); and
a plurality of media block circuits formed at least one third die and configured to communicate with a plurality of media devices through a second interface for controlling a plurality of media devices (pars. 58-60 and fig. 10, the back-end chips 500 and 600 are the media block circuits, controlling the respective memory (media) devices. The back-end chips are chiplets separate from the front-end chiplet, and are thus are formed at at least one third die. The second interface is the connection between the back-end chips and the memory devices),
wherein the plurality of media devices are configured to constitute a plurality of channels (pars. 58-60 and fig. 10, a plurality of channels are shown, particularly the channel between the back-end chip 500 and the first memory device, and the channel between the back-end chip 600 and the second memory device),
wherein each of the plurality of media block circuits is connected to a corresponding channel of the plurality of channels (pars. 58-60 and fig. 10, a plurality of channels are shown, particularly the channel between the back-end chip 500 and the first memory device, and the channel between the back-end chip 600 and the second memory device), and
wherein the host block circuit and the plurality of media block circuits are connected with each other through a chiplet interface (par. 59 and fig. 10, the front-end chip, first back-end chip and second back-end chip are configured in a chiplet structure, connected through an interface).
Lee fails to teach, in one single embodiment, outputting a read command and receiving data through a NAND flash interface. Hoshino teaches:
wherein each media block circuit of the plurality of media block circuits is configured to:
output a read command to a corresponding media device of the plurality of media devices through the second interface (par. 66, the NAND controller outputs a read command to the flash), and
receive read data from the corresponding media device through the second interface (par. 71, the data is read from the flash memory),
wherein the second interface includes a NAND flash interface (par. 43 and fig. 1, the NAND interface).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee and Hoshino before him before the earliest effective filing date, to modify the storage system of Lee with the storage system of Hoshino, as the use of a NAND flash interface allows the management of the endurance of the memory system, as taught by Hoshino in par. 65.
With respect to claim 2, Lee and Hoshino teach all limitations of the parent claim. Lee further teaches the storage controller of claim 1, wherein the first die and the at least one third die are formed on a package board (par. 58 and fig. 10, storage architecture 100b is the package board that the first and third dies are formed on).
With respect to claim 11, Lee and Hoshino teach all limitations of the parent claim. Lee further teaches a storage device comprising:
at least one nonvolatile memory device (par. 57 and fig. 19, the flash memory device); and
a controller configured to control the at least one nonvolatile memory device (par. 57 and fig. 9, flash controller 386), wherein the controller includes:
a host interface circuit formed at a first die and connected to a host device (pars. 58-60 and fig. 10, host interface 410 formed at first die 410 and connected to the host device) and
a nonvolatile memory interface circuit formed at a third die and connected to the at least one nonvolatile memory device (pars. 57-60 and fig. 10, the back-end chip 500 is at a third die and connected to a first memory device, which corresponds to the flash memory of fig. 9), and
wherein the host interface circuit formed at the first die and the nonvolatile memory interface circuit formed at the third die are configured to communicate with each other using a chiplet interface (par. 59 and fig. 10, the front-end chip, first back-end chip and second back-end chip are configured in a chiplet structure, connected through an interface).
Lee fails to disclose using an interface including a NAND flash interface, and wherein the nonvolatile memory interface circuit is configured to: output a read command to a corresponding nonvolatile memory device of the at least one nonvolatile memory device, and receive read data from the corresponding nonvolatile memory device. Hoshino teaches:
using an interface including a NAND flash interface (par. 83 and fig. 1, the NAND interface), and
wherein the nonvolatile memory interface circuit is configured to:
output a read command to a corresponding nonvolatile memory device of the at least one nonvolatile memory device (par. 66, the NAND controllers output a read commands to corresponding flash dies), and
receive read data from the corresponding nonvolatile memory device (par. 71, the data is read from the flash memory).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee and Hoshino before him before the earliest effective filing date, to modify the storage system of Lee with the storage system of Hoshino, as the use of a NAND flash interface allows the management of the endurance of the memory system, as taught by Hoshino in par. 65.
With respect to claim 15, Lee and Hoshino teach all limitations of the parent claim. Lee further teaches the storage device of claim 11, wherein the at least one nonvolatile memory device is implemented in a stacked package form (par. 49).
With respect to claim 16, Lee teaches a method of operating a storage device, the method comprising:
receiving a write request from a host device by a host interface circuit formed at a first die (pars. 57-58 and fig. 10, write requests are received from the host device at host interface circuit 410 formed at first die front-end chip 400);
transmitting the write request to a nonvolatile memory interface circuit formed at a third die through a second chiplet interface (pars. 57-60 and fig. 10 memory operations are transmitted to back-end chip 500 through a second interface from front-end chip 400); and
outputting a program command corresponding to the write request to at least one nonvolatile memory device by the nonvolatile memory interface circuit (pars. 57-60, memory operations are issued to the first memory device, which as shown in fig. 9 may be a nonvolatile flash memory, through flash controller 386).
Lee fails to teach receiving write completion information from the at least one nonvolatile Lee memory device by the nonvolatile memory interface circuit. Hoshino teaches:
receiving, by the host interface circuit, write completion information from the at least one nonvolatile memory device by the nonvolatile memory interface circuit (pars. 103-104 and fig. 1, data is written to a write destination block in flash memory, which as shown in fig. 1, is over NAND interface 53, and write completion information is received, as the management information in DRAM 7 is updated).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee and Hoshino before him before the earliest effective filing date, to modify the storage system of Lee with the storage system of Hoshino, as the use of a NAND flash interface allows the management of the endurance of the memory system, as taught by Hoshino in par. 65.
With respect to claim 17, Lee and Hoshino teach all limitations of the parent claim. Hoshino further teaches the method of claim 16, further comprising:
transmitting write data from the host interface circuit to error correction circuit (ECC) formed at a second die through a first interface (par. 46);
generating, by the ECC, an encoded data including parity bits by performing error correction encoding of the write data (par. 46); and
outputting the encoded data to the at least one nonvolatile memory device by the nonvolatile memory interface circuit (par. 46).
Lee teaches a first chiplet interface (par. 59),
With respect to claim 20, Lee and Hoshino teach all limitations of the parent claim. Lee further teaches the method of claim 17, further comprising: transmitting the write completion information to the host interface circuit through a third chiplet interface by the nonvolatile memory interface circuit (par. 49, the write operation is an access operation).
Claim(s) 3-9 and 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee and Hoshino as applied to claim 1 above, and further in view of Hornung et al., US PGPub 2022/0066869.
With respect to claim 3, Lee and Hoshino teach all limitations of the parent claim but fail to teach an ECC circuit formed at a third die. Hornung further teaches the storage controller of claim 1, further comprising:
an error correction circuit (ECC) formed at a third die and configured to communicate with the host block circuit through a first chiplet interface and each of the plurality of media block circuits through a second chiplet interface (par. 23 and fig. 1b, memory controller chiplet 140 performs error correction and communicates with the host block circuit 135 through first chiplet interface 160, and communicates with the plurality of media block circuits 150).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee, Hoshino and Hornung before him before the earliest effective filing date, to modify the storage system of Lee and Hoshino with the storage system of Hornung, in order to facilitate error correction in a manner to minimize the need to interrupt a sequence of data reads to write corrected data from a prior read back into the storage array, as taught by Hornung in par. 10.
With respect to claim 4, Lee, Hoshino and Hornung teach all limitations of the parent claim. Hornung further teaches the storage controller of claim 3,
wherein the first chiplet interface and the second chiplet interface are compatible to Advanced Interface Bus (AIB) Protocol (par. 14).
With respect to claim 5, Lee, Hoshino and Hornung teach all limitations of the parent claims. Hornung further teaches the storage controller of claim 3, wherein the host block circuit transmits write data to the ECC through the first chiplet interface (par. 23, write data is through chiplet mesh 160).
With respect to claim 6, Lee, Hoshino and Hornung teach all limitations of the parent claims. Hornung further teaches the storage controller of claim 5, wherein encoded data generated by the ECC based on the write data is transmitted to the plurality of media block circuits through the second chiplet interface (par. 23, the error correction is performed through memory interface 145).
With respect to claim 7, Lee, Hoshino and Hornung teach all limitations of the parent claims. Lee further teaches the storage controller of claim 6, wherein write completion information is transmitted from the plurality of media block circuits to the host block circuit through a third chiplet interface (par. 49).
With respect to claim 8, Lee, Hoshino and Hornung teach all limitations of the parent claims. Hornung further teaches the storage controller of claim 3, wherein a read request is transmitted from the host block circuit to the plurality of media block circuits through a fourth chiplet interface (par. 23 and fig. 2, reads occur through another interface to off-die memory 275).
With respect to claim 9, Lee, Hoshino and Hornung teach all limitations of the parent claim. Hornung further teaches the storage controller of claim 8, wherein read data is transmitted from the plurality of media block circuits to the ECC through the second chiplet interface, and a decoded data generated by the ECC based on the read data is transmitted to the host block circuit through the first chiplet interface (pars. 46-49).
Claims 12-13 correspond to claims 3-4, and are rejected using similar logic.
With respect to claim 14, Lee, Hoshino and Hornung teach all limitations of the parent claims. Lee further teaches the storage device of claim 12, further comprising:
a volatile memory device (par. 49, the DRAM),
wherein the controller further includes a volatile memory controller formed at the second die and configured to control an operation of the volatile memory device (par. 49, the DRAM controller).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee and Hoshino as applied to claim 1 above, and further in view of He et al., US PGPub 2023/0153143.
With respect to claim 10, Lee and Hoshino teach all limitations of the parent claim, but fail to teach a UCIe. He further teaches the storage controller of claim 1, wherein the chiplet interface includes a Universal Chiplet Interconnect Express (UCIe) interface (par. 17).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee, Hoshino and He before him before the earliest effective filing date, to modify the storage system of Lee and Hoshino with the storage system of He, in order to facilitate connection of peripheral devices on the platform, as taught by He in par. 56.
Response to Arguments
Applicant's arguments filed 12/01/2025 have been fully considered but they are not persuasive. Applicant’s arguments on pages 3-5, with respect to independent claim 1, are directed towards Chritz failing to teach the cited limitations. These arguments are moot, as Chritz is no longer being relied upon to teach the amended claim. The new Lee reference teaches a third die distinct from first and second dies. Applicant’s arguments on page 5, with respect to independent claim 11 are moot, as the new Lee reference teaches the cited limitations. Applicant’s arguments on page 16, with respect to independent claim 16, are moot, as the new Lee reference is used to teach the cited limitations. Applicant’s arguments on page 6, regarding dependent claims 7 and 15 as patentable as depending from claims 1 and 11 are also moot, as claims 1 and 15 are newly rejected under Lee and Hoshino.
Conclusion
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/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132